aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer1-0/+5
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-0/+14
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich1-0/+5
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-0/+7
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra1-0/+9
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-0/+10
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-0/+13
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-0/+9
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich1-0/+6
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-0/+6
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-0/+14
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-0/+18
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen1-0/+4
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus1-0/+5
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra1-0/+4
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich1-0/+4
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich1-0/+7
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich1-0/+5
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-0/+21
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich1-0/+21
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-0/+19
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-0/+10
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-0/+67
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich1-0/+99
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich1-0/+34
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich1-0/+15
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich1-0/+16
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-0/+19
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-0/+7
2021-03-03x86: infer operand count of templatesJan Beulich1-0/+7
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-0/+15
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-0/+7
2021-02-17read_leb128 overflow checkingAlan Modra1-0/+7
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich1-0/+5
2021-02-16x86: have preprocessor expand macrosJan Beulich1-0/+6
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel1-0/+5
2021-02-10bfd, opcodes, libctf: support --with-included-gettextNick Alcock1-0/+6
2021-02-08opcodes: tic54x: namespace exported variablesMike Frysinger1-0/+18
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu1-0/+6
2021-01-26Segmentation fault i386-genAlan Modra1-0/+5
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu1-0/+7
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-0/+4
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-0/+5
2021-01-13Regen Makefile.in for jobserver.m4 aclocal.m4 dependencyAlan Modra1-0/+4
2021-01-12Implement a workaround for GNU mak jobserverH.J. Lu1-0/+7
2021-01-12Updated translations for some subdirectoriesNick Clifton1-0/+4
2021-01-11Binutils: Check if AR works with --plugin and rcH.J. Lu1-0/+5
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-0/+12
2021-01-11Updated translations for multiple subdirectoriesNick Clifton1-0/+8
2021-01-09Binutils: Pass --plugin to AR and RANLIBH.J. Lu1-0/+4
generated by cgit v1.1 at 2025-02-21 12:52:15 +0000