| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-05-14 | A series of fixes to addres problems detected by compiling the assembler with... | Nick Clifton | 1 | -0/+6 |
| 2019-05-10 | Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6 | Faraz Shahbazker | 1 | -0/+5 |
| 2019-05-11 | PowerPC objdump -Mraw | Alan Modra | 1 | -0/+5 |
| 2019-05-09 | [binutils][aarch64] Add SVE2 instructions. | Matthew Malcomson | 1 | -0/+30 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+11 |
| 2019-05-09 | [binutils][aarch64] New sve_size_tsz_bhs iclass. | Matthew Malcomson | 1 | -0/+7 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 1 | -0/+12 |
| 2019-05-09 | [binutils][aarch64] New sve_shift_tsz_bhsd iclass. | Matthew Malcomson | 1 | -0/+7 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+16 |
| 2019-05-09 | [binutils][aarch64] New sve_size_013 iclass. | Matthew Malcomson | 1 | -0/+7 |
| 2019-05-09 | [binutils][aarch64] New sve_size_bh iclass. | Matthew Malcomson | 1 | -0/+7 |
| 2019-05-09 | [binutils][aarch64] New sve_size_sd2 iclass. | Matthew Malcomson | 1 | -0/+9 |
| 2019-05-09 | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 1 | -0/+10 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 1 | -0/+13 |
| 2019-05-09 | [binutils][aarch64] New iclass sve_size_hsd2. | Matthew Malcomson | 1 | -0/+9 |
| 2019-05-09 | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 1 | -0/+12 |
| 2019-05-09 | [binutils][aarch64] Allow movprfx for SVE2 instructions. | Matthew Malcomson | 1 | -0/+5 |
| 2019-05-09 | [binutils][aarch64] SVE2 feature extension flags. | Matthew Malcomson | 1 | -0/+11 |
| 2019-05-06 | Add load-link, store-conditional paired EVA instructions | Faraz Shahbazker | 1 | -0/+10 |
| 2019-05-01 | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 1 | -0/+13 |
| 2019-04-29 | S12Z: Opcodes: Fix crash when trying to decode a truncated operation. | John Darrington | 1 | -0/+4 |
| 2019-04-26 | [MIPS] Add load-link, store-conditional paired instructions | Andrew Bennett | 1 | -0/+5 |
| 2019-04-24 | S12Z: Opcodes: Handle bit map operations with non-canonical operands. | John Darrington | 1 | -0/+5 |
| 2019-04-24 | S12Z: s12z-opc.h: Add extern "C" bracketing | John Darrington | 1 | -0/+5 |
| 2019-04-15 | [binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers | Andre Vieira | 1 | -0/+8 |
| 2019-04-15 | [binutils, ARM, 15/16] Add support for VSCCLRM | Andre Vieira | 1 | -0/+6 |
| 2019-04-15 | [opcodes, ARM, 14/16] Add mode availability to coprocessor table entries | Andre Vieira | 1 | -0/+9 |
| 2019-04-15 | [binutils, ARM, 13/16] Add support for CLRM | Andre Vieira | 1 | -0/+6 |
| 2019-04-15 | [binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma... | Andre Vieira | 1 | -0/+5 |
| 2019-04-15 | [binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline | Andre Vieira | 1 | -0/+5 |
| 2019-04-15 | [binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_... | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline | Andre Vieira | 1 | -0/+6 |
| 2019-04-15 | [binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM... | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo... | Andre Vieira | 1 | -0/+4 |
| 2019-04-15 | [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI | Andre Vieira | 1 | -0/+4 |
| 2019-04-12 | S12Z: opcodes: Replace "operator" with "optr". | John Darrington | 1 | -0/+5 |
| 2019-04-11 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 1 | -0/+13 |
| 2019-04-11 | [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction | Sudakshina Das | 1 | -0/+7 |
| 2019-04-09 | [MIPS] Add RDHWR with the SEL field for MIPS R6. | Robert Suchanek | 1 | -0/+4 |
| 2019-04-08 | x86: Consolidate AVX512 BF16 entries in i386-opc.tbl | H.J. Lu | 1 | -0/+5 |
| 2019-04-07 | print_insn_powerpc tidy | Alan Modra | 1 | -0/+6 |
| 2019-04-07 | PR24421, Wrong brackets in opcodes/arm-dis.c | Alan Modra | 1 | -0/+6 |
| 2019-04-05 | x86: Support Intel AVX512 BF16 | Xuepeng Guo | 1 | -0/+14 |
| 2019-04-05 | PowerPC bc extended branch mnemonics and "y" hints | Alan Modra | 1 | -0/+7 |
| 2019-04-05 | PowerPC disassembler: Don't emit trailing spaces | Alan Modra | 1 | -0/+5 |
| 2019-04-04 | Add extended mnemonics for bctar. Fix setting of 'at' branch hints. | Peter Bergner | 1 | -0/+36 |
| 2019-03-28 | PR24390, Don't decode mtfsb field as a cr field | Alan Modra | 1 | -0/+8 |
