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2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-0/+39
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang1-0/+7
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel1-0/+5
2017-07-20Update the German translation for the opcodes library.Nick Clifton1-0/+4
2017-07-19[ARC] Add SecureShield AUX registersclaziss1-0/+12
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu1-0/+7
2017-07-19[ARC] Add JLI support.John Eric Martin1-0/+8
2017-07-18Fix spelling typos.Yuri Chornovian1-0/+6
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria1-0/+5
2017-07-12Update PO filesAlan Modra1-0/+18
2017-07-11Mark generated cgen files read-onlyAlan Modra1-0/+99
2017-07-07Move print_insn_XXX to an opcodes internal header, againAlan Modra1-0/+6
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov1-0/+4
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+5
2017-07-04Regenerate configure.Tristan Gingold1-0/+4
2017-07-03Regenerate pot files.Tristan Gingold1-0/+4
2017-06-30MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki1-0/+5
2017-06-30MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)Maciej W. Rozycki1-1/+1
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki1-0/+7
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki1-0/+6
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-0/+12
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki1-0/+7
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov1-0/+5
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov1-0/+6
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+9
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-0/+4
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+21
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman1-0/+5
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-0/+15
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-0/+6
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-0/+7
2017-06-19Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton1-0/+5
2017-06-17Regen rx-decode.cAlan Modra1-0/+4
2017-06-15i386-dis: Check valid bnd registerH.J. Lu1-0/+6
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton1-0/+6
2017-06-15Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton1-0/+9
2017-06-15Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton1-0/+8
2017-06-14Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton1-0/+5
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-0/+13
2017-06-14Fix address violation problems when disassembling a corrupt RX binary.Nick Clifton1-0/+9
2017-06-14[opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira1-0/+4
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov1-0/+9
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-0/+28
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi1-0/+5
2017-05-24Refactor disassembler selectionYao Qi1-0/+5
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+16
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-0/+37
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-0/+7
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-0/+28
2017-05-15MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki1-0/+5
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