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For each command line option, parse_args() calls ldemul_parse_args()
to check if the command line option is an emulation option. But when
there is a conflict between the emulation option value and the default
option value, the default command line option will be processed as if
the emulation option is used. Remove PARSE_AND_LIST_PROLOGUE and move
all emulation options to ldlex.h to avoid conflicts.
PR ld/31247
* ldlex.h (option_values): Add all emulation options.
* emulparams/elf32mcore.sh (PARSE_AND_LIST_PROLOGUE): Removed.
* emulparams/plt_unwind.sh (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/aarch64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/alphaelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/armelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/avrelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/bfin.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/cskyelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/hppaelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/ia64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/m68hc1xelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/m68kelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/metagelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/mipself.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/nds32elf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/nto.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/ppc32elf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/ppc64elf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/riscvelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/rxelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/s390.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/scoreelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/spuelf.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/tic6xdsbt.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/vxworks.em (PARSE_AND_LIST_PROLOGUE): Likewise.
* emultempl/aix.em: Include "ldlex.h".
(OPTION_XXX): Removed.
(gld${EMULATION_NAME}_read_file): Replace lineno with linenumber.
* emultempl/beos.em (OPTION_XXX): Removed.
* emultempl/elf.em: Include "ldlex.h".
Don't check PARSE_AND_LIST_PROLOGUE.
(OPTION_XXX): Removed.
* emultempl/msp430.em: Include "ldlex.h".
(OPTION_XXX): Removed.
* emultempl/pe.em (OPTION_XXX): Removed.
* emultempl/pep.em (OPTION_XXX): Likewise.
* emultempl/ticoff.em: Include "ldlex.h".
(OPTION_XXX): Removed.
* emultempl/vms.em: Include "ldlex.h".
(OPTION_XXX): Removed.
* emultempl/xtensaelf.em (elf32xtensa_size_opt,
elf32xtensa_no_literal_movement, elf32xtensa_abi): Moved out of
PARSE_AND_LIST_PROLOGUE.
(PARSE_AND_LIST_PROLOGUE): Removed.
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Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
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* Problematic fix commit,
2029e13917d53d2289d3ebb390c4f40bd2112d21
RISC-V: Clarify the behaviors of SET/ADD/SUB relocations
* Bugzilla,
https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5
The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it
non-zero by accident in assembler before. This causes troubles by applying
the above commit, since the calculation is changed to support .reloc *SUB*
relocations with non-zero addend.
We encourage people to rebuild their stuff to get the non-zero addend of
SUB_ULEB128, but that might need some times, so report warnings to inform
people need to rebuild their stuff if --check-uleb128 is enabled.
Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use,
it may acceptable that stop supproting them until people rebuld their stuff,
maybe half-year or a year later. Or maybe we should teach people that don't
write the .reloc R_RISCV_SUB* with non-zero constant, and then report
warnings/errors in assembler.
bfd/
* elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of
R_RISCV_SUB_ULEB128.
(riscv_elf_relocate_section): Report warnings to inform people need
to rebuild their stuff if --check-uleb128 is enabled. So that can
get the right non-zero addend of R_RISCV_SUB_ULEB128.
* elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128.
ld/
* NEWS: Updated.
* emultempl/riscvelf.em: Added linker risc-v target options,
--[no-]check-uleb128, to enable/disable checking if the addend of
uleb128 is non-zero or not. So that people will know they need to
rebuild the objects with binutils 2.42 and up, to get the right zero
addend of SUB_ULEB128 relocation, or they may get troubles if using
.reloc.
* ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
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--relax enables all relaxations. --no-relax-gp disables GP relaxation to
allow measuring its effect.
The option can test effectiveness of GP relaxation and support some ABI
variants that use GP for other purposes.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/298
bfd/
* elfnn-riscv.c (struct riscv_elf_link_hash_table): Add params.
(riscv_elfNN_set_options): New.
(riscv_info_to_howto_rela): Check relax_gp.
(_bfd_riscv_relax_section): Likewise.
* elfxx-riscv.h (struct riscv_elf_params): New.
(riscv_elf32_set_options): New.
(riscv_elf64_set_options): New.
ld/
* emultempl/riscvelf.em: Add option parsing.
* testsuite/ld-riscv-elf/code-model-relax-medlow-01-norelaxgp.d: New.
* testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d: New.
* testsuite/ld-riscv-elf/pcgp-relax-02.d: Test --relax --relax-gp can be
used together.
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Commit 43025f01a0c9 ("RISC-V: Improve link time complexity.") reduced the
time complexity of the linker relaxation but some code portions did not
reflect this change.
This commit fixes a comment describing each relaxation pass and reduces
actual number of passes for the RISC-V linker relaxation from 3 to 2.
Though it does not change the functionality, it marginally improves the
performance while linking large programs (with many relocations).
bfd/ChangeLog:
* elfnn-riscv.c (_bfd_riscv_relax_section): Fix a comment to
reflect current roles of each relaxation pass.
ld/ChangeLog:
* emultempl/riscvelf.em: Reduce the number of linker relaxation
passes from 3 to 2.
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The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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Commit abd20cb637008da9d32018b4b03973e119388a0a and
ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional
complexity into the paths run by the RISC-V relaxation pass in order to
resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo
pairs. The first commit split up relaxation of these relocs into a pass
which occurred after other relaxations in order to prevent the situation
where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting
our ability to find the corresponding pcrel_hi relocation from the
address attached to the pcrel_lo.
Since the relaxation was split into two passes the 'again' parameter
could not be used to perform the entire relaxation process again and so
the second commit added a way to restart ldelf_map_segments, thus
starting the whole process again.
Unfortunately this process could not account for the fact that we were
not finished with the relaxation process so in some cases - such as the
case where code would not fit in a memory region before the
R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code
would fail.
This patch fixes all three of these concerns by reverting back to a
system of having only one target relax pass but updating entries in the
table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus
we can keep track of the pairs accurately, and we can use the 'again'
parameter to restart the entire target relax pass, behaving in the way
that generic code expects. Unfortunately we must still have an
additional pass to delay deleting AUIPC bytes to avoid ambiguity between
pcrel_hi relocs stored in the table after deletion. This pass can only
be run once so we may potentially miss out on relaxation opportunities
but this is likely to be rare.
https://sourceware.org/bugzilla/show_bug.cgi?id=28410
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax.
(riscv_elf_link_hash_table_create): Updated.
(riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs.
Update the pcgp_relocs table whenever bytes are deleted.
(riscv_update_pcgp_relocs): Add function to update the section
offset of pcrel_hi and pcrel_lo, and also update the symbol value
of pcrel_hi.
(_bfd_riscv_relax_call): Need to update the pcgp_relocs table
when deleting codes.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN,
we can't relax anything else, so set the sec->sec_flg0 to true.
Besides, we don't need to update the pcgp_relocs table at this
stage, so just pass NULL pointer as the pcgp_relocs table for
riscv_relax_delete_bytes.
(_bfd_riscv_relax_section): Use only one pass for all target
relaxations.
(_bfd_riscv_relax_delete): Likewise, we don't need to update
the pcgp_relocs table at this stage, and don't need to set
the `again' since restart_relax mechanism is abandoned.
(bfd_elfNN_riscv_restart_relax_sections): Removed.
(_bfd_riscv_relax_section): Updated.
* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed.
(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
* emultempl/riscvelf.em: Revert restart_relax changes and set
relax_pass to 3.
* testsuite/ld-riscv-elf/align-small-region.d: New testcase.
* testsuite/ld-riscv-elf/align-small-region.ld: Likewise.
* testsuite/ld-riscv-elf/align-small-region.s: Likewise.
* testsuite/ld-riscv-elf/restart-relax.d: Removed sine the
restart_relax mechanism is abandoned.
* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
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According to the commit abd20cb637008da9d32018b4b03973e119388a0a, an
intersting thing is that - the more relax passes, the more chances of
relaxations are reduced [1]. Originally, we set the boolean `again`
to TRUE once the code is actually deleted, and then we run the relaxations
repeatedly if `again` is still TRUE. But `again` only works for the
relax pass itself, and won't affect others. That is - we can not use
`again` to re-run the relax pass when we already enter into the following
passes (can not run the relax passes backwards). Besides, we must seperate
the PCREL relaxations into two relax passes for some reasons [2], it make
us lose some relax opportunities.
This patch try to fix the problem, and the basic idea was come from Jim
Wilson - we use a new boolean, restart_relax, to determine if we need to
run the whole relax passes again from 0 to 2. Once we have deleted the
code between relax pass 0 to 2, the restart_relax will be set to TRUE,
we should run the whole relaxations again to give them more chances to
shorten the code. We will only enter into the relax pass 3 when the
restart_relax is FALSE, since we can't relax anything else once we start
to handle the alignments.
I have passed the gcc/binutils regressions by riscv-gnu-toolchain, and
looks fine for now.
[1] https://sourceware.org/pipermail/binutils/2020-November/114223.html
[2] https://sourceware.org/pipermail/binutils/2020-November/114235.html
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): New boolean restart_relax,
used to check if we need to run the whole relaxations from relax pass 0
to 2 again.
(riscv_elf_link_hash_table_create): Init restart_relax to FALSE.
(_bfd_riscv_relax_align): Remove obsolete sec_flg0 set.
(_bfd_riscv_relax_delete): Set again to TRUE if we do delete the code.
(bfd_elfNN_riscv_restart_relax_sections): New function. Called by
after_allocation to check if we need to run the whole relaxations again.
(_bfd_riscv_relax_section): We will only enter into the relax pass 3 when
the restart_relax is FALSE; At last set restart_relax to TRUE if again is
TRUE, too.
* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Declaration.
(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
* emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments many
times if riscv_restart_relax_sections returns TRUE.
* testsuite/ld-riscv-elf/restart-relax.d: New testcase. Before applying
this patch, the call won't be relaxed to jal; But now we have more chances
to do relaxations.
* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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I get the feedback recently that enable linker relaxations may fail to
build some program. Consider the following case,
.text
foo:
addi a0, a0, %pcrel_lo(.L2)
call foo
.L1: auipc a1, %pcrel_hi(data_g)
addi a1, a1, %pcrel_lo(.L1)
lui a2, %hi(data_g)
addi a2, a2, %lo(data_g)
lui a3, %tprel_hi(data_t)
add a3, a3, tp, %tprel_add(data_t)
addi a3, a3, %tprel_lo(data_t)
.L2: auipc a0, %pcrel_hi(data_g)
.data
.word 0x0
.global data_g
data_g: .word 0x1
.section .tbss
data_t: .word 0x0
The current ld reports `dangerous relocation error` when doing the
pcgp relaxation,
test.o: in function `foo':
(.text+0x0): dangerous relocation: %pcrel_lo missing matching %pcrel_hi
The .L2 auipc should not be removed since it is behind the corresponding
addi, so we record the information in the pcgp_relocs table to avoid
removing the auipc later. But current ld still remove it since we do not
update the pcgp_relocs table while doing other relaxations. I have two
solutions to fix the problem,
1. Update the pcgp_relocs table once we actually delete the code.
2. Add new relax pass to do the pcgp relaxations
At first I tried to do the first solution, and we need to update at
least three information - hi_sec_off of riscv_pcgp_lo_reloc, hi_sec_off
and hi_addr (symbol value) of riscv_pcgp_hi_reloc. Update the hi_sec_off
is simple, but it is more complicate to update the symbol value, since we
almost have to do parts the same works of _bfd_riscv_relax_call again in
the riscv_relax_delete_bytes to get the correct symbol value.
Compared with the first solution, the second one is more intuitive and
simple. We add a new relax pass to do the pcgp relaxations later, so
we will get all the information correctly in the _bfd_riscv_relax_call,
including the symbol value, without changing so much code. I do not see
any penalty by adding a new relax pass for now, so it should be fine
to delay the pcgp relaxations.
Besides, I have pass all riscv-gnu-toolchain regressions for this patch.
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_section): Add a new relax pass
to do the pcgp relaxation later, after the lui and call relaxations,
but before the delete and alignment relaxations.
ld/
* emultempl/riscvelf.em (riscv_elf_before_allocation): Change
link_info.relax_pass from 3 to 4.
* testsuite/ld-riscv-elf/pcgp-relax.d: New testcase.
* testsuite/ld-riscv-elf/pcgp-relax.s: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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Many ELF linker targets support multiple "emulations" and thus have
multiple copies of elf32.em being compiled and linked into ld. This
patch moves much of elf32.em and elf-generic.em into files which will
be compiled just once, resulting in a 20% decrease in ld size for
--enable-targets=all.
* Makefile.am (ALL_EMUL_EXTRA_OFILES): Add ldelf and ldelfgen.
(CFILES, HFILES, EXTRA_ld_new_SOURCES): Likewise.
* configure.tgt: Formatting.
(targ_extra_ofiles): Init to ldelf.o ldelfgen.o, reset to just
ldelfgen.o for generic ELF targets, and empty for non-ELF.
* emultempl/aarch64elf.em (gldaarch64_layout_sections_again): Use
ldelf_map_segments.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, aarch64_for_each_input_file_wrapper),
(aarch64_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/alphaelf.em (alpha_after_parse): Use ldelf_map_segments.
* emultempl/armelf.em (gldarm_layout_sections_again): Likewise.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, arm_for_each_input_file_wrapper),
(arm_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/cr16elf.em (cr16elf_after_parse): Use ldelf_map_segments.
* emultempl/crxelf.em (crxelf_after_parse): Likewise. Delete
declaration.
* emultempl/cskyelf.em (gldcsky_layout_sections_again): Use
ldelf_map_segments.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, csky_for_each_input_file_wrapper),
(csky_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/genelf.em: Include ldelfgen.h.
(gld${EMULATION_NAME}_before_allocation): Use ldelf_map_segments.
* emultempl/hppaelf.em (hppaelf_after_parse): Likewise.
(hppaelf_layout_sections_again): Likewise.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, hppa_for_each_input_file_wrapper),
(hppa_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/ia64elf.em (ia64elf_after_parse): Use ldelf_map_segments.
* emultempl/m68hc1xelf.em (real_func),
(m68hc11_for_each_input_file_wrapper),
(m68hc11_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/metagelf.em (metagelf_layout_sections_again): Use
ldelf_map_segments.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, metag_for_each_input_file_wrapper),
(metag_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/mipself.em (real_func),
(mips_for_each_input_file_wrapper),
(mips_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/mmo.em: Don't include elf-bfd.h, do include ldelfgen.h.
(gld${EMULATION_NAME}_after_allocation): Use ldelf_map_segments.
* emultempl/nds32elf.em (nds32_elf_after_parse): Use ldelf_after_parse.
(nds32_elf_after_allocation): Comment fix.
* emultempl/nios2elf.em (nios2elf_layout_sections_again): Use
ldelf_map_segments.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, nios2_for_each_input_file_wrapper),
(nios2_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
* emultempl/ppc32elf.em (gld${EMULATION_NAME}_load_symbols): Delete
declaration.
(ppc_recognized_file): Call ldelf_load_symbols.
* emultempl/ppc64elf.em (ppc_layout_sections_again): Likewise.
(gld${EMULATION_NAME}_after_allocation): Likewise.
(real_func, ppc_for_each_input_file_wrapper),
(ppc_lang_for_each_input_file): Delete.
(lang_for_each_input_file): Don't define.
(gld${EMULATION_NAME}_load_symbols): Don't declare.
(ppc64_recognized_file): Call ldelf_load_symbols.
* emultempl/riscvelf.em (gld${EMULATION_NAME}_after_allocation):
Use ldelf_map_segments.
* emultempl/spuelf.em (spu_place_special_section): Use
ldelf_place_orphan.
* emultempl/tic6xdsbt.em (gld${EMULATION_NAME}_after_allocation):
Use ldelf_map_segments.
* emultempl/vms.em: Include ldelfgen.h.
(gld${EMULATION_NAME}_after_allocation): Use ldelf_map_segments.
* emultempl/elf32.em: Remove unnecessary headers, include ldelf.h
and ldelfgen.h. Move much of file content to..
* ldelf.c: ..here. New file.
* ldelf.h: New file.
* emultempl/elf-generic.em: Move gld${EMULATION_NAME}_map_segments..
* ldelfgen.c: ..to here.
* ldelfgen.h: New file.
* ldlang.c (lang_for_each_input_file): Adjust to only call func
on real files.
(lang_for_each_file): Likewise.
* po/SRC-POTFILES.in: Regenerate.
* Makefile.in: Regenerate.
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PR ld/22949
* emultempl/riscvelf.em (riscv_elf_before_allocation): Don't
enable relaxation in relocatable link.
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PR 22920
* emultempl/riscvelf.em (riscv_create_output_section_statements): New.
(LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): New.
* testsuite/ld-elf/pr21884.d (#notarget): Add riscv*-*-*.
* testsuite/ld-unique/pr21529.d (#notarget): Likewise.
* testsuite/ld-srec/srec.exp (run_srec_test): For riscv*-*-* target,
call setup_xfail.
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We currently delete bytes by shifting an entire BFD backwards to
overwrite the bytes we no longer need. The result is that relaxing a
BFD is quadratic time.
This patch adds an additional relocation that specifies a byte range
that will be deleted from the final object file, and adds a relaxation
pass (between the existing passes that delete bytes and the alignment
pass) that actually deletes the bytes. Note that deletion is still
quadratic time, and nothing uses R_RISCV_DELETE yet.
I've been meaning to go convert all the other relaxations to use
R_RISCV_DELETE and then make it faster, but this patch has been sitting
around for months so it looks like that won't happen for a bit. The
PCREL->GPREL relaxation that comes next uses this, and since we've been
using these two patches out of tree since I wrote them months ago I
figure it's better to just get them in now. I (or someone else :)) can
convert all the relocations later...
R_RISCV_DELETE will never be emitted into ELF objects, so therefor isn't
exposed to the rest of binutils. As such, we're not considering this as
part of the ABI.
bfd/ChangeLog
2017-10-19 Palmer Dabbelt <palmer@dabbelt.com>
* elfnn-riscv (R_RISCV_DELETE): New define.
(_bfd_riscv_relax_delete): New function.
(perform_relocation): Handle R_RISCV_DELETE.
(_bfd_riscv_relax_section): Likewise.
ld/ChangeLog
2017-10-19 Palmer Dabbelt <palmer@dabbelt.com>
* emultempl/riscvelf.em (riscv_elf_before_allocation): Add a
third relaxation pass.
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* emultempl/aarch64elf.em: Wrap einfo strings in _(). Formatting.
* emultempl/aix.em: Likewise.
* emultempl/armcoff.em: Likewise.
* emultempl/armelf.em: Likewise.
* emultempl/avrelf.em: Likewise.
* emultempl/beos.em: Likewise.
* emultempl/cr16elf.em: Likewise.
* emultempl/elf-generic.em: Likewise.
* emultempl/elf32.em: Likewise.
* emultempl/genelf.em: Likewise.
* emultempl/hppaelf.em: Likewise.
* emultempl/linux.em: Likewise.
* emultempl/lnk960.em: Likewise.
* emultempl/m68hc1xelf.em: Likewise.
* emultempl/m68kcoff.em: Likewise.
* emultempl/m68kelf.em: Likewise.
* emultempl/metagelf.em: Likewise.
* emultempl/mipself.em: Likewise.
* emultempl/mmix-elfnmmo.em: Likewise.
* emultempl/mmo.em: Likewise.
* emultempl/msp430.em: Likewise.
* emultempl/nds32elf.em: Likewise.
* emultempl/nios2elf.em: Likewise.
* emultempl/pe.em: Likewise.
* emultempl/pep.em: Likewise.
* emultempl/ppc32elf.em: Likewise.
* emultempl/ppc64elf.em: Likewise.
* emultempl/riscvelf.em: Likewise.
* emultempl/s390.em: Likewise.
* emultempl/scoreelf.em: Likewise.
* emultempl/spuelf.em: Likewise.
* emultempl/sunos.em: Likewise.
* emultempl/tic6xdsbt.em: Likewise.
* emultempl/v850elf.em: Likewise.
* emultempl/vms.em: Likewise.
* emultempl/vxworks.em: Likewise.
* ldcref.c: Likewise.
* ldlang.c: Likewise.
* ldlex.l: Likewise.
* ldmain.c: Likewise.
* pe-dll.c: Likewise.
* plugin.c: Likewise.
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bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.
binutils* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.
gas * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.
ld * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this target.
* configure.tgt: Add riscv entries.
* emulparams/elf32lriscv-defs.sh: New file.
* emulparams/elf32lriscv.sh: New file.
* emulparams/elf64lriscv-defs.sh: New file.
* emulparams/elf64lriscv.sh: New file.
* emultempl/riscvelf.em: New file.
opcodes * configure.ac: Add entry for bfd_riscv_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add support for riscv.
(disassembler_usage): Likewise.
* riscv-dis.c: New file.
* riscv-opc.c: New file.
include * dis-asm.h: Add prototypes for print_insn_riscv and
print_riscv_disassembler_options.
* elf/riscv.h: New file.
* opcode/riscv-opc.h: New file.
* opcode/riscv.h: New file.
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