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2021-10-24LoongArch opcodes supportliuzhensong2-0/+240
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-10-24LoongArch bfd supportliuzhensong2-1/+130
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> bfd/ * Makefile.am: Add LoongArch. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-loongarch.c: New. * elf-bfd.h: Add LoongArch. * elf.c: Add LoongArch elfcore_grok_xxx. * elfnn-loongarch.c: New. * elfxx-loongarch.c: New. * elfxx-loongarch.h: New. * reloc.c: Add LoongArch BFD RELOC ENUM. * targets.c: Add LoongArch target. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. include/ * elf/common.h: Add NT_LARCH_{CPUCFG,CSR,LSX,LASX}. * elf/loongarch.h: New.
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich2-0/+25
This change adds the Zbs instructions from the Zbs 1.0.0 specification. See https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0 for the frozen specification. 2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu> bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS. * testsuite/gas/riscv/b-ext.d: Test Zbs instructions. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS. opcodes/ * riscv-opc.c (riscv_supported_std_z_ext): Add zbs. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+5
Patch is adding new 'armv9-a` command line flag to -march for AArch64. gas/ * config/tc-aarch64.c: Add 'armv9-a' command line flag. * docs/c-aarch64.text: Update docs. * NEWS: Update docs. include/ * opcode/aarch64.h (AARCH64_FEATURE_V9): New define. (AARCH64_ARCH_V9): New define.
2021-09-30Add Solaris specific ELF note processingLibor Bukata1-0/+23
Add elfcore_grok_solaris_note function that enables to obtain process status, register values, and program info from Solaris's core files. bfd/ * elf.c (elfcore_grok_solaris_note): Solaris specific ELF note parser. Better GDB's coredump analysis on Solaris... (elfcore_grok_solaris_note_impl): New function. (elfcore_grok_solaris_prstatus): New function. (elfcore_grok_solaris_info): New function. (elfcore_grok_solaris_lwpstatus): New function. (elf_parse_notes): Added "CORE" groker element. include/ * elf/common.h: Add note segment constants for core files on Solaris systems.
2021-09-07Revert: [AArch64] MTE corefile supportLuis Machado2-6/+9
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-09-02obstack.h __PTR_ALIGN vs. ubsanAlan Modra1-3/+3
Current ubsan complains on every use of __PTR_ALIGN (when ptrdiff_t is as large as a pointer), due to making calculations relative to a NULL pointer. This patch avoids the problem by extracting out and simplifying __BPTR_ALIGN for the usual case. I've continued to use ptrdiff_t here, where it might be better to throw away __BPTR_ALIGN entirely and just assume uintptr_t exists. * obstack.h (__PTR_ALIGN): Expand and simplify __BPTR_ALIGN rather than calculating relative to a NULL pointer.
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-0/+7
Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree.
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PACRET_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PACRET_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PACRET_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PAC_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PAC_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PAC_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PAC_extension'.
2021-08-11Add 3 new PAC-related ARM note typesLuis Machado1-0/+9
The following patch synchronizes includes/objdump/readelf with the Linux Kernel in terms of ARM regset notes. We're currently missing 3 of them: NT_ARM_PACA_KEYS NT_ARM_PACG_KEYS NT_ARM_PAC_ENABLED_KEYS We don't need GDB to bother with this at the moment, so this doesn't update bfd/elf.c. If needed, we can do it in the future. binutils/ * readelf.c (get_note_type): Handle new ARM PAC notes. include/elf/ * common.h (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) (NT_ARM_PAC_ENABLED_KEYS): New constants.
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+7
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (pacbti_ext): Define. (BAD_PACBTI): New macro. (armv8_1m_main_ext_table): Add 'pacbti' extension. include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New macro.
2021-07-26PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bitsAndrea Corallo1-4/+16
include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (arm_feature_set): Extend 'core' field. (ARM_CPU_HAS_FEATURE, ARM_FSET_CPU_SUBSET, ARM_CPU_IS_ANY) (ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, ARM_FEATURE_EQUAL) (ARM_FEATURE_ZERO, ARM_FEATURE_CORE_EQUAL): Account for 'core[2]'. (ARM_FEATURE_CORE_HIGH_HIGH): New macro.
2021-07-08elf: Add GNU_PROPERTY_1_NEEDED checkH.J. Lu1-4/+19
If GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS is set on any input relocatable files: 1. Don't generate copy relocations. 2. Turn off extern_protected_data since it implies GNU_PROPERTY_NO_COPY_ON_PROTECTED. 3. Treate reference to protected symbols with indirect external access as local. 4. Set GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS on output. 5. When generating executable, clear this bit when there are non-GOT or non-PLT relocations in input relocatable files without the bit set. 6. Add -z [no]indirect-extern-access to control indirect external access. bfd/ * elf-bfd (elf_obj_tdata): Add has_indirect_extern_access. (elf_has_indirect_extern_access): New. * elf-properties.c (_bfd_elf_parse_gnu_properties): Set elf_has_indirect_extern_access and elf_has_no_copy_on_protected when seeing GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. (elf_write_gnu_propertie): Add an argument to pass link_info. Set needed_1_p for GNU_PROPERTY_1_NEEDED in memory. (_bfd_elf_link_setup_gnu_properties): Handle GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS for -z indirect-extern-access. Set nocopyreloc to true and extern_protected_data to false for indirect external access. (_bfd_elf_convert_gnu_properties): Updated. * elf32-i386.c (elf_i386_check_relocs): Set non_got_ref_without_indirect_extern_access on legacy non-GOT or non-PLT references. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. * elflink.c (_bfd_elf_symbol_refs_local_p): Return true for STV_PROTECTED symbols with indirect external access. * elfxx-x86.c (_bfd_x86_elf_adjust_dynamic_symbol): Clear indirect_extern_access for legacy non-GOT/non-PLT references. * elfxx-x86.h (elf_x86_link_hash_entry): Add non_got_ref_without_indirect_extern_access. include/ * bfdlink.h (bfd_link_info): Add indirect_extern_access and needed_1_p. Change nocopyreloc to int. ld/ * NEWS: Mention -z [no]indirect-extern-access * ld.texi: Document -z [no]indirect-extern-access * ldmain.c (main): Initialize link_info.indirect_extern_access to -1. * emulparams/extern_protected_data.sh: Support -z [no]indirect-extern-access. * testsuite/ld-elf/indirect-extern-access-1.rd: New file * testsuite/ld-elf/indirect-extern-access-1a.c: Likewise. * testsuite/ld-elf/indirect-extern-access-1b.c: Likewise. * testsuite/ld-elf/indirect-extern-access-2.rd: Likewise. * testsuite/ld-elf/indirect-extern-access-2a.c: Likewise. * testsuite/ld-elf/indirect-extern-access-2b.c: Likewise. * testsuite/ld-elf/indirect-extern-access-3.rd: Likewise. * testsuite/ld-elf/indirect-extern-access.S: Likewise. * testsuite/ld-elf/property-1_needed-1b.d: Likewise. * testsuite/ld-elf/property-1_needed-1c.d: Likewise. * testsuite/ld-x86-64/indirect-extern-access.rd: Likewise. * testsuite/ld-x86-64/protected-data-1.h: Likewise. * testsuite/ld-x86-64/protected-data-1a.c: Likewise. * testsuite/ld-x86-64/protected-data-1b.c: Likewise. * testsuite/ld-x86-64/protected-data-2a.S: Likewise. * testsuite/ld-x86-64/protected-data-2b.S: Likewise. * testsuite/ld-x86-64/protected-func-2a.S: Likewise. * testsuite/ld-x86-64/protected-func-2b.S: Likewise. * testsuite/ld-x86-64/protected-func-2c.c: Likewise. * testsuite/ld-elf/linux-x86.exp: Run test with GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. * testsuite/ld-x86-64/x86-64.exp: Run tests for protected function and data with indirect external access.
2021-07-08elf: Add GNU_PROPERTY_1_NEEDEDH.J. Lu1-0/+7
Add GNU_PROPERTY_1_NEEDED: #define GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO to indicate the needed properties by the object file. Add GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS: #define GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0) to indicate that the object file requires canonical function pointers and cannot be used with copy relocation. binutils/ * readelf.c (decode_1_needed): New. (print_gnu_property_note): Handle GNU_PROPERTY_1_NEEDED. include/ * elf/common.h (GNU_PROPERTY_1_NEEDED): New. (GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS): Likewise. ld/ * testsuite/ld-elf/property-1_needed-1a.d: New file. * testsuite/ld-elf/property-1_needed-1.s: Likewise.
2021-07-08ld: Limit cache size and add --max-cache-size=SIZEH.J. Lu1-0/+7
When link_info.keep_memory is true, linker caches the relocation information and symbol tables of input files in memory. When there are many input files with many relocations, we may run out of memory. Add --max-cache-size=SIZE to set the maximum cache size. bfd/ PR ld/18028 * bfd.c (bfd): Add alloc_size. * elf-bfd.h (_bfd_elf_link_info_read_relocs): New. * elf32-i386.c (elf_i386_check_relocs): Use _bfd_link_keep_memory. Update cache_size. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. * elflink.c (_bfd_elf_link_read_relocs): Renamed to ... (_bfd_elf_link_info_read_relocs): This. Update cache_size. (_bfd_elf_link_read_relocs): New. (_bfd_elf_link_check_relocs): Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (elf_link_add_object_symbols): Likewise. (elf_link_input_bfd): Likewise. (init_reloc_cookie_rels): Likewise. (init_reloc_cookie): Update cache_size. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (link_info_ok): New. (elf_gc_smash_unused_vtentry_relocs): Updated. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (bfd_elf_gc_sections): Use link_info_ok. Pass &link_info_ok to elf_gc_smash_unused_vtentry_relocs. * libbfd-in.h (_bfd_link_keep_memory): New. * linker.c (_bfd_link_keep_memory): New. * opncls.c (bfd_alloc): Update alloc_size. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. include/ PR ld/18028 * bfdlink.h (bfd_link_info): Add cache_size and max_cache_size. ld/ PR ld/18028 * NEWS: Mention --max-cache-size=SIZE. * ld.texi: Document --max-cache-size=SIZE. * ldlex.h (option_values): Add OPTION_MAX_CACHE_SIZE. * ldmain.c: (main): Set link_info.max_cache_size to -1. * lexsup.c (ld_options): Add --max-cache-size=SIZE. (parse_args): Support OPTION_MAX_CACHE_SIZE. * testsuite/ld-bootstrap/bootstrap.exp: Add test for --max-cache-size=-1.
2021-07-06RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR.Kito Cheng1-0/+5
We added PT_RISCV_ATTRIBUTES to program header to make .riscv.attribute easier to find in dynamic loader or kernel. Ref: https://github.com/riscv/riscv-elf-psabi-doc/pull/71 ChangeLog: bfd/ * elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New. (riscv_elf_additional_program_headers): Ditto. (riscv_elf_modify_segment_map): Ditto. (elf_backend_additional_program_headers): Ditto. (elf_backend_modify_segment_map): Ditto. (elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME rather than string literal. binutils/ * readelf.c(get_riscv_segment_type): New. (get_segment_type): Handle EM_RISCV. include/ * elf/riscv.h (PT_RISCV_ATTRIBUTES): New. * testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes section for simplify testcase. * testsuite/ld-riscv-elf/attr-phdr.d: New. * testsuite/ld-riscv-elf/attr-phdr.s: Ditto. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to testcase.
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-03Synchronize libiberty sources (and include/demangle.h) with GCC master versionNick Clifton2-0/+12
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger2-1/+5
This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-07-01arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw2-1/+6
Although the XScale and its iwMMX extensions are implemented in the Arm co-processor space, they are not considered to be part of the FPU specification. In particular, they cannot be enabled or disabled via a .fpu directive. It's therefore incorrect to strip these properties when a new .fpu directive is encountered. Note that the legacy Maverick co-processor is considered to be a FPU and it is possible to control this via the .fpu directive. include: PR gas/28031 * opcode/arm.h (FPU_ANY): Exclude XScale-related features.
2021-06-29sim: callback: add printf attributesMike Frysinger2-4/+13
This helps these funcs get printf format checking coverage. The sim-io.c hack as a result is a bit unfortunate, but the compiler throws warnings when printing with empty strings. In this one case, we actually want that due to the side-effect of the callback halting execution for us.
2021-06-24sim: callback: extend syscall interface to handle 7 argsMike Frysinger2-1/+6
The Linux syscall interface, depending on architecture, handles up to 7 arguments. Extend the callback API to handle those.
2021-06-23sim: callback: add a kill interfaceMike Frysinger2-0/+5
This will make it easier to emulate the syscall. If the kill target is the sim itself, don't do anything. This forces the higher layers to make a decision as to how to handle this event: like halting the overall engine process.
2021-06-22sim: callback: add a getpid interfaceMike Frysinger2-0/+5
Rather than hit the OS interface directly, use the existing callback layer so the instantiator can decide behavior.
2021-06-18elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXXH.J. Lu2-0/+17
Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX: https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html 1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI #define GNU_PROPERTY_UINT32_AND_LO 0xb0000000 #define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff A bit in the output pr_data field is set only if it is set in all relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, all input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. 2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI #define GNU_PROPERTY_UINT32_OR_LO 0xb0008000 #define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff A bit in the output pr_data field is set if it is set in any relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, some input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. bfd/ * elf-properties.c (_bfd_elf_parse_gnu_properties): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. (elf_merge_gnu_properties): Likewise. binutils/ * readelf.c (print_gnu_property_note): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. include/ * elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New. (GNU_PROPERTY_UINT32_AND_HI): Likewise. (GNU_PROPERTY_UINT32_OR_LO): Likewise. (GNU_PROPERTY_UINT32_OR_HI): Likewise. ld/ * testsuite/ld-elf/property-and-1.d: New file. * testsuite/ld-elf/property-and-1.s: Likewise. * testsuite/ld-elf/property-and-2.d: Likewise. * testsuite/ld-elf/property-and-2.s: Likewise. * testsuite/ld-elf/property-and-3.d: Likewise. * testsuite/ld-elf/property-and-3.s: Likewise. * testsuite/ld-elf/property-and-4.d: Likewise. * testsuite/ld-elf/property-and-empty.s: Likewise. * testsuite/ld-elf/property-or-1.d: Likewise. * testsuite/ld-elf/property-or-1.s: Likewise. * testsuite/ld-elf/property-or-2.d: Likewise. * testsuite/ld-elf/property-or-2.s: Likewise. * testsuite/ld-elf/property-or-3.d: Likewise. * testsuite/ld-elf/property-or-3.s: Likewise. * testsuite/ld-elf/property-or-4.d: Likewise. * testsuite/ld-elf/property-or-empty.s: Likewise.
2021-06-15Allow readelf to recognise GO buildid notes.Nick Clifton2-0/+5
binutils * readelf.c (get_note_type): Add support for NT_GO_BUILDID. include * elf/common.h (NT_GO_BUILDID): Define.
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-0/+5
The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2-19/+24
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and handle the exclusion for any ISA levels properly in `opcode_is_member'. Flatten the structure of the `if' statements there. No functional change for the existing opcode tables. include/ * opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA exclusion. (opcode_is_member): Handle ISA level exclusion.
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2-4/+27
In preparation for the next change factor out code for ISA matching against instruction flags used in MIPS opcode tables, similarly to how CPU matching is already done. No functional change, though for clarity split the single `if' statement into multiple ones and use temporaries rather than repeated expressions. include/ * opcode/mips.h (isa_is_member): New inline function, factored out from... (opcode_is_member): ... here.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-2/+15
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-2/+6
In the operand handling rewrite made for the MIPS disassembler with commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu2-1/+5
The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu2-0/+6
commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs caused linker failure when building 16-bit program in a 32-bit ELF container. Update GNU_PROPERTY_X86_FEATURE_2_USED with #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12) to indicate that 16-bit mode instructions are used in the input object: https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA to indicate that 16-bit mode instructions are used in the object to allow linker to properly perform relocation overflow check for 16-bit PC-relative relocations in 16-bit mode instructions. 1. Update x86 assembler to always generate the GNU property note with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. 2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. bfd/ PR ld/27905 * elf32-i386.c: Include "libiberty.h". (elf_howto_table): Add 16-bit R_386_PC16 entry. (elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit R_386_PC16 if input has 16-bit mode instructions. (elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto call. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit R_X86_64_PC16 entry. (elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input has 16-bit mode instructions. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set elf_x86_has_code16 if relocatable input is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. * elfxx-x86.h (elf_x86_obj_tdata): Add has_code16. (elf_x86_has_code16): New. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Support GNU_PROPERTY_X86_FEATURE_2_CODE16. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Update x86_feature_2_used with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Always generate the GNU property note if x86_feature_2_used isn't 0. * testsuite/gas/i386/code16-2.d: New file. * testsuite/gas/i386/code16-2.s: Likewise. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. * testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New. ld/ PR ld/27905 * testsuite/ld-i386/code16.d: New file. * testsuite/ld-i386/code16.t: Likewise. * testsuite/ld-x86-64/code16.d: Likewise. * testsuite/ld-x86-64/code16.t: Likewise. * testsuite/ld-i386/i386.exp: Run code16. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-23elf: Use official name LoongArch for EM_LOONGARCH.Chenghua Xu2-1/+6
The official name for Loongson Architecture is LoongArch, it is better to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid confusion and keep consistent with the various of software in the future. The official documentation in Chinese: http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf The translated version in English: https://loongson.github.io/LoongArch-Documentation/ binutils/ * readelf.c (get_machine_name): Change Loongson Loongarch to LoongArch. include/ * elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to LoongArch.
2021-05-21[AArch64] MTE corefile supportLuis Machado2-0/+11
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-05-14sim: callback: convert FS interfaces to 64-bitMike Frysinger2-3/+8
Rather than rely on off_t being the right size between the host & target, have the interface always be 64-bit. We can figure out if we need to truncate when actually outputting it to the right target.
2021-05-14sim: callback: convert time interface to 64-bitMike Frysinger2-1/+8
PR sim/27705 Rather than rely on time_t being the right size between the host & target, have the interface always be 64-bit. We can figure out if we need to truncate when actually outputting it to the right target.
2021-05-14sim: callback: inline PTR defineMike Frysinger2-3/+8
We require C11 now, so no need for these pre-ANSI C hacks. PTR is simply void*, so use that directly.
2021-05-14sim: callback: use ATTRIBUTE_NORETURNMike Frysinger2-5/+5
This define is handled by ansidecl.h, so no need to duplicate effort.
2021-05-14sim: callback: always include necessary headersMike Frysinger2-4/+4
We use types from these headers, so always include them.
2021-05-14sim: create header namespaceMike Frysinger4-5/+14
The gdb/callback.h & gdb/remote-sim.h headers have nothing to do with gdb and are really definitions for the libsim API under the sim/ tree. While gdb uses those headers as a client, it's not specific to it. So create a new sim/ namespace and move the headers there.
2021-05-07Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on ↵Cl?ment Chigot3-0/+10
XCOFF. gas * config/tc-ppc.c (ppc_function): Update comment for fifth argument. (ppc_frob_symbol): Remove ppc_last_function check. Make sure coff_last_function is reset. Correctly set fsize when not provided in .function. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-function-1-32.d: New test. * testsuite/gas/ppc/xcoff-function-1-64.d: New test. * testsuite/gas/ppc/xcoff-function-1.s: New test. bfd * coff-rs6000.c (xcoff_dwsect_names): Add new DWARF sections. * coffgen.c (coff_pointerize_aux): Handle C_DWARF. (coff_print_symbol): Likewise. * libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update. gas * config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF. (coff_adjust_section_syms): Use corrext auxent for C_DWARF. (coff_frob_section): Likewise. * config/obj-coff.h (SA_GET_SECT_SCNLEN, SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN, SA_SET_SECT_NRELOC) New defines. (SET_SECTION_RELOCS): Adjust for C_DWARF. * config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF. (ppc_adjust_symtab): Reorder C_DWARF symbols. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2.s: New test. include * coff/internal.h (C_DWARF): New define. * coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME, SSUBTYP_DWMAC): New defines.
2021-05-07libiberty: add htab_eq_stringTom Tromey1-0/+3
The libiberty hash table includes a helper function for strings, but no equality function. Consequently, this equality function has been reimplemented a number of times in both the gcc and binutils-gdb source trees. This patch adds the function to the libiberty hash table, as a step toward the goal of removing all the copies. One change to gcc is included here. Normally I would have put this in the next patch, but gensupport.c used the most natural name for its reimplementation of this function, and this can't coexist with the extern function in libiberty. include * hashtab.h (htab_eq_string): Declare. libiberty * hashtab.c (htab_eq_string): New function.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2-0/+6
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-06libctf, include: support an alternative encoding for nonrepresentable typesNick Alcock3-1/+9
Before now, types that could not be encoded in CTF were represented as references to type ID 0, which does not itself appear in the dictionary. This choice is annoying in several ways, principally that it forces generators and consumers of CTF to grow special cases for types that are referenced in valid dicts but don't appear. Allow an alternative representation (which will become the only representation in format v4) whereby nonrepresentable types are encoded as actual types with kind CTF_K_UNKNOWN (an already-existing kind theoretically but not in practice used for padding, with value 0). This is backward-compatible, because CTF_K_UNKNOWN was not used anywhere before now: it was used in old-format function symtypetabs, but these were never emitted by any compiler and the code to handle them in libctf likely never worked and was removed last year, in favour of new-format symtypetabs that contain only type IDs, not type kinds. In order to link this type, we need an API addition to let us add types of unknown kind to the dict: we let them optionally have names so that GCC can emit many different unknown types and those types with identical names will be deduplicated together. There are also small tweaks to the deduplicator to actually dedup such types, to let opening of dicts with unknown types with names work, to return the ECTF_NONREPRESENTABLE error on resolution of such types (like ID 0), and to print their names as something useful but not a valid C identifier, mostly for the sake of the dumper. Tests added in the next commit. include/ChangeLog 2021-05-06 Nick Alcock <nick.alcock@oracle.com> * ctf.h (CTF_K_UNKNOWN): Document that it can be used for nonrepresentable types, not just padding. * ctf-api.h (ctf_add_unknown): New. libctf/ChangeLog 2021-05-06 Nick Alcock <nick.alcock@oracle.com> * ctf-open.c (init_types): Unknown types may have names. * ctf-types.c (ctf_type_resolve): CTF_K_UNKNOWN is as non-representable as type ID 0. (ctf_type_aname): Print unknown types. * ctf-dedup.c (ctf_dedup_hash_type): Do not early-exit for CTF_K_UNKNOWN types: they have real hash values now. (ctf_dedup_rwalk_one_output_mapping): Treat CTF_K_UNKNOWN types like other types with no referents: call the callback and do not skip them. (ctf_dedup_emit_type): Emit via... * ctf-create.c (ctf_add_unknown): ... this new function. * libctf.ver (LIBCTF_1.2): Add it.
2021-04-22Harmonize and improve auxiliary entries support for XCOFFCl?ment Chigot4-101/+117
bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_swap_aux_in): Add errors for unsupported storage class or auxialiry entries. Improve and adapt to new aux structures. Add C_DWARF support. (_bfd_xcoff_swap_aux_out): Likewise. * coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise. (_bfd_xcoff64_swap_aux_out): Likewise. binutils/ChangeLog: * od-xcoff.c (dump_xcoff32_symbols): Adapt to new aux structures. include/ChangeLog: * coff/internal.h (union internal_auxent): Add x_sect structure. * coff/rs6000.h (union external_auxent): Rework to match official documentation. * coff/rs6k64.h (union external_auxent): Likewise. (_AUX_SECT): New define.
generated by cgit v1.1 at 2024-10-20 02:38:07 +0000