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2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-1/+8
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16.
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a ↵Tamar Christina2-1/+7
into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
2017-11-13PE: don't corrupt section flags when linking from ELF objectsJan Beulich2-1/+10
Linking EFI executables from ELF object files can result in corrupted COFF section flags if the section's alignment is too high. Issue a diagnostic in that case, erroring out if this is not a final link, and make sure only in-range values get written to the output image. While doing this also make tic80 use the generic alignment macros instead of custom #ifdef-ary. No testsuite regressions for the range of COFF/PE targets that actually cross-build in the first place on x86-64-linux.
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina2-1/+6
include/ * opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD. gas/testsuite * gas/aarch64/dotproduct_armv8_4.s: New. * gas/aarch64/dotproduct_armv8_4.d: New.
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2-0/+16
gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own ↵Tamar Christina2-0/+11
options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
2017-11-09Change the type of the aarch64_feature_set typedef to unsigned long long so ↵Nick Clifton2-1/+6
that it will work on 32-bit hosts. * opcode/aarch64.h (aarch64_feature_set): Change type to unsigned long long.
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own ↵Nick Clifton2-0/+7
options (+aes and +sha2). The new options are: +aes: Enables the AES instructions of Armv8-a, enabled by default with +crypto. +sha2: Enables the SHA1 and SHA2 instructions of Armv8-a, enabled by default with +crypto. These options have been turned on by default when +crypto is used, as such no breakage is expected. The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. Backporting the split does not break any of the previous requirements and so is safe to do. gas * config/tc-aarch64.c (aarch64_features): Include AES and SHA2 in CRYPTO. Add SHA2 and AES. include * opcode/aarch64.h: (AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New. opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. (aarch64_feature_sha2, aarch64_feature_aes): New. (SHA2, AES): New. (AES_INSN, SHA2_INSN): New. (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. (sha1h, sha1su1, sha256su0, sha1c, sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1): Change to SHA2_INS.
2017-11-08Adds command line support for Armv8.4-A, via the new command line option ↵Jiong Wang2-2/+14
-march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt2-2/+11
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page Table Base Register) to satp (Supervisor Address Translation and Protection) to reflect the fact it could be used for more than just paging. This patch adds an alias, as they're the same register. include/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * opcode/riscv-opc.h (sptbr): Rename to satp. (CSR_SPTBR): Rename to CSR_SATP. (sptbr): Alias to CSR_SATP. gas/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * testsuite/gas/riscv/satp.d: New test. testsuite/gas/riscv/satp.s: Likewise. testsuite/gas/riscv/riscv.exp: Likewise. config/tc-riscv.c (md_begin): Handle CSR aliases.
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by ↵Tamar Christina2-19/+33
default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions. gas * config/tc-arm.c (arm_cpus): Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD. include * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): New macro.
2017-11-02aarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2Siddhesh Poyarekar2-1/+5
The FP16 feature is optional in ARMv8.2, so it is wrong to add it to the default AARCH64_ARCH_V8_2 feature flags. This patch makes the behaviour consistent with that of gcc, which also does not assume FP16 for ARMv8.2. include/ * opcode/aarch64.h (AARCH64_ARCH_V8_2): Drop AARCH64_FEATURE_F16.
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which ↵James Bowman2-0/+8
requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 2 adds a relaxation pass, which actually implements the code compression scheme. bfd * archures.c: Add bfd_mach_ft32b. * cpu-ft32.c: Add arch_info_struct. * elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1, DIFF32. (ft32_elf_relocate_section): Add clauses for R_FT32_SC0, SC1, DIFF32. (ft32_reloc_shortable, elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value, elf32_ft32_adjust_reloc_if_spans_insn, elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target, ft32_elf_relax_section): New function. * reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-ft32.c (md_assemble): add relaxation reloc BFD_RELOC_FT32_RELAX. (md_longopts): Add "norelax" and "no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32. (relaxable_section, ft32_validate_fix_sub, ft32_force_relocation, ft32_allow_local_subtract): New function. * config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION. * testsuite/gas/ft32/insnsc.s: New test exercising all FT32B shortcodes. include * elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra3-14/+13
include/ PR 22348 * opcode/cr16.h (instruction): Delete. (cr16_words, cr16_allWords, cr16_currInsn): Delete. * opcode/crx.h (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. (instruction): Delete. opcodes/ PR 22348 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. (cr16_words, cr16_allWords, processing_argument_number): Likewise. (imm4flag, size_changed): Likewise. * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. (words, allWords, processing_argument_number): Likewise. (cst4flag, size_changed): Likewise. * crx-opc.c (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. gas/ PR 22348 * config/tc-crx.c (instruction, output_opcode): Make static. (relocatable, ins_parse, cur_arg_num): Likewise. (parse_insn): Adjust for renamed opcodes globals. (check_range): Likewise
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman2-1/+6
This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-12FT32: support for FT32B processor - part 1James Bowman3-3/+394
FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
2017-10-05Handle FreeBSD-specific AT_EHDRFLAGS and AT_HWCAP auxiliary vector types.John Baldwin2-0/+6
FreeBSD recently added two additional ELF auxiliary vectors. FreeBSD's AT_HWCAP uses a different number compared to AT_HWCAP on Linux as the numerical value was already in use for a different vector on FreeBSD. include/ChangeLog: * elf/common.h (AT_FREEBSD_EHDRFLAGS, AT_FREEBSD_HWCAP): Define. gdb/ChangeLog: * fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_EHDRFLAGS and AT_HWCAP.
2017-09-22LVU: dump loclists with locviewsAlexandre Oliva3-0/+17
When dumping location lists, also dump locview lists that may be interspersed with them, and bring view pairs next to the corresponding location list entries. This patch supports DW_AT_GNU_locviews as a separate attribute for DWARF4- loc_lists and split (dwo) loclists, as well as DWARF5 loclists. It also supports, in DWARF5 loclists, the proposed DW_LLE_GNU_view_pair loclist entry type proposed for DWARF6. The tests use 32-bit DWARF, even on 64-bit targets, resolving offsets to constants so as to reduce the risk that relocations be created for them, or that the offsets be rejected as nonconstants. The patch also adds an xfail to an unrelated test, namely dw5, so that no unexpected fails remain on nds32*-elf, one of the tested targets. Reviewed-by: Alan Modra <amodra@gmail.com> for include/ChangeLog * dwarf2.def (DW_AT_GNU_locviews): New. * dwarf2.h (enum dwarf_location_list_entry_type): Add DW_LLE_GNU_view_pair. (DW_LLE_view_pair): Define. for binutils/ChangeLog * dwarf.h (debug_info): Add loc_views and num_loc_views. * dwarf.c (vm1): New constant. (print_dwarf_view): New function. (read_and_display_attr_value): Support DW_AT_GNU_locviews. (process_debug_info): Keep num_loc_offsets and num_loc_views in sync. (display_view_pair_list): New function. (display_loc_list_dwo): Take vstart_ptr; update it. Dump location view pairs before the range they apply to, when a viewlist augments the loc list. (display_loc_list): Likewise. Check view numbers in range tests. (display_loclists_list): Likewise. Handle view pair entries, and warn on trailing ones. (loc_views): New variable. (loc_offsets_compar): Compare loc_views if loc_offsets are the same. (display_debug_loc): Check and sort loc_views too. Accept loc_view as expected_start. Skip if lists and views are the same. Dump locview list separately in order, and pass the locview list base to each list dump function. Warn and skip overlap and hole checking if we find loclists and locviews to not be adjacent. * testsuite/binutils-all/locview-1.s: New. * testsuite/binutils-all/readelf.locview-1: New. * testsuite/binutils-all/locview-2.s: New. * testsuite/binutils-all/readelf.locview-2: New. * testsuite/binutils-all/readelf.exp: Run new tests. Fix option spelling in pr18374 fail message. XFAIL dw5 test on nds32*-elf.
2017-09-15Sync libiberty/ & include/ with GCCPedro Alves12-81/+1737
Note this brings in the interface files for libcc1/G++ as well, which we will be needing in GDB soon anyway. That commit renamed a method in the C interface and that required a small update to GDB's compile/ code, which I've included that in this patch to keep the tree building. include/ChangeLog: 2017-09-15 Pedro Alves <palves@redhat.com> * ansidecl.h (DISABLE_COPY_AND_ASSIGN): New macro. 2017-09-12 Jiong Wang <jiong.wang@arm.com> * dwarf2.def (DW_CFA_AARCH64_negate_ra_state): New DW_CFA_DUP. * dwarf2.h (DW_CFA_DUP): New define. 2017-08-21 Richard Biener <rguenther@suse.de> * simple-object.h (simple_object_copy_lto_debug_sections): New function. 2017-05-18 Martin Liska <mliska@suse.cz> * ansidecl.h: Define CONSTEXPR macro. 2017-05-24 Nathan Sidwell <nathan@acm.org> * libiberty.h (ASTRDUP): Adjust cast to avoid warning. 2017-01-30 Alexandre Oliva <aoliva@redhat.com> Introduce C++ support in libcc1. * gcc-c-fe.def (int_type_v0): Rename from... (int_type): ... this. Introduce new version. (float_type_v0): Rename from... (float_type): ... this. Introduce new version. (char_type): New. * gcc-c-interface.h (gcc_c_api_version): Add GCC_C_FE_VERSION_1. (gcc_type_array): Move... * gcc-interface.h: ... here. * gcc-cp-fe.def: New. * gcc-cp-interface.h: New. 2016-04-29 Oleg Endo <olegendo@gcc.gnu.org> * longlong.h (umul_ppmm): Remove SHMEDIA checks. (__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations. 2017-09-15 Yao Qi <yao.qi@linaro.org> Pedro Alves <palves@redhat.com> * ansidecl.h (DISABLE_COPY_AND_ASSIGN): New macro. 2017-09-12 Jiong Wang <jiong.wang@arm.com> * dwarf2.def (DW_CFA_AARCH64_negate_ra_state): New DW_CFA_DUP. * dwarf2.h (DW_CFA_DUP): New define. 2017-08-21 Richard Biener <rguenther@suse.de> * simple-object.h (simple_object_copy_lto_debug_sections): New function. 2017-05-18 Martin Liska <mliska@suse.cz> * ansidecl.h: Define CONSTEXPR macro. 2017-05-24 Nathan Sidwell <nathan@acm.org> * libiberty.h (ASTRDUP): Adjust cast to avoid warning. 2017-01-30 Alexandre Oliva <aoliva@redhat.com> Introduce C++ support in libcc1. * gcc-c-fe.def (int_type_v0): Rename from... (int_type): ... this. Introduce new version. (float_type_v0): Rename from... (float_type): ... this. Introduce new version. (char_type): New. * gcc-c-interface.h (gcc_c_api_version): Add GCC_C_FE_VERSION_1. (gcc_type_array): Move... * gcc-interface.h: ... here. * gcc-cp-fe.def: New. * gcc-cp-interface.h: New. 2016-04-29 Oleg Endo <olegendo@gcc.gnu.org> * longlong.h (umul_ppmm): Remove SHMEDIA checks. (__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations. libiberty/ChangeLog: 2017-09-15 Nathan Sidwell <nathan@acm.org> PR demangler/82195 * cp-demangle.c (d_name): Add 'toplevel' parm. Pass to ... (d_local_name): ... here. Parse trailing function args on nested local_name. (d_encoding, d_special_name, d_class_enum_type): Adjust d_name calls. * testsuite/demangle-expected: Add tests. 2017-09-15 Richard Biener <rguenther@suse.de> PR lto/81968 * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections): Iterate marking dependent sections necessary. 2017-09-15 Nathan Sidwell <nathan@acm.org> * cp-demangle.c (is_fnqual_component_type): Reimplement using FNQUAL_COMPONENT_CASE. (d_encoding): Hold bare_function_type in local var. (d_local_name): Build name in both cases and build result once. Collapse switch-if to single conditional. (d_local_name): * testsuite/demangle-expected: Realign blank lines with tests. 2017-09-12 Jiong Wang <jiong.wang@arm.com> * dwarfnames.c (DW_CFA_DUP): New define. gdb/ChangeLog: 2017-09-15 Pedro Alves <palves@redhat.com> * compile/compile-c-types.c (convert_enum, convert_int) (convert_float): Adjust to refer to int_type_v0 and float_type_v0.
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen2-2/+6
2017-09-05Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556132-0/+6
include/ * elf/ppc.h (R_PPC_VLE_ADDR20): New relocation. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20. (ppc_elf_check_relocs): Handle it. (ppc_elf_vle_split20): New function. (ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20. binutils/ * readelf.c (get_elf_section_flags): Add VLE. (process_section_headers): Add VLE key to details. gas/ * config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag. (ppc_elf_section_letter): New function. * config/tc-ppc.h (md_elf_section_letter): New. * testsuite/gas/elf/section10.d: Adjust for VLE.
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov2-0/+24
include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise.
2017-08-23compile: Add 'set compile-gcc'Jan Kratochvil2-14/+54
As discussed in How to use compile & execute function in GDB https://sourceware.org/ml/gdb/2015-04/msg00026.html GDB currently searches for compilers on /usr/bin/ARCH-OS-gcc and chooses a match from there. However, it is not currently possible for the user to override which compiler to use. This is what this patch implements. It is also a sync between GCC's and GDB's interfaces. gdb/ChangeLog 2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com> * NEWS (Changes since GDB 7.9): Add set compile-gcc and show compile-gcc. * compile/compile.c (compile_gcc, show_compile_gcc): New. (compile_to_object): Implement compile_gcc. (_initialize_compile): Install "set compile-gcc". Initialize compile_gcc. gdb/doc/ChangeLog 2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com> * gdb.texinfo (Compiling and Injecting Code): Add to subsection "Compiler search for the compile command" descriptions of set compile-gcc and show compile-gcc. include/ChangeLog 2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com> * gcc-interface.h (enum gcc_base_api_version): Update comment for GCC_FE_VERSION_1. (struct gcc_base_vtable): Rename set_arguments to set_arguments_v0. Add set_arguments, set_triplet_regexp and set_driver_filename.
2017-08-23compile: set debug compile: Display GCC driver filenameJan Kratochvil2-8/+35
As discussed in How to use compile & execute function in GDB https://sourceware.org/ml/gdb/2015-04/msg00026.html GDB currently searches for compilers on /usr/bin/ARCH-OS-gcc and chooses a match from there. However, it is not currently possible for the user to display which compiler was selected. Up until now, GDB's compiler interface was not up-to-date with GCC's one, which means that it wasn't possible to obtain this information. This patch implements the mechanisms necessary for that. gdb/ChangeLog 2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com> * compile/compile.c (compile_to_object): Conditionally call set_verbose. Conditionally call compile or compile_v0. include/ChangeLog 2017-08-23 Jan Kratochvil <jan.kratochvil@redhat.com> * gcc-interface.h (enum gcc_base_api_version): Add GCC_FE_VERSION_1. (struct gcc_base_vtable): Rename compile to compile_v0. Update comment for compile. New methods set_verbose and compile.
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov2-0/+8
include/ * opcode/ppc.h (PPC_OPCODE_LSP): New define. opcodes/ * ppc-opc.c (insert_evuimm2_ex0): New function. (extract_evuimm2_ex0): Likewise. (insert_evuimm4_ex0): Likewise. (extract_evuimm4_ex0): Likewise. (insert_evuimm8_ex0): Likewise. (extract_evuimm8_ex0): Likewise. (insert_evuimm_lt16): Likewise. (extract_evuimm_lt16): Likewise. (insert_rD_rS_even): Likewise. (extract_rD_rS_even): Likewise. (insert_off_lsp): Likewise. (extract_off_lsp): Likewise. (RD_EVEN): New operand. (RS_EVEN): Likewise. (RSQ): Adjust. (EVUIMM_LT16): New operand. (HTM_SI): Adjust. (EVUIMM_2_EX0): New operand. (EVUIMM_4): Adjust. (EVUIMM_4_EX0): New operand. (EVUIMM_8): Adjust. (EVUIMM_8_EX0): New operand. (WS): Adjust. (VX_OFF): New operand. (VX_LSP): New macro. (VX_LSP_MASK): Likewise. (VX_LSP_OFF_MASK): Likewise. (PPC_OPCODE_LSP): Likewise. (vle_opcodes): Add LSP opcodes. * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. gas/ * testsuite/gas/ppc/lsp-checks.d, * testsuite/gas/ppc/lsp-checks.l, * testsuite/gas/ppc/lsp-checks.s: New test. * testsuite/gas/ppc/lsp.d, * testsuite/gas/ppc/lsp.s: New test. * testsuite/gas/ppc/ppc.exp: Run new tests.
2017-08-16Add new NT_PPC_* available since Linux 4.8Gustavo Romero2-0/+42
Add new note types available since Linux 4.8 to elf/common.h and make the 'readelf' tool aware of it. include/ * elf/common.h (NT_PPC_TAR): New macro. (NT_PPC_PPR): Likewise. (NT_PPC_DSCR): Likewise. (NT_PPC_EBB): Likewise. (NT_PPC_PMU): Likewise. (NT_PPC_TM_CGPR): Likewise. (NT_PPC_TM_CFPR): Likewise. (NT_PPC_TM_CVMX): Likewise. (NT_PPC_TM_CVSX): Likewise. (NT_PPC_TM_SPR): Likewise. (NT_PPC_TM_CTAR): Likewise. (NT_PPC_TM_CPPR): Likewise. (NT_PPC_TM_CDSCR): Likewise. binutils/ * readelf.c (get_note_type): Handle PPC note types available since Linux 4.8.
2017-08-06Treat common symbol as undefined for --no-define-commonH.J. Lu2-0/+8
When --no-define-common is used to build shared library, treat common symbol as undefined so that common symbols that are referenced from a shared library to be assigned addresses only in the main program. This eliminates the unused duplicate space in the shared library, and also prevents any possible confusion over resolving to the wrong duplicate when there are many dynamic modules with specialized search paths for runtime symbol resolution. --no-define-common is only allowed when building a shared library. bfd/ PR ld/21903: * elflink.c (elf_link_add_object_symbols): Treat common symbol as undefined for --no-define-common. include/ PR ld/21903: * bfdlink.h (bfd_link_info): Add inhibit_common_definition. ld/ PR ld/21903: * ld.h (command_line): Remove inhibit_common_definition. * ldgram.y: Replace command_line.inhibit_common_definition with link_info.inhibit_common_definition. * ldlang.c (lang_common): Likewise. * lexsup.c (parse_args): Likewise. * ldmain.c (main): Only allow --no-define-common with -shared. * testsuite/ld-elf/pr21903.s: New file. * testsuite/ld-elf/pr21903a.d: Likewise. * testsuite/ld-elf/pr21903b.d: Likewise. * testsuite/ld-elf/pr21903c.d: Likewise. * testsuite/ld-elf/pr21903d.d: Likewise. * testsuite/ld-elf/pr21903e.d: Likewise.
2017-07-31Fix compile time error when using ansidecl.h with an old version of GCC.Nick Clifton2-12/+24
PR 21850 * ansidecl.h (OVERRIDE): Protect check of __cplusplus value with #idef __cplusplus.
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu2-0/+5
include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (SJLI): Add. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_uimm12_20): New function. (UIMM12_20): New operand. (SIMM3_5_S): Adjust. * arc-tbl.h (sjli): Add new instruction.
2017-07-19[ARC] Add JLI support.John Eric Martin3-1/+27
The following relocation types were added to GCC/binutils: ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by GCC as well to adjust the index of function calls to functions with attribute jli_call_always. bfd/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c (JLI): Define. * reloc.c: Add JLI relocations. gas/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/jli-1.d: New file. * testsuite/gas/arc/jli-1.s: Likewise. * testsuite/gas/arc/taux.d: Update for jli_base. include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * elf/arc-reloc.def: Add JLI relocs howto. * opcode/arc-func.h (replace_jli): New function. ld/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * emulparams/arcelf.sh (JLI_START_TABLE): Define. * scripttempl/elfarc.sc: Handle jlitab section. * scripttempl/elfarcv2.sc: Likewise. * testsuite/ld-arc/arc.exp: Add JLI test. * testsuite/ld-arc/jli-script.ld: New file. * testsuite/ld-arc/jli-simple.dd: Likewise. * testsuite/ld-arc/jli-simple.rd: Likewise. * testsuite/ld-arc/jli-simple.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * arc-opc.c (UIMM10_6_S_JLIOFF): Define. (UIMM3_23): Adjust accordingly. * arc-regs.h: Add/correct jli_base register. * arc-tbl.h (jli_s): Likewise.
2017-07-18Fix spelling typos.Yuri Chornovian9-117/+134
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2-1/+6
When elf section size is beyond unsigned int max value, objdump fails to disassemble from that section. Ex on PowerPC, $ objdump -h /proc/kcore Idx Name Size VMA 4 load2 100000000 c000000000000000 Here, size of load2 section is 0x100000000. Also note that, 0xc00.... address range is kernel space for PowerPC. Now let's try to disassemble do_sys_open() using /proc/kcore. $ cat /proc/kallsyms | grep -A1 -w do_sys_open c00000000036c000 T do_sys_open c00000000036c2d0 T SyS_open Before patch: $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore /proc/kcore: file format elf64-powerpcle Disassembly of section load2: c00000000036c000 <load2+0x36c000>: c00000000036c000: Address 0xc00000000036c000 is out of bounds. Fix this by changing type of 'buffer_length' from unsigned int to size_t. After patch: $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore /proc/kcore: file format elf64-powerpcle Disassembly of section load2: c00000000036c000 <load2+0x36c000>: c00000000036c000: fc 00 4c 3c addis r2,r12,252 c00000000036c004: 00 53 42 38 addi r2,r2,21248 c00000000036c008: a6 02 08 7c mflr r0 include/ * dis-asm.h (struct disassemble_info): Change type of buffer_length field to size_t. opcodes/ * dis-buf.c (buffer_read_memory): Change type of end_addr_offset, max_addr_offset and octets variables to size_t.
2017-07-07Recognize the recently-added FreeBSD core dump note for LWP info.John Baldwin2-0/+5
This core dump note contains the same information returned by the ptrace PT_LWPINFO operation for each LWP belonging to a process. binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): Handle NT_FREEBSD_PTLWPINFO. include/ChangeLog: * elf/common.h (NT_FREEBSD_PTLWPINFO): Define.
2017-07-02Import include/+libiberty/ r249883 from upstream GCC.Jan Kratochvil3-12/+34
include/ChangeLog 2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com> * dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset) (DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user) (DW_IDX_GNU_internal, DW_IDX_GNU_external): New. * dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New. (enum dwarf_name_index_attribute): Remove. (get_DW_IDX_name): New declaration. libiberty/ChangeLog 2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com> * dwarfnames.c (DW_FIRST_IDX, DW_END_IDX, DW_IDX, DW_IDX_DUP): New.
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay2-0/+10
PR gas/21683 include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr. gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it. (AVR Pseudo Instructions): New node. * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook. (md_undefined_symbol): Define to avr_undefined_symbol. (avr_pre_output_hook, avr_undefined_symbol): New protos. * config/tc-avr.c (struc-symbol.h): Include it. (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums. (avr_isr, avr_gccisr_opcode) (avr_no_sreg_hash, avr_no_sreg): New static variables. (avr_opt_s) <have_gccisr>: Add field. (avr_opt): Add initializer for have_gccisr. (enum options) <OPTION_HAVE_GCCISR>: Add enum. (md_longopts) <"mgcc-isr">: Add entry. (md_show_usage): Document -mgcc-isr. (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it. (md_undefined_symbol): Remove. (avr_undefined_symbol, avr_pre_output_hook): New fuctions. (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them. (avr_operand) <pregno>: Add argument and set *pregno if function is called for a register constraint. [N]: Handle constraint. (avr_operands) <avr_operand>: Pass 5th parameter to calls. [avr_opt.have_gccisr]: Call avr_update_gccisr. Call avr_gccisr_operands instead of avr_operands. (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag) (avr_gccisr_operands, avr_check_gccisr_done): New static functions. * testsuite/gas/avr/gccisr-01.d: New test. * testsuite/gas/avr/gccisr-01.s: New test. * testsuite/gas/avr/gccisr-02.d: New test. * testsuite/gas/avr/gccisr-02.s: New test. * testsuite/gas/avr/gccisr-03.d: New test. * testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2-0/+8
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-29S390: Support guarded-storage core note sectionsAndreas Arnez2-0/+9
Newer Linux kernel versions offer two new register sets in support of the z/Architecture's guarded storage facility: NT_S390_GS_CB, the "guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage broadcast control block". This patch adds support for the respective core notes sections to binutils. bfd/ChangeLog: * elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype. (elfcore_write_s390_gs_bc): Likewise. * elf.c (elfcore_grok_s390_gs_cb): New function. (elfcore_grok_s390_gs_bc): New function. (elfcore_grok_note): Call them. (elfcore_write_s390_gs_cb): New function. (elfcore_write_s390_gs_bc): New function. (elfcore_write_register_note): Call them. binutils/ChangeLog: * readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC. include/ChangeLog: * elf/common.h (NT_S390_GS_CB): New macro. (NT_S390_GS_BC): Likewise.
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina2-0/+7
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod.
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2-1/+9
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki3-5/+33
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-26RISC-V: Use pc-relative relocation for FDE initial locationKuan-Lin Chen2-0/+5
The symbol address in .eh_frame may be adjusted in _bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert a relocation whose addend symbol is in .eh_frame. Othrewise, the value may be adjusted twice. bfd/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elfnn-riscv.c (perform_relocation): Support the new R_RISCV_32_PCREL relocation. (riscv_elf_relocate_section): Likewise. * elfxx-riscv.c (howto_table): Likewise. (riscv_reloc_map): Likewise. * bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation. * libbfd.h: Regenerate. gas/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a R_RISCV_32_PCREL relocation. include/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elf/riscv.h (R_RISCV_32_PCREL): New.
2017-06-26Add pgste marker changelogAndreas Krebbel1-0/+4
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme3-1/+18
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro.
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme2-5/+15
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to remove special casing for ARMv6S-M autodetection. === Motivation === Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor architectures with extra checks in the handler function (do_t_swi) to give an error message when ARMv6-M is targeted and some more special casing in aeabi_set_public_attributes. This was made to exclude these mnemonics for ARMv6-M unless the OS extension is in use. However this logic is superfluous: there is already code to check whether an instruction is available based on the feature bit it is part of and whether the targeted architecture has that feature bit. This patch aims at removing that unneeded complexity. === Patch description === The OS extension is already limited to the ARMv6-M architecture so all this patch does is redefined availability of the ARM_EXT_OS feature bit to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any change either because it already includes ARM_EXT_OS. The patch also make sure that the error message that was given by do_t_swi when SWI/SVC is unavailable is still the same by detecting the situation in md_assemble. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v6m): Delete. (arm_ext_v7m): Delete. (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M profile. (arm_arch_v6m_only): Delete. (do_t_swi): Remove special case for ARMv6S-M. (md_assemble): Display error message previously in do_t_swi when SVC is not available. (insns): Guard swi and svc by arm_ext_os for Thumb mode. (aeabi_set_public_attributes): Remove special case for ARMv6S-M. include/ * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set. (ARM_AEXT_V4T): Likewise. (ARM_AEXT_V5TxM): Likewise. (ARM_AEXT_V5T): Likewise. (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-23S/390: Add support for pgste markerAndreas Krebbel1-0/+3
This patch adds a new S/390 specific segment type: PT_S390_PGSTE. For binaries marked with that segment the kernel will allocate 4k page tables. The only user so far will be qemu. ld/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * Makefile.in: Add s390.em as build dependency. * emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em. * emultempl/s390.em: New file. * gen-doc.texi: Add documentation for --s390-pgste option. * ld.texinfo: Likewise. include/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf/s390.h (PT_S390_PGSTE): Define macro. binutils/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * readelf.c (get_s390_segment_type): Add support for the new segment type PT_S390_PGSTE. (get_segment_type): Call get_s390_segment_type. elfcpp/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elfcpp.h (enum PT): Add PT_S390_PGSTE to enum. bfd/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf-s390.h: New file. * elf64-s390.c (struct elf_s390_link_hash_table): Add params field. (elf_s390_additional_program_headers): New function. (elf_s390_modify_segment_map): New function. (bfd_elf_s390_set_options): New function. (elf_backend_additional_program_headers) (elf_backend_modify_segment_map): Add macro definitions.
2017-06-22x86: Support Intel Shadow Stack with SHSTK propertyH.J. Lu3-0/+9
To support Intel Shadow Stack (SHSTK) in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) is added to GNU program properties to indicate that all executable sections are compatible with SHSTK where return address popped from shadow stack always matches return address popped from normal stack. GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all relocatable inputs. bfd/ * elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_i386_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. * elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_x86_64_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. binutils/ * readelf.c (decode_x86_feature): Decode GNU_PROPERTY_X86_FEATURE_1_SHSTK. * testsuite/binutils-all/i386/shstk.d: New file. * testsuite/binutils-all/i386/shstk.s: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. * testsuite/binutils-all/x86-64/shstk.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add shstk. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New. ld/ * NEWS: Mention -z shstk and GNU_PROPERTY_X86_FEATURE_1_SHSTK. * emulparams/cet.sh (PARSE_AND_LIST_OPTIONS_CET): Add "-z shstk". (PARSE_AND_LIST_ARGS_CASE_Z_CET): Support "-z shstk". * ld.texinfo: Document -z shstk. * testsuite/ld-i386/i386.exp: Run SHSTK tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/property-x86-shstk.s: New file. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk.s: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
2017-06-22x86: Support Intel IBT with IBT property and IBT-enable PLTH.J. Lu3-0/+15
To support IBT in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 #define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) are added to GNU program properties to indicate that all executable sections are compatible with IBT when ENDBR instruction starts each valid target where an indirect branch instruction can land. GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on all relocatable inputs. The followings changes are made to the Procedure Linkage Table (PLT): 1. For 64-bit x86-64, PLT is changed to PLT0: push GOT[1] bnd jmp *GOT[2] nop ... PLTn: endbr64 push namen_reloc_index bnd jmp PLT0 together with the second PLT section: PLTn: endbr64 bnd jmp *GOT[namen_index] nop BND prefix is also added so that IBT-enabled PLT is compatible with MPX. 2. For 32-bit x86-64 (x32) and i386, PLT is changed to PLT0: push GOT[1] jmp *GOT[2] nop ... PLTn: endbr64 # endbr32 for i386. push namen_reloc_index jmp PLT0 together with the second PLT section: PLTn: endbr64 # endbr32 for i386. jmp *GOT[namen_index] nop BND prefix isn't used since MPX isn't supported on x32 and BND registers aren't used in parameter passing on i386. GOT is an array of addresses. Initially, GOT[namen_index] is filled with the address of the ENDBR instruction of the corresponding entry in the first PLT section. The function, namen, is called via the ENDBR instruction in the second PLT entry. GOT[namen_index] is updated to the actual address of the function, namen, at run-time. 2 linker command line options are added: 1. -z ibtplt: Generate IBT-enabled PLT. 2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program properties as well as IBT-enabled PLT. bfd/ * elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New. (elf_i386_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_lazy_ibt_plt0_entry): Likewise. (elf_i386_non_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_non_lazy_ibt_plt_entry): Likewise. (elf_i386_eh_frame_lazy_ibt_plt): Likewise. (elf_i386_lazy_plt_layout): Likewise. (elf_i386_non_lazy_plt_layout): Likewise. (elf_i386_link_hash_entry): Add plt_second. (elf_i386_link_hash_table): Add plt_second and plt_second_eh_frame. (elf_i386_allocate_dynrelocs): Use the second PLT if needed. (elf_i386_size_dynamic_sections): Use .plt.got unwind info for the second PLT. Check the second PLT. (elf_i386_relocate_section): Use the second PLT to resolve PLT reference if needed. (elf_i386_finish_dynamic_symbol): Fill and use the second PLT if needed. (elf_i386_finish_dynamic_sections): Set sh_entsize on the second PLT. Generate unwind info for the second PLT. (elf_i386_plt_type): Add plt_second. (elf_i386_get_synthetic_symtab): Support the second PLT. (elf_i386_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_i386_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_i386_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. * elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New. (elf_x32_lazy_ibt_plt_entry): Likewise. (elf_x86_64_non_lazy_ibt_plt_entry): Likewise. (elf_x32_non_lazy_ibt_plt_entry): Likewise. (elf_x86_64_eh_frame_lazy_ibt_plt): Likewise. (elf_x32_eh_frame_lazy_ibt_plt): Likewise. (elf_x86_64_lazy_ibt_plt): Likewise. (elf_x32_lazy_ibt_plt): Likewise. (elf_x86_64_non_lazy_ibt_plt): Likewise. (elf_x32_non_lazy_ibt_plt): Likewise. (elf_x86_64_get_synthetic_symtab): Support the second PLT. (elf_x86_64_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_x86_64_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_x86_64_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. binutils/ * readelf.c (decode_x86_feature): New. (print_gnu_property_note): Call decode_x86_feature on GNU_PROPERTY_X86_FEATURE_1_AND. * testsuite/binutils-all/i386/empty.d: New file. * testsuite/binutils-all/i386/empty.s: Likewise. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/ibt.s: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/empty.s: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/ibt.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add ibtplt and ibt. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New. (GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh. * Makefile.in: Regenerated. * NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt and -z ibt. * emulparams/cet.sh: New file. * testsuite/ld-i386/ibt-plt-1.d: Likewise. * testsuite/ld-i386/ibt-plt-1.s: Likewise. * testsuite/ld-i386/ibt-plt-2.s: Likewise. * testsuite/ld-i386/ibt-plt-2a.d: Likewise. * testsuite/ld-i386/ibt-plt-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3.s: Likewise. * testsuite/ld-i386/ibt-plt-3a.d: Likewise. * testsuite/ld-i386/ibt-plt-3b.d: Likewise. * testsuite/ld-i386/ibt-plt-3c.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/plt-main-ibt.dd: Likewise. * testsuite/ld-i386/plt-pie-ibt.dd: Likewise. * testsuite/ld-i386/property-x86-empty.s: Likewise. * testsuite/ld-i386/property-x86-ibt.s: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3.s: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise. * testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise. * testsuite/ld-x86-64/plt-main-ibt.dd: Likewise. * testsuite/ld-x86-64/property-x86-empty.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * emulparams/elf32_x86_64.sh: Source emulparams/cet.sh. (TINY_READONLY_SECTION): Add .plt.sec. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Source emulparams/cet.sh. * ld.texinfo: Document -z ibtplt and -z ibt. * testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme2-0/+5
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to rework the Tag_CPU_arch build attribute value selection to (i) match architecture or CPU if specified by user without any need for hack and (ii) match an architecture with all the features used if in autodetection mode or return an error. === Motivation === Currently, Tag_CPU_arch build attribute value selection assumes that an architecture is always a superset of architectures released earlier. As such, the logic is to browse architectures in chronological order of release and selecting the Tag_CPU_arch value of the last one to contribute a feature used[1]/requested[2] not contributed by earlier architectures. [1] in case of autodetection mode [2] otherwise, ie. in case of -mcpu/-march or associated directives This logic fails the two objectives mentionned in the Context section. First, due to the assumption it does an architecture can be selected while not having all the features used/requested which fails the second objective. Second, not doing an exact match when an architecture or CPU is selected by the user means the wrong value is chosen when a later architecture provides a subset of the feature bits of an earlier architecture. This is the case for the implementation of ARMv8-R (see later patch). An added benefit of this patch is that it is possible to easily generate more consistent build attribute by setting the feature bits from the architecture matched in aeabi_set_public_attributes in autodetection mode. This is better done as a separate patch because lots of testcase' expected results must then be updated accordingly. === Patch description === The patch changes the main logic for Tag_CPU_arch and Tag_CPU_arch_profile values selection to: - look for an exact match in case an architecture or CPU was specified on the command line or in a directive - select the first released architecture that provides a superset of the feature used in the autodetection case - select the most featureful architecture in case of -march=all The array cpu_arch_ver is updated to include all architectures in order to make the first point work. Note that when looking for an exact match, the architecture with selected extension is tried first and then only the architecture. This is because some architectures are exactly equivalent to an earlier architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS extension) and ARMv6KZ (ARMv6K + security extension) are two such examples. Other adjustments are also necessary in aeabi_set_public_attributes to make this change work. 1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the absence of feature bit used/requested to decide whether to give the default value for empty files (see EABI attribute defaults test). It was previously checking that arch == 0 which would only happen if no feature bit could be matched by any architecture, ie there is no feature bit to match. 2) A fallback to a superset match must exist when no_cpu_selected () returns true. This is because aeabi_set_public_attributes is called again after relaxation and at this point selected_cpu is set from the previous execution of that function. There is therefore no way to check whether the user specified an architecture or CPU. 3) Tag_CPU_arch lines are removed from expected output when the detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch value for pre-ARMv4 architectures and default value for an absent entry is 0. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (fpu_any): Defined from FPU_ANY. (cpu_arch_ver): Add all architectures and sort by release date. (have_ext_for_needed_feat_p): New. (get_aeabi_cpu_arch_from_fset): New. (aeabi_set_public_attributes): Call above function to determine Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use and Tag_THUMB_ISA_use selection logic to check absence of feature bit accordingly. * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build attribute value. * testsuite/gas/arm/attr-march-armv2.d: Likewise. * testsuite/gas/arm/attr-march-armv2a.d: Likewise. * testsuite/gas/arm/attr-march-armv2s.d: Likewise. * testsuite/gas/arm/attr-march-armv3.d: Likewise. * testsuite/gas/arm/attr-march-armv3m.d: Likewise. * testsuite/gas/arm/pr12198-2.d: Likewise. include/ * opcode/arm.h (FPU_ANY): New macro.
2017-06-16Rewrite __start and __stop symbol handlingAlan Modra2-3/+8
This arranges for __start and __stop symbols to be defined before garbage collection, for all target formats. That should allow the COFF and PE --gc-sections to keep a singleton orphan input section, a feature lost by 2017-06-13 commit cbd0eecf26. The fancier ELF treatment of keeping all input sections associated with a __start or __stop symbol, from 2015-10-23 commit 1cce69b9dc, is retained. .startof. and .sizeof. symbols are deliberately not defined before garbage collection, so these won't affect garbage collection of sections. The patch also ensures __start, __stop, .startof. and .sizeof. symbols are defined before target size_dynamic_sections is called, albeit with a preliminary value, so that target code doesn't need to cope with a symbol changing from undefined at size_dynamic_sections to defined at relocate_section. Also, a number of problems with the testcases have been fixed. PR ld/20022 PR ld/21557 PR ld/21562 PR ld/21571 include/ * bfdlink.h (struct bfd_link_hash_entry): Delete undef.section. bfd/ * targets.c (struct bfd_target): Add _bfd_define_start_stop. (BFD_JUMP_TABLE_LINK): Likewise. * elf-bfd.h (bfd_elf_define_start_stop): Declare. * elflink.c (_bfd_elf_gc_mark_rsec): Update comment. (bfd_elf_define_start_stop): New function. * linker.c (bfd_generic_define_start_stop): New function. * coff64-rs6000.c (rs6000_xcoff64_vec, rs6000_xcoff64_aix_vec): Init new field. * aout-adobe.c (aout_32_bfd_define_start_stop): Define. * aout-target.h (MY_bfd_define_start_stop): Define. * aout-tic30.c (MY_bfd_define_start_stop): Define. * binary.c (binary_bfd_define_start_stop): Define. * bout.c (b_out_bfd_define_start_stop): Define. * coff-alpha.c (_bfd_ecoff_bfd_define_start_stop): Define. * coff-mips.c (_bfd_ecoff_bfd_define_start_stop): Define. * coff-rs6000.c (_bfd_xcoff_bfd_define_start_stop): Define. * coffcode.h (coff_bfd_define_start_stop): Define. * elfxx-target.h (bfd_elfNN_bfd_define_start_stop): Define. * i386msdos.c (msdos_bfd_define_start_stop): Define. * i386os9k.c (os9k_bfd_define_start_stop): Define. * ieee.c (ieee_bfd_define_start_stop): Define. * ihex.c (ihex_bfd_define_start_stop): Define. * libbfd-in.h (_bfd_nolink_bfd_define_start_stop): Define. * mach-o-target.c (bfd_mach_o_bfd_define_start_stop): Define. * mmo.c (mmo_bfd_define_start_stop): Define. * nlm-target.h (nlm_bfd_define_start_stop): Define. * oasys.c (oasys_bfd_define_start_stop): Define. * pef.c (bfd_pef_bfd_define_start_stop): Define. * plugin.c (bfd_plugin_bfd_define_start_stop): Define. * ppcboot.c (ppcboot_bfd_define_start_stop): Define. * som.c (som_bfd_define_start_stop): Define. * srec.c (srec_bfd_define_start_stop): Define. * tekhex.c (tekhex_bfd_define_start_stop): Define. * versados.c (versados_bfd_define_start_stop): Define. * vms-alpha.c (vms_bfd_define_start_stop): Define. (alpha_vms_bfd_define_start_stop): Define. * xsym.c (bfd_sym_bfd_define_start_stop): Define. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Don't set __start/__stop syms here. * ldlang.c (lang_set_startof): Delete. (start_stop_syms, start_stop_count, start_stop_alloc): New vars. (lang_define_start_stop, lang_init_start_stop, foreach_start_stop, undef_start_stop, lang_undef_start_stop, lang_init_startof_sizeof, set_start_stop, lang_finalize_start_stop): New functions. (lang_process): Call _start_stop functions. * testsuite/ld-elf/pr21562a.d: Use xfail rather than notarget. Correct typos and list of xfail targets. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562e.d: Likewise. * testsuite/ld-elf/pr21562f.d: Likewise. * testsuite/ld-elf/pr21562g.d: Likewise. * testsuite/ld-elf/pr21562h.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/sizeofa.d: Likewise. Adjust to pass for generic ELF. * testsuite/ld-elf/sizeofb.d: Likewise. * testsuite/ld-elf/startofa.d: Likewise. * testsuite/ld-elf/startofb.d: Likewise.
2017-06-14Don't use print_insn_XXX in GDBYao Qi2-8/+8
This is a follow-up to [PATCH 0/6] Unify the disassembler selection in gdb and objdump https://sourceware.org/ml/binutils/2017-05/msg00192.html that is, opcodes is able to select the right disassembler, so gdb doesn't have to select them. Instead, gdb can just use default_print_insn. As a result, these print_insn_XXX are not used out of opcodes, so this patch also moves their declarations from include/dis-asm.h to opcodes/disassemble.h. With this change, GDB doesn't use any print_insn_XXX directly any more. gdb: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_gdb_print_insn): Call default_print_insn instead of print_insn_aarch64. * arm-tdep.c (gdb_print_insn_arm): Call default_print_insn instead of print_insn_big_arm and print_insn_little_arm. * i386-tdep.c (i386_print_insn): Call default_print_insn instead of print_insn_i386. * ia64-tdep.c (ia64_print_insn): Call default_print_insn instead of print_insn_ia64. * mips-tdep.c (gdb_print_insn_mips): Call default_print_insn instead of print_insn_big_mips and print_insn_little_mips. * spu-tdep.c (gdb_print_insn_spu): Call default_print_insn instead of print_insn_spu. include: 2017-06-14 Yao Qi <yao.qi@linaro.org> * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. (print_insn_spu): Likewise. opcodes: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. * arm-dis.c: Likewise. * ia64-dis.c: Likewise. * mips-dis.c: Likewise. * spu-dis.c: Likewise. * disassemble.h (print_insn_aarch64): New declaration, moved from include/dis-asm.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise.
generated by cgit v1.1 at 2024-11-20 12:19:19 +0000