| Age | Commit message (Collapse) | Author | Files | Lines |
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* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
and pitlb.
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2005-07-27 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add comment to movd. Use LongMem for all
movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
Add movq-s as 64-bit variants of movd-s.
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implicit space-register addressing. Set space-register bits on opcodes
using implicit space-register addressing. Add various missing pa20
long-immediate opcodes. Remove various opcodes using implicit 3-bit
space-register addressing. Use "fE" instead of "fe" in various
fstw opcodes.
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2005-07-18 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Operands of aam and aad are unsigned.
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2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.h (CpuVMX): New.
(CpuUnknownFlags): Add CpuVMX.
gas/testsuite/
2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add vmx and x86-64-vmx.
* gas/i386/vmx.d: New file.
* gas/i386/vmx.s: Likewise.
* gas/i386/x86-64-vmx.d: Likewise.
* gas/i386/x86-64-vmx.s: Likewise.
include/opcode/
2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel VMX Instructions.
opcodes/
2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
(VMX_Fixup): New. Fix up Intel VMX Instructions.
(Em): New.
(Gm): New.
(VM): New.
(dis386_twobyte): Updated entries 0x78 and 0x79.
(twobyte_has_modrm): Likewise.
(grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
(OP_G): Handle m_mode.
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2005-07-05 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuSVME): New.
(CpuUnknownFlags): Include CpuSVME.
* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
as alias of sledgehammer.
(md_assemble): Include invlpga in the check for insns with two source
operands.
(process_operands): Include SVME insns in the check for ignored
segment overrides. Adjust diagnostic.
(i386_index_check): Special-case SVME insns with memory operands.
gas/testsuite/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* gas/i386/svme.d: New.
* gas/i386/svme.s: New.
* gas/i386/svme64.d: New.
* gas/i386/i386.exp: Run new tests.
include/opcode/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add new insns.
opcodes/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (SVME_Fixup): New.
(grps): Use it for the lidt entry.
(PNI_Fixup): Call OP_M rather than OP_E.
(INVLPG_Fixup): Likewise.
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2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* config/tc-i386.c (md_assemble): Don't call optimize_disp on
movabs.
(optimize_disp): Optimize only if possible. Don't use 64bit
displacement on non-constants and do same on constants if
possible.
gas/testsuite/
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* i386/x86_64.s: Add absolute 64bit addressing tests for mov.
* i386/x86_64.s: Updated.
include/opcode/
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013
* i386.h (i386_optab): Update comments for 64bit addressing on
mov. Allow 64bit addressing for mov and movq.
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respectively, in various floating-point load and store patterns.
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(pa_opcodes): Update load and store entries to allow both PA 1.X and
PA 2.0 mneumonics when equivalent. Entries with cache control
completers now require PA 1.1. Adjust whitespace.
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2005-05-09 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (parse_insn): Disallow use of prefix separator
and comma in Intel mode.
include/opcode/
2005-05-09 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add ht and hnt.
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* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr. Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
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* opcode/m88k.h: Rename psr macros to avoid conflicts.
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* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
adjust them accordingly.
gas/ChangeLog:
* config/tc-i386.c (output_insn): Handle VIA PadLock instructions
similar to other instructions now that they're marked as ImmExt.
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2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add rdtscp.
opcodes/
2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
easier future additions.
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2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
x86-64-segment and x86-64-inval-seg for x86-64.
* gas/i386/intel.d: Expect movw for moving between memory and
segment register.
* gas/i386/naked.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/opcode.s: Use movw for moving between memory and
segment register.
* gas/i386/x86-64-opcode.s: Likewise.
* : Likewise.
* gas/i386/inval-seg.l: New.
* gas/i386/inval-seg.s: New.
* gas/i386/segment.l: New.
* gas/i386/segment.s: New.
* gas/i386/x86-64-inval-seg.l: New.
* gas/i386/x86-64-inval-seg.s: New.
* gas/i386/x86-64-segment.l: New.
* gas/i386/x86-64-segment.s: New.
include/opcode/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Don't allow the `l' suffix for moving
moving between memory and segment register. Allow movq for
moving between general-purpose register and segment register.
opcodes/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SEG_Fixup): New.
(Sv): New.
(dis386): Use "Sv" for 0x8c and 0x8e.
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* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
and ARM_ARCH_V6ZKT2.
opcodes:
* arm-dis.c (arm_opcodes): Document %E and %V.
Add entries for v6T2 ARM instructions:
bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
(print_insn_arm): Add support for %E and %V.
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2005-02-09 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.s: Remove comments disabling alternative forms of
fbld, fbstp, and fldcw.
* gas/i386/intelok.d: Expect two instances of fbld, fbstp, and fldcw.
include/opcode/
2005-02-09 Jan Beulich <jbeulich@novell.com>
PR gas/707
* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
fnstsw.
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2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* elf32-frv.c (elf32_frv_relocate_section): Force local binding
for TLSMOFF.
* reloc.c: Add R_FRV_TLSMOFF.
* elf32-frv.c (elf32_frv_howto_table): Likewise.
(frv_reloc_map, frv_reloc_type_lookup): Map it.
(elf32_frv_relocate_section): Handle it.
(elf32_frv_check_relocs): Likewise.
* libbfd.h, bfd-in2.h: Rebuilt.
2004-11-26 Alexandre Oliva <aoliva@redhat.com>
* elf32-frv.c (_frvfdpic_emit_got_relocs_plt_entries): Don't crash
when given an undefweak TLS symbol. Fix constant TLS PLT entries
such that they return the constant in gr9.
(_frvfdpic_relax_tls_entries): Don't crash for undefweak TLS
symbols.
(_frvfdpic_size_got_plt): Set _cooked_size of dynamic sections.
too, such that they shrink on relaxation.
(elf32_frvfdpic_finish_dynamic_sections): Check __ROFIXUP_END__ as
marking the position right past the _GLOBAL_OFFSET_TABLE_ value.
(_frvfdpic_assign_plt_entries): Shrink constant TLS PLT entries
if we can guarantee the use of 16-bit constants.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
Introduce TLS support for FR-V FDPIC.
* reloc.c: Add TLS relocations.
* elf32-frv.c (elf32_frv_howto_table): Add TLS relocations.
(elf32_frv_rel_tlsdesc_value_howto): New.
(elf32_frv_rel_tlsoff_howto): New.
(frv_reloc_map): Add new mappings.
(struct frvfdpic_elf_link_hash_table): Add pointer to summary
reloc information.
(frvfdpic_dynamic_got_plt_info): New.
(frvfdpic_plt_tls_ret_offset): New.
(ELF_DYNAMIC_INTERPRETER, DEFAULT_STACK_SIZE): Move earlier.
(struct _frvfdpic_dynamic_got_info): Likewise. Add TLS members.
(struct _frvfdpic_dynamic_got_plt_info): Likewise.
(FRVFDPIC_SYM_LOCAL): Regard symbols defined in the absolute
section as local.
(struct frvfdpic_relocs_info): Add TLS fields.
(frvfdpic_relocs_info_hash): Warning clean up.
(frvfdpic_relocs_info_find): Initialize tlsplt_entry.
(frvfdpic_pic_merge_early_relocs_info): Merge TLS fields.
(FRVFDPIC_TLS_BIAS): Define.
(tls_biased_base): New.
(_frvfdpic_emit_got_relocs_plt_entries): Deal with TLS
relocations.
(frv_reloc_type_lookup): Likewise.
(frvfdpic_info_to_howto_rel): Likewise.
(elf32_frv_relocate_section): Likewise.
(_frv_create_got_section): Create the PLT section here.
(elf32_frvfdpic_create_dynamic_sections): Not here.
(_frvfdpic_count_nontls_entries): Move out of...
(_frvfdpic_count_got_plt_entries): ... here.
(_frvfdpic_count_tls_entries): Likewise. Add TLS support.
(_frvfdpic_count_relocs_fixups): Likewise. Add relaxation
support.
(_frvfdpic_relax_tls_entries): New.
(_frvfdpic_compute_got_alloc_data): Add TLS support.
(_frvfdpic_get_tlsdesc_entry): New.
(_frvfdpic_assign_got_entries): Add TLS support.
(_frvfdpic_assign_plt_entries): Likewise.
(_frvfdpic_reset_got_plt_entries): New.
(_frvfdpic_size_got_plt): Move out of...
(elf32_frvfdpic_size_dynamic_sections): ... here.
(_frvfdpic_relax_got_plt_entries): New.
(elf32_frvfdpic_relax_section): New.
(elf32_frvfdpic_finish_dynamic_sections): Add TLS sanity check.
(elf32_frv_check_relocs): Add TLS support.
(bfd_elf32_bfd_relax_section): Define for FDPIC.
* libbfd.h, bfd-in2.h: Rebuilt.
cpu/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv.cpu: Add support for TLS annotations in loads and calll.
* frv.opc (parse_symbolic_address): New.
(parse_ldd_annotation): New.
(parse_call_annotation): New.
(parse_ld_annotation): New.
(parse_ulo16, parse_uslo16): Use parse_symbolic_address.
Introduce TLS relocations.
(parse_d12, parse_s12, parse_u12): Likewise.
(parse_uhi16): Likewise. Fix constant checking on 64-bit host.
(parse_call_label, print_at): New.
gas/ChangeLog:
* config/tc-frv.c (md_apply_fix3): Mark TLS symbols as such.
2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* config/tc-frv.c (frv_pic_ptr): Add tlsmoff support.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* cgen.c (gas_cgen_parse_operand): Handle
CGEN_PARSE_OPERAND_SYMBOLIC.
* config/tc-frv.c (md_cgen_lookup_reloc): Handle TLS relocations.
(frv_force_relocation): Likewise. Fix handling of PIC
relocations.
(md_apply_fix3): Likewise.
include/elf/ChangeLog:
2004-12-10 Alexandre Oliva <aoliva@redhat.com>
* frv.h: Add R_FRV_TLSMOFF.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv.h: Add TLS relocations.
include/opcode/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* cgen.h (enum cgen_parse_operand_type): Add
CGEN_PARSE_OPERAND_SYMBOLIC.
ld/testsuite/ChangeLog:
* ld-frv/fdpic.exp: Add -mfdpic to ASFLAGS.
* ld-frv/tls.exp: Likewise.
2004-11-26 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/tls-3.s: New.
* ld-frv/tls-static-3.d: New.
* ld-frv/tls-dynamic-3.d: New.
* ld-frv/tls-pie-3.d: New.
* ld-frv/tls-shared-3.d: New.
* ld-frv/tls-relax-static-3.d: New.
* ld-frv/tls-relax-dynamic-3.d: New.
* ld-frv/tls-relax-pie-3.d: New.
* ld-frv/tls-relax-shared-3.d: New.
* ld-frv/tls.exp: Run the new tests.
* ld-frv/tls-dynamic-2.d: Adjust for improved relaxation.
* ld-frv/tls-relax-dynamic-2.d: Likewise.
* ld-frv/tls-relax-initial-shared-2.d: Likewise.
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/tls-1-dep.s: New.
* ld-frv/tls-1-shared.lds: New.
* ld-frv/tls-1.s: New.
* ld-frv/tls-2.s: New.
* ld-frv/tls-dynamic-1.d: New.
* ld-frv/tls-dynamic-2.d: New.
* ld-frv/tls-initial-shared-2.d: New.
* ld-frv/tls-pie-1.d: New.
* ld-frv/tls-relax-dynamic-1.d: New.
* ld-frv/tls-relax-dynamic-2.d: New.
* ld-frv/tls-relax-initial-shared-2.d: New.
* ld-frv/tls-relax-pie-1.d: New.
* ld-frv/tls-relax-shared-1.d: New.
* ld-frv/tls-relax-shared-2.d: New.
* ld-frv/tls-relax-static-1.d: New.
* ld-frv/tls-shared-1-fail.d: New.
* ld-frv/tls-shared-1.d: New.
* ld-frv/tls-shared-2.d: New.
* ld-frv/tls-static-1.d: New.
* ld-frv/tls.exp: New.
* ld-frv/fdpic-pie-1.d: Adjust for 64-bit host.
* ld-frv/fdpic-pie-2.d: Likewise.
* ld-frv/fdpic-pie-6.d: Likewise.
* ld-frv/fdpic-pie-7.d: Likewise.
* ld-frv/fdpic-pie-8.d: Likewise.
* ld-frv/fdpic-shared-1.d: Likewise.
* ld-frv/fdpic-shared-2.d: Likewise.
* ld-frv/fdpic-shared-3.d: Likewise.
* ld-frv/fdpic-shared-4.d: Likewise.
* ld-frv/fdpic-shared-5.d: Likewise.
* ld-frv/fdpic-shared-6.d: Likewise.
* ld-frv/fdpic-shared-7.d: Likewise.
* ld-frv/fdpic-shared-8.d: Likewise.
* ld-frv/fdpic-shared-local-2.d: Likewise.
* ld-frv/fdpic-shared-local-8.d: Likewise.
* ld-frv/fdpic-static-1.d: Likewise.
* ld-frv/fdpic-static-2.d: Likewise.
* ld-frv/fdpic-static-6.d: Likewise.
* ld-frv/fdpic-static-7.d: Likewise.
* ld-frv/fdpic-static-8.d: Likewise.
opcodes/ChangeLog:
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv-asm.c: Rebuilt.
* frv-desc.c: Rebuilt.
* frv-desc.h: Rebuilt.
* frv-dis.c: Rebuilt.
* frv-ibld.c: Rebuilt.
* frv-opc.c: Rebuilt.
* frv-opc.h: Rebuilt.
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* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
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* mips.h (struct mips_opcode): Add new pinfo2 member.
(INSN_ALIAS): New define for opcode table entries that are
specific instances of another entry, such as 'move' for an 'or'
with a zero operand.
(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
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(OPCODE_IS_MEMBER): Handle CPU_RM9000.
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* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
Remove redundant instruction types.
(struct argument): X_op - new field.
(struct cst4_entry): Remove.
(no_op_insn): Declare.
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2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
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2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
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* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
gas/
* config/tc-msp430.c (struct rcodes_s, MSP430_RLC, msp430_rcodes,
struct hcodes_s, msp430_hcodes): From include/opcode/msp430.h.
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* i386.h (i386_optab): Put back "movzb".
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* opcode/crx.h (enum argtype): Rename types, remove unused types.
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comments. Remove member cris_ver_sim. Add members
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
(struct cris_support_reg, struct cris_cond15): New types.
(cris_conds15): Declare.
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
SIZE_FIELD_UNSIGNED.
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2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
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(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
(enum operand_type): Rearrange operands, edit comments.
replace us<N> with ui<N> for unsigned immediate.
replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped displacements (respectively).
replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
(instruction type): Add NO_TYPE_INS.
(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
(operand_entry): New field - 'flags'.
(operand flags): New.
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* opcode/crx.h (operand_type): Remove redundant types i3, i4, i5, i8, i12.
Add new unsigned immediate types us3, us4, us5, us16.
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atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
* include/opcode/avr.h: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
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* ppc-opc.c (L): Make this field not optional.
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
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* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
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doesn't support it.
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