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2017-01-02Update year range in copyright notice of all files.Alan Modra70-70/+70
2016-12-31PRU BFD supportDimitar Dimitrov1-0/+411
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-2/+8
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-5/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+4
2016-12-21Remove high bit set charactersAlan Modra1-8/+8
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+8
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-3/+3
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-2/+1
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki1-1/+1
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki1-0/+1
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+4
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-0/+5
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi1-0/+4
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-0/+17
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+5
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+2
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-14/+7
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+4
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+1
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-28/+7
2016-11-03opcodes/arc: Make some macros 64-bit safeGraham Markall1-26/+28
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-4/+3
2016-11-01Add support for RISC-V architecture.Nick Clifton2-0/+1502
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-0/+1
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-0/+4
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu1-1/+3
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+39
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-1/+3
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+3
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-1/+3
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw1-0/+2
2016-08-26Fixes to legacy ARC relocations.Cupertino Miranda1-0/+15
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner1-0/+3
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-59/+135
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-4/+7
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab1-1/+1
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders1-2/+1
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-3/+3
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