riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-05	MIPS: add MT ASE support for micromips32	YunQiang Su	1	-10/+25
2023-06-01	RISC-V: PR30449, Add lga assembler macro support.	Jim Wilson	1	-0/+1
2023-05-30	LoongArch: include: Add support for linker relaxation.	mengqinggang	1	-0/+3
2023-04-26	RISC-V: Support XVentanaCondOps extension	Philipp Tomsich	2	-0/+9
2023-03-30	aarch64: Remove stray reglist variable	Richard Sandiford	1	-1/+1
2023-03-30	aarch64: Add the RPRFM instruction	Richard Sandiford	1	-0/+2
2023-03-30	aarch64: Add new SVE dot-product instructions	Richard Sandiford	1	-1/+2
2023-03-30	aarch64: Add the SME2 shift instructions	Richard Sandiford	1	-0/+3
2023-03-30	aarch64: Add the SME2 saturating conversion instructions	Richard Sandiford	1	-0/+1
2023-03-30	aarch64: Add the SME2 MLALL and MLSLL instructions	Richard Sandiford	1	-0/+5
2023-03-30	aarch64: Add the SME2 MLAL and MLSL instructions	Richard Sandiford	1	-0/+4
2023-03-30	aarch64: Add the SME2 FMLA and FMLS instructions	Richard Sandiford	1	-0/+2
2023-03-30	aarch64: Add the SME2 maximum/minimum instructions	Richard Sandiford	1	-0/+1
2023-03-30	aarch64: Add the SME2 ADD and SUB instructions	Richard Sandiford	1	-0/+3
2023-03-30	aarch64: Add the SME2 ZT0 instructions	Richard Sandiford	1	-0/+11
2023-03-30	aarch64: Add the SME2 predicate-related instructions	Richard Sandiford	1	-0/+11
2023-03-30	aarch64: Add the SME2 multivector LD1 and ST1 instructions	Richard Sandiford	1	-0/+3
2023-03-30	aarch64: Add the SME2 MOVA instructions	Richard Sandiford	1	-0/+10
2023-03-30	aarch64: Add support for predicate-as-counter registers	Richard Sandiford	1	-0/+5
2023-03-30	aarch64; Add support for vector offset ranges	Richard Sandiford	1	-4/+19
2023-03-30	aarch64: Add support for vgx2 and vgx4	Richard Sandiford	1	-0/+13
2023-03-30	aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array	Richard Sandiford	1	-3/+3
2023-03-30	aarch64: Add +sme2	Richard Sandiford	1	-0/+1
2023-03-30	aarch64: Add support for strided register lists	Richard Sandiford	1	-12/+26
2023-03-30	aarch64: Add a aarch64_cpu_supports_inst_p helper	Richard Sandiford	1	-0/+3
2023-03-30	aarch64: Add an operand class for SVE register lists	Richard Sandiford	1	-0/+1
2023-03-30	aarch64: Add an error code for out-of-range registers	Richard Sandiford	1	-1/+9
2023-03-30	aarch64: Deprioritise AARCH64_OPDE_REG_LIST	Richard Sandiford	1	-5/+9
2023-03-30	aarch64: Update operand_mismatch_kind_names	Richard Sandiford	1	-1/+4
2023-03-30	aarch64: Move ZA range checks to aarch64-opc.c	Richard Sandiford	1	-0/+1
2023-03-30	aarch64: Make indexed_za use 64-bit immediates	Richard Sandiford	1	-1/+1
2023-03-30	aarch64: Rename za_tile_vector to za_index	Richard Sandiford	1	-10/+13
2023-03-30	aarch64: Make SME instructions use F_STRICT	Richard Sandiford	1	-0/+2
2023-03-30	aarch64: Add sme-i16i64 and sme-f64f64 aliases	Richard Sandiford	1	-2/+2
2023-02-03	bpf: fix error conversion from long unsigned int to unsigned int [-Werror=ove...	Guillermo E. Martinez	1	-1/+1
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra	70	-70/+70
2022-12-27	RISC-V: Fix T-Head Fmv vendor extension encoding	Christoph Müllner	1	-2/+2
2022-11-25	riscv: Add AIA extension support (Smaia, Ssaia)	Christoph Müllner	1	-0/+68
2022-11-19	RISC-V: Add 'Ssstateen' extension and its CSRs	Tsukasa OI	1	-13/+13
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner	2	-0/+9
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner	2	-0/+9
2022-11-14	aarch64: Add support for Common Short Sequence Compression extension	Andre Vieira	1	-1/+5
2022-10-27	PowerPC: Add support for RFC02653 - Dense Math Facility	Peter Bergner	1	-15/+18
2022-10-14	e200 LSP support	Alan Modra	1	-0/+5
2022-10-14	RISC-V: Move certain arrays to riscv-opc.c	Tsukasa OI	1	-11/+2
2022-10-04	RISC-V: Fix buffer overflow on print_insn_riscv	Tsukasa OI	1	-0/+2
2022-10-04	RISC-V: Renamed INSN_CLASS for floating point in integer extensions.	Nelson Chu	1	-7/+7
2022-10-04	RISC-V/gas: allow generating up to 176-bit instructions with .insn	Jan Beulich	1	-0/+3
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	2	-0/+9
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	2	-0/+18