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AgeCommit message (Expand)AuthorFilesLines
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman1-0/+40
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+226
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-37/+43
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-6/+8
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-2/+1
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig1-0/+1
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+6
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-1/+3
2017-02-24Add new counter-enable CSRsAndrew Waterman1-0/+4
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-1/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-1/+9
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+3
2017-02-14PowerPC register expression checksAlan Modra1-70/+78
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-1/+23
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov6-6/+6
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-1/+3
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+104
2017-01-02Update year range in copyright notice of all files.Alan Modra70-70/+70
2016-12-31PRU BFD supportDimitar Dimitrov1-0/+411
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-2/+8
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-5/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+4
2016-12-21Remove high bit set charactersAlan Modra1-8/+8
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+8
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-3/+3
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-2/+1
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki1-1/+1
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki1-0/+1
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+4
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-0/+5
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi1-0/+4
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-0/+17
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+5
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+2
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-14/+7
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+4
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+1
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-28/+7
2016-11-03opcodes/arc: Make some macros 64-bit safeGraham Markall1-26/+28
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-4/+3
2016-11-01Add support for RISC-V architecture.Nick Clifton2-0/+1502
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-0/+1
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-0/+4
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu1-1/+3
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+4
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