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2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+2
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+3
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw1-5/+3
Remove the patterns to match Maverick co-processor instructions from the disassembly tables. This required fixing a couple of tests in the assembler testsuite where we, probably incorrectly, disassembled generic co-processor instructions as a Maverick instruction (it particularly made no sense to do this for Armv6t2 in Thumb state).
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-1/+2
* https://github.com/riscv/riscv-b/tags Added standard B extension back, which implies Zba, Zbb and Zbs extensions. * https://github.com/riscv/riscv-zaamo-zalrsc/tags Splited standard A extension into two new extensions, Zaamo and Zalrsc. The A extension implies Zaamo and Zalrsc extensions. Not sure if we need to do the similar check as i and zicsr/zifencei. Passed riscv[32|64]-[elf/linux] binutils testcases. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for A and B extensions. The A implies Zaamo and Zalrsc, the B implies Zba, Zbb and Zbs. (riscv_supported_std_ext): Supported B extension with v1.0. (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated. include/ * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC. opcodes/ * riscv-opc.c (riscv_opcodes): Splited standard A extension into two new extensions, Zaamo and Zalrsc. gas/ * testsuite/gas/riscv/march-imply-a.d: New testcase. * testsuite/gas/riscv/march-imply-b.d: New testcase. * testsuite/gas/riscv/attribute-01.d: Updated. * testsuite/gas/riscv/attribute-02.d: Updated. * testsuite/gas/riscv/attribute-03.d: Updated. * testsuite/gas/riscv/attribute-04.d: Updated. * testsuite/gas/riscv/attribute-05.d: Updated. * testsuite/gas/riscv/attribute-10.d: Updated. * testsuite/gas/riscv/mapping-symbols.d: Updated. * testsuite/gas/riscv/march-imply-g.d: Updated. * testsuite/gas/riscv/march-imply-unsupported.d: Updated. * testsuite/gas/riscv/march-ok-reorder.d: Updated. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang1-0/+1
Ignore .align at the start of a section may result in misalignment when partial linking. Manually add -mignore-start-align option without partial linking. Gcc -falign-functions add .align 5 to the start of a section, it causes some error message mismatch. Set these testcases to xfail on LoongArch target.
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-0/+3
Given that the disassembler should never abort when decoding (potentially random) data, assertion statements in the `get_*reg_qualifier_from_value' function family prove problematic. Consider the random 32-bit word W, encoded in a data segment and encountered on execution of `objdump -D <obj_name>'. If: (W & ~opcode_mask) == valid instruction Then before `print_insn_aarch64_word' has a chance to report the instruction as potentially undefined, an attempt will be made to have the qualifiers for the instruction's register operands (if any) decoded. If the relevant bits do not map onto a valid qualifier for the matched instruction-like word, an abort will be triggered and the execution of objdump aborted. As this scenario is perfectly feasible and, in light of the fact that objdump must successfully decode all sections of a given object file, it is not appropriate to assert in this family of functions. Therefore, we add a new pseudo-qualifier `AARCH64_OPND_QLF_ERR' for handling invalid qualifier-associated values and re-purpose the assertion conditions in qualifier-retrieving functions to be the predicate guarding the returning of the calculated qualifier type. If the predicate fails, we return this new qualifier and allow the caller to handle the error as appropriate. As these functions are called either from within `aarch64_extract_operand' or `do_special_decoding', both of which are expected to return non-zero values, it suffices that callers return zero upon encountering `AARCH64_OPND_QLF_ERR'. Ar present the error presented in the hypothetical scenario has been encountered in `get_sreg_qualifier_from_value', but the change is made to the whole family to keep the interface consistent. Bug: https://sourceware.org/PR31595
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei2-0/+32
Support zcmp extension push/pop/popret and popret zero instructions. The `reg_list' is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}" to present this feature. Passed gcc/binutils regressions of riscv-gnu-toolchain. Most of work was finished by Sinan Lin. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp. (riscv_supported_std_z_ext): Added zcmp with version 1.0. (riscv_parse_check_conflicts): Zcmp conflicts with d/zcd. (riscv_multi_subset_supports): Handle zcmp. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (regno_to_reg_list): New function, used to map register to reg_list number. (reglist_lookup): Called reglist_lookup_internal. Return false if reg_list number is zero, which is an invalid value. (reglist_lookup_internal): Parse register list, and return the last register by regno_to_reg_list. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp. (MATCH/MASK_CM_POP): Ditto. (MATCH/MASK_CM_POPRET): Ditto. (MATCH/MASK_CM_POPRETZ): Ditto. (DECLARE_INSN): New declarations for zcmp. * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm operand for zcmp. (OP_MASK_REG_LIST): Handle operand for zcmp register list. (OP_SH_REG_LIST): Ditto. (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base. (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers. (enum riscv_insn_class): Added INSN_CLASS_ZCMP. (extern riscv_get_sp_base): Added. opcodes/ChangeLog: * riscv-dis.c (print_reg_list): New function, used to get zcmp reg_list field. (riscv_get_spimm): New function, used to get zcmp sp adjustment immediate. (print_insn_args): Handle new operands for zcmp. * riscv-opc.c (riscv_get_sp_base): New function, used by gas and objdump. Get sp base adjustment. (riscv_opcodes): Added zcmp instructions.
2024-03-28RISC-V: Removed privileged spec 1.9.1 support in assembler.Nelson Chu1-204/+185
Removed since it's may have lots of conflicts with the newer extensions, but still keep linker recognizes it in case of linking old objects. gas/ * NEWS: Updated. * config/tc-riscv.c (riscv_set_default_priv_spec): Regard 1.9.1 as an unknown version. (md_show_usage): Removed privileged spec 1.9.1 information. * testsuite/gas/riscv/attribute-05.s: Updated since privileged spec 1.9.1 is unsupported. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-12.d: Likewise. * testsuite/gas/riscv/attribute-13.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Removed. * testsuite/gas/riscv/csr-version-1p9p1.l: Removed. include/ * opcode/riscv-opc.h: Updated since privileged spec 1.9.1 is unsupported. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d: Updated since privileged spec 1.9.1 is unsupported. * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha1-0/+2
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev1-0/+3
The following instructions are added in this patch: - ADDPT and SUBPT - Add/Subtract checked pointer - MADDPT and MSUBPT - Multiply Add/Subtract checked pointer These instructions are part of Checked Pointer Arithmetic extension. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. A new flag "+cpa" added to documentation. This flag enables CPA extension. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-08RISC-V: Support Zabha extension.Jiawei2-0/+55
The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-03-01s390: Warn when register name type does not match operandJens Remus1-0/+3
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their ↵Matthieu Longo1-2/+2
naming for coherency Hi, Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion. Regression tested on aarch64-none-elf, and no regression found. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu. From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001 From: Matthieu Longo <matthieu.longo@arm.com> Date: Fri, 23 Feb 2024 11:30:40 +0000 Subject: [PATCH] aarch64: rename internals related to PAuth feature to use pauth in their naming for coherency Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.
2024-02-20kvx: gas: rename: or -> ior, xor -> eorPaul Iannetta1-1382/+1431
TCA instructions start with an X, this introduces ambiguities when it comes to XOR (Is it the OR on the TCA or the XOR of the core?). For this reason, we rename OR to IOR and XOR to EOR. OR and XOR variants are still valid on KV3-1 and KV3-2. However, they have been completely removed from KV4-1. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: move the splat modifier to the immediatePaul Iannetta1-1915/+1864
The position of the splat modifier is now after the operand it modifies and not attached directly to the opcode. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-19arm: Add support for Armv9.5-AClaudio Bantaloukas1-0/+1
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov1-0/+1
DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi1-2/+2
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang1-0/+1
In LoongArch ABI, r22 register can be used as frame pointer or static register(s9). Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers
2024-01-23aarch64: Include +predres2 in -march=armv8.9-aAndrew Carlotti1-2/+2
This matches the dependencies in the architecture, in LLVM, and even in the original Binutils commit message that mistakenly included it only in armv9.4-a.
2024-01-15aarch64: rcpc3: Add integer load/store insnsVictor Do Nascimento1-0/+1
Along with the relevant unit tests and updates to the existing regression tests, this adds support for the following novel rcpc3 insns: LDIAPP <Wt1>, <Wt2>, [<Xn|SP>] LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8 LDIAPP <Xt1>, <Xt2>, [<Xn|SP>] LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16 STILP <Wt1>, <Wt2>, [<Xn|SP>] STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]! STILP <Xt1>, <Xt2>, [<Xn|SP>] STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]! LDAPR <Wt>, [<Xn|SP>], #4 LDAPR <Xt>, [<Xn|SP>], #8 STLR <Wt>, [<Xn|SP>, #-4]! STLR <Xt>, [<Xn|SP>, #-8]!
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+5
The particular choices of address indexing, along with their encoding for RCPC3 instructions lead to the requirement of a new set of operand descriptions, along with the relevant inserter/extractor set. That is, for the integer load/stores, there is only a single valid indexing offset quantity and offset mode is allowed - The value is always equivalent to the amount of data read/stored by the operation and the offset is post-indexed for Load-Acquire RCpc, and pre-indexed with writeback for Store-Release insns. This indexing quantity/mode pair is selected by the setting of a single bit in the instruction. To represent these insns, we add the following operand types: - AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND - AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB In the case of loads and stores involving SIMD/FP registers, the optional offset is encoded as an 8-bit signed immediate, but neither post-indexing or pre-indexing with writeback is available. This created the need for an operand type similar to AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should not be checked. We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-2/+4
Beyond the need to encode any registers involved in data transfer and the address base register for load/stores, it is necessary to specify the data register addressing mode and whether the address register is to be pre/post-indexed, whereby loads may be post-indexed and stores pre-indexed with write-back. The use of a single bit to specify both the indexing mode and indexing value requires a novel function be written to accommodate this for address operand insertion in assembly and another for extraction in disassembly, along with the definition of two insn fields for use with these instructions. This therefore defines the following functions: - aarch64_ins_rcpc3_addr_opt_offset - aarch64_ins_rcpc3_addr_offset - aarch64_ext_rcpc3_addr_opt_offset - aarch64_ext_rcpc3_addr_offset It extends the `do_special_{encoding|decoding}' functions and defines two rcpc3 instruction fields: - FLD_opc2 - FLD_rcpc3_size
2024-01-15aarch64: rcpc3: Create implicit load/store size calc functionVictor Do Nascimento1-0/+3
The allowed immediate offsets in integer rcpc3 load store instructions are not encoded explicitly in the instruction itself, being rather implicitly equivalent to the amount of data loaded/stored by the instruction. This leads to the requirement that this quantity be calculated based on the number of registers involved in the transfer, either as data source or destination registers and their respective qualifiers. This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)' implemented here, using a cumulative sum of qualifier sizes preceding the address operand in the OPNDS operand list argument.
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+2
Indicating the presence of the Armv8.2-a feature adding further support for the Release Consistency Model, the `+rcpc3' architectural extension flag is added to the list of possible `-march' options in Binutils, together with the necessary macro for encoding rcpc3 instructions.
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-1/+5
Add an aarch64_feature_set field to aarch64_sys_ins_reg, and use this for feature checks instead of testing against a list of operand codes.
2024-01-15aarch64: Remove unused BTI feature bitAndrew Carlotti1-3/+0
OK for master?
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+3
Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-1/+4
Hi, This patch add support for SVE2.1 instruction dupq, eorqv and extq. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-2/+8
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+11
Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni1-0/+2
Hi, This patch add support for SVE2.1 and SME2.1 non-widening BFloat16 (FEAT_B16B16) instructions. Following instructions predicated, unpredicated and indexed variants are added in this patch. bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm, bfmla,bfmls,bfmul and bfsub. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-0/+3
Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of "+d128". This is an incremental improvement; there are still some FEAT_XS tlbi variants that are gated incorrectly or missing entirely.
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-0/+3
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+4
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha1-0/+15
This patch adds support for the new AArch64 system registers that are part of the following extensions: * FEAT_DEBUGv8p9 * FEAT_PMUv3p9 * FEAT_PMUv3_SS * FEAT_PMUv3_ICNTR * FEAT_SEBEP
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni1-0/+1
This patch adds support for FEAT_THE doubleword and quadword instructions. doubleword insturctions are enabled by "+the" flag whereas quadword instructions are enabled on passing both "+the and +d128" flags. Support for following sets of instructions is added in this patch. Read check write compare and swap doubleword: (rcwcas, rcwcasa, rcwcasal, rcwcasl) Read check write compare and swap quadword: (rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl) Read check write software compare and swap doubleword: (rcwscas, rcwscasa, rcwscasal, rcwscasl) Read check write software compare and swap quadword: (rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl) Read check write atomic bit clear on doubleword: (rcwclr, rcwclra, rcwclral, rcwclrl) Read check write atomic bit clear on quadword: (rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl) Read check write software atomic bit clear on doubleword: (rcwsclr, rcwsclra, rcwsclral, rcwsclrl) Read check write software atomic bit clear on quadword: (rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl) Read check write atomic bit set on doubleword: (rcwset,rcwseta, rcwsetal,rcwsetl) Read check write atomic bit set on quadword: (rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl) Read check write software atomic bit set on doubleword: (rcwsset,rcwsseta,rcwssetal,rcwssetl) Read check write software atomic bit set on quadword: (rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl) Read check write swap doubleword: (rcwswp,rcwswpa,rcwswpal,rcwswpl) Read check write swap quadword: (rcwswpp,rcwswppa, rcwswppal,rcwswppl) Read check write software swap doubleword: (rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl) Read check write software swap quadword: (rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-0/+2
With the addition of 128-bit system registers to the Arm architecture starting with Armv9.4-a, a mechanism for manipulating their contents is introduced with the `msrr' and `mrrs' instruction pair. These move values from one such 128-bit system register into a pair of contiguous general-purpose registers and vice-versa, as for example: msrr ttlb0_el1, x0, x1 mrrs x0, x1, ttlb0_el1 This patch adds the necessary support for these instructions, adding checks for system-register width by defining a new operand type in the form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p' predicate, responsible for checking whether the requested system register table entry is marked as implemented in the 128-bit mode via the F_REG_128 flag.
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+1
The addition of 128-bit page table descriptors and, with it, the addition of 128-bit system registers for these means that special "invalidate translation table entry" instructions are needed to cope with the new 128-bit model. This is introduced with the `tlbpi' instruction, implemented here.
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+6
While CRn and CRm fields in the SYSP instruction are 4-bit wide and are thus able to accommodate values in the range 0-15, the specifications for the SYSP instructions limit their ranges to 8-9 for CRm and 0-7 in the case of CRn. This led to the need to signal in some way to the operand parser that a given operand is under special restrictions regarding its use. This is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the range of operand values for fields in the instruction tagged with the flag. The flag is then used in `parse_operands' when the instruction is assembled, but needs not be taken into consideration during disassembly.
2024-01-09aarch64: Add support for optional operand pairsVictor Do Nascimento1-1/+11
Two of the instructions added by the `+d128' architectural extension add the flexibility to have two optional operands. Prior to the addition of the `tlbip' and `sysp' instructions, no mnemonic allowed more than one such optional operand. With `tlbip' as an example, some TLBIP instruction names do not allow for any optional operands, while others allow for both to be optional. In the latter case, it is possible that either the second operand alone is omitted or both operands are omitted. Therefore, a considerable degree of flexibility needed to be added to the way operands were parsed. It was, however, possible to achieve this with relatively few changes to existing code. it is noteworthy that opcode flags specifying the optional operand number are non-orthogonal. For example, we have: #define F_OPD1_OPT (2 << 12) : 0b10 << 12 #define F_OPD2_OPT (3 << 12) : 0b11 << 12 such that by virtue of the observation that (F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT it is impossible to mark both operands 1 and 2 as optional for an instruction and it is assumed that a maximum of 1 operand can ever be optional. This is not overly-problematic given that, for optional pairs, the second optional operand is always found immediately after the first. Thus, it suffices for us to flag that there is a second optional operand. With this fact, we can infer its position in the mnemonic from the position of the first (e.g. if the second operand in the mnemonic is optional, we know the third is too). We therefore define the `F_OPD_PAIR_OPT' flag and calculate its position in the mnemonic from the value encoded by the `F_OPD<n>_OPT' flag. Another observation is that there is a tight coupling between default values assigned to the two registers when one (or both) are omitted from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero register is specified), Xt2 defaults to the same value, otherwise Xt2 will be assigned Xt + 1. This meant that where you have default value validation, in checking the second optional operand's value, it is also necessary to look at the value assigned to the previously-processed operand value before deciding its validity. Thus `process_omitted_operand' needs not only access to its `operand' argument, but also to the global `inst' struct.
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento1-0/+1
Analysis of the allowed operand values for `sysp' and `tlbip' reveals a significant departure from the allowed behavior for operand register pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other insns in this category. For instructions `casp', `mrrs' and `msrr' the register pair must always start at an even index and the second register in the pair is the index + 1. This precludes the use of xzr as the first register, given it corresponds to register number 31. This is different in the case of `sysp' and `tlbip', however. These allow the use of xzr and, where the first operand in the pair is omitted, this is the default value assigned to it. When this operand is assigned xzr, it is expected that the second operand will likewise take on a value of xzr. These two instructions therefore "break" two rules of register pairs: * The first of the two registers is odd-numbered. * The index of the second register is equal to that of the first, and not n+1. To allow for this departure from hitherto standard behavior, we extend the functionality of the assembler by defining an extension of the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR. It is used in defining `sysp' and `tlbip' and allows `operand_general_constraint_met_p' to allow the pair to both take on the value of xzr.
2024-01-09aarch64: Expand maximum number of operands from 5 to 6Victor Do Nascimento1-1/+1
Given the introduction of the new Armv9.4-a `sysp' insn using the following syntax: sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} and by extension the need to encode 6 assembly operands, extend Binutils to handle instructions taking 6 operands, up from a previous maximum of 5.
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+3
Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions.
2024-01-08arm: Add support for Armv8.9-A and Armv9.4-Asrinath1-0/+2
This patch adds AArch32 support for -march=armv8.9-a and -march=armv9.4-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_4A and ARM_ARCH_V8_9A are technically redundant but it including them for macro code consistency across architectures.
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma1-0/+11
Since the particularity of "th.vsetvli" was not taken into account in the initial support patches for XTheadVector, the program operation failed due to instruction coding errors. According to T-Head SPEC ([1]), the "vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV, which is quite different from the "V" extension. Therefore, we cannot simply reuse the processing of vsetvl in V extension. We have set up tens of thousands of test cases to ensure that no further encoding issues are there, and and execute all compiled test files on real HW and make sure they don't trigger SIGILL. Ref: [1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add handling for th.vsetvli. (my_getThVsetvliExpression): New function. (riscv_ip): Likewise. * testsuite/gas/riscv/x-thead-vector.d: Likewise. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro. (OP_SH_XTHEADVLMUL): Likewise. (OP_MASK_XTHEADVSEW): Likewise. (OP_SH_XTHEADVSEW): Likewise. (OP_MASK_XTHEADVEDIV): Likewise. (OP_SH_XTHEADVEDIV): Likewise. (OP_MASK_XTHEADVTYPE_RES): Likewise. (OP_SH_XTHEADVTYPE_RES): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Likewise. * riscv-opc.c: Likewise.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra72-72/+72
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-0/+4
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-25LoongArch: Add tls transition support.Lulu Cai1-0/+6
Transitions between DESC->IE/LE and IE->LE are supported now. 1. For DESC -> LE: pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 2. For DESC -> IE: pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 3. For IE -> LE: pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) add.d $a0,$a0,$tp 4. When a tls variable is accessed using both DESC and IE, DESC transitions to IE and uses the same GOT entry as IE.
generated by cgit v1.1 at 2024-10-19 13:22:58 +0000