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AgeCommit message (Expand)AuthorFilesLines
2023-01-01Update year range in copyright notice of binutils filesAlan Modra70-70/+70
2022-12-27RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner1-2/+2
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner1-0/+68
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI1-13/+13
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner2-0/+9
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2-0/+9
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-1/+5
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner1-15/+18
2022-10-14e200 LSP supportAlan Modra1-0/+5
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-11/+2
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-0/+2
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-7/+7
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich1-0/+3
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner2-0/+9
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2-0/+18
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2-0/+135
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2-0/+27
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2-0/+21
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2-0/+9
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2-0/+42
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+17
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2-0/+18
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2-0/+66
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner1-0/+3
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-0/+1
2022-08-11ppc/svp64: introduce non-zero operand flagDmitry Selyutin1-0/+5
2022-08-11ppc/svp64: support LibreSOC architectureDmitry Selyutin1-0/+3
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-1/+27
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-3/+4
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+1
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+10
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+62
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+42
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2-25/+26
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-2/+3
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra2-32/+32
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-1/+7
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-6/+0
2022-05-18AArch64: Enable FP16 by default for Armv9-A.Tamar Christina1-0/+1
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2-0/+77
2022-04-22RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner1-0/+9
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-2/+2
2022-03-18RISC-V: Cache management instructionsTsukasa OI2-0/+11
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+8
2022-03-16Delete PowerPC macro insn supportAlan Modra1-26/+0
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-3/+5
2022-02-23RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu1-34/+49
2022-02-23RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI1-0/+138
2022-01-02Update year range in copyright notice of binutils filesAlan Modra70-70/+70
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+100