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AgeCommit message (Expand)AuthorFilesLines
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay1-0/+5
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-0/+3
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+2
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-1/+4
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-5/+16
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme1-1/+6
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme1-5/+7
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme1-0/+1
2017-05-30S/390: Improve error checking for optional operandsAndreas Krebbel1-3/+4
2017-05-30S/390: Remove optional operand flag.Andreas Krebbel1-10/+6
2017-05-23[ARC] Update MAX_INSN_FLGS.claziss1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+1
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-2/+23
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-5/+34
2017-05-14Fix match and mask for 64-bit bb opcode.John David Anglin1-1/+1
2017-05-10[ARC] Object attributes.Claudiu Zissulescu2-62/+98
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra1-43/+46
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra1-5/+0
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra1-3/+0
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra1-3/+0
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman1-0/+40
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+226
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-37/+43
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-6/+8
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-2/+1
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig1-0/+1
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+6
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-1/+3
2017-02-24Add new counter-enable CSRsAndrew Waterman1-0/+4
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-1/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-1/+9
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+3
2017-02-14PowerPC register expression checksAlan Modra1-70/+78
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-1/+23
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov6-6/+6
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-1/+3
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+104
2017-01-02Update year range in copyright notice of all files.Alan Modra70-70/+70
2016-12-31PRU BFD supportDimitar Dimitrov1-0/+411
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-2/+8
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-5/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+4
2016-12-21Remove high bit set charactersAlan Modra1-8/+8
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+8
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-3/+3
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-2/+1
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki1-1/+1
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki1-0/+1
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+4
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-0/+5
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