riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-11-25	riscv: Add AIA extension support (Smaia, Ssaia)	Christoph Müllner	1	-0/+68
2022-11-19	RISC-V: Add 'Ssstateen' extension and its CSRs	Tsukasa OI	1	-13/+13
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner	1	-0/+8
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner	1	-0/+8
2022-09-23	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	1	-0/+8
2022-09-22	RISC-V: Add T-Head MemPair vendor extension	Christoph Müllner	1	-0/+17
2022-09-22	RISC-V: Add T-Head MemIdx vendor extension	Christoph Müllner	1	-0/+134
2022-09-22	RISC-V: Add T-Head FMemIdx vendor extension	Christoph Müllner	1	-0/+26
2022-09-22	RISC-V: Add T-Head MAC vendor extension	Christoph Müllner	1	-0/+20
2022-09-22	RISC-V: Add T-Head CondMov vendor extension	Christoph Müllner	1	-0/+8
2022-09-22	RISC-V: Add T-Head Bitmanip vendor extension	Christoph Müllner	1	-0/+39
2022-09-22	RISC-V: Add T-Head SYNC vendor extension	Christoph Müllner	1	-0/+17
2022-09-22	RISC-V: Add T-Head CMO vendor extension	Christoph Müllner	1	-0/+65
2022-06-28	RISC-V: Add 'Sstc' extension and its CSRs	Tsukasa OI	1	-0/+10
2022-06-28	RISC-V: Add 'Sscofpmf' extension with its CSRs	Tsukasa OI	1	-0/+62
2022-06-28	RISC-V: Add 'Smstateen' extension and its CSRs	Tsukasa OI	1	-0/+42
2022-06-22	RISC-V: Use single h extension to control hypervisor CSRs and instructions.	Nelson Chu	1	-25/+25
2022-05-20	RISC-V: Remove RV128-only fmv instructions	Tsukasa OI	1	-6/+0
2022-05-17	RISC-V: Added half-precision floating-point v1.0 instructions.	Nelson Chu	1	-0/+72
2022-04-22	RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}	Christoph Muellner	1	-0/+9
2022-03-18	RISC-V: Cache management instructions	Tsukasa OI	1	-0/+9
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI	1	-0/+7
2022-02-23	RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.	Nelson Chu	1	-34/+49
2022-02-23	RISC-V: Add Privileged Architecture 1.12 CSRs	Tsukasa OI	1	-0/+138
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2021-12-24	RISC-V: Hypervisor ext: support Privileged Spec 1.12	Vineet Gupta	1	-0/+100
2021-12-24	RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests	Vineet Gupta	1	-20/+0
2021-12-16	RISC-V: Support svinval extension with frozen version 1.0.	Nelson Chu	1	-0/+16
2021-11-17	RISC-V: Support rvv extension with released version 1.0.	Nelson Chu	1	-0/+1296
2021-11-16	RISC-V: Scalar crypto instructions and operand set.	jiawei	1	-0/+75
2021-10-07	RISC-V: Add support for Zbs instructions	Philipp Tomsich	1	-0/+24
2021-03-16	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	Kuan-Lin Chen	1	-0/+104
2021-02-05	RISC-V: PR27348, Remove obsolete Xcustom support.	Nelson Chu	1	-72/+0
2021-02-04	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.	Nelson Chu	1	-108/+0
2021-01-15	RISC-V: Comments tidy and improvement.	Nelson Chu	1	-8/+8
2021-01-07	RISC-V: Add pause hint instruction.	Philipp Tomsich	1	-0/+3
2021-01-07	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).	Claire Xenia Wolf	1	-0/+108
2021-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2020-06-30	RISC-V: Support debug and float CSR as the unprivileged ones.	Nelson Chu	1	-24/+42
2020-06-30	RISC-V: Cleanup the include/opcode/riscv-opc.h.	Nelson Chu	1	-33/+26
2020-06-12	RISC-V: Drop the privileged spec v1.9 support.	Nelson Chu	1	-218/+217
2020-05-20	[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...	Nelson Chu	1	-261/+248
2020-03-30	RISC-V: Update CSR to privileged spec 1.11.	Nelson Chu	1	-6/+19
2020-02-20	RISC-V: Support the ISA-dependent CSR checking.	Nelson Chu	1	-244/+244
2018-10-02	RISC-V: Add fence.tso instruction	Palmer Dabbelt	1	-0/+2
2018-05-08	RISC-V: Add missing hint instructions from RV128I.	Jim Wilson	1	-0/+6
2018-01-04	RISC-V: Add 2 missing privileged registers.	Jim Wilson	1	-4/+8
2017-12-28	RISC-V: Add missing privileged spec registers.	Jim Wilson	1	-148/+208
2017-11-07	RISC-V: Add satp as an alias for sptbr	Palmer Dabbelt	1	-2/+5
2017-03-31	RISC-V: Add physical memory protection CSRs	Andrew Waterman	1	-0/+40