| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+2 |
| 2018-05-08 | RISC-V: Add missing hint instructions from RV128I. | Jim Wilson | 1 | -0/+6 |
| 2018-01-04 | RISC-V: Add 2 missing privileged registers. | Jim Wilson | 1 | -4/+8 |
| 2017-12-28 | RISC-V: Add missing privileged spec registers. | Jim Wilson | 1 | -148/+208 |
| 2017-11-07 | RISC-V: Add satp as an alias for sptbr | Palmer Dabbelt | 1 | -2/+5 |
| 2017-03-31 | RISC-V: Add physical memory protection CSRs | Andrew Waterman | 1 | -0/+40 |
| 2017-02-24 | Add new counter-enable CSRs | Andrew Waterman | 1 | -0/+4 |
| 2017-02-15 | Add SFENCE.VMA instruction | Andrew Waterman | 1 | -0/+3 |
| 2017-01-03 | Add support for the Q extension to the RISCV ISA. | Kito Cheng | 1 | -0/+102 |
| 2016-11-01 | Add support for RISC-V architecture. | Nick Clifton | 1 | -0/+1160 |
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index : riscv-gnu-toolchain/gdb.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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