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Some gdbserver targets generate their target description based on the
gdb/regformats/*.dat files. These .dat files are generated from a
matching xml file in gdb/features/.
Lets consider a concrete example:
Take gdb/features/or1k-linux.xml, this file is processed by
gdb/features/Makefile to create gdb/regformats/or1k-linux.dat.
When gdbserver is built for the or1k target the file
or1k-linux-generated.cc is generated using the
gdb/regformats/regdat.sh script. This .cc file is then compiled and
linked into gdbserver.
The or1k-linux-generated.cc file contains the function
init_registers_or1k_linux which is called from within gdbserver, this
function creates a target_desc object and sets its xmltarget field to
a fixed string. This fixed string is the xml filename that was
originally used to generate the xml file, in this case or1k-linux.xml.
Additionally, as part of the gdbserver build the file or1k-linux.xml
is converted to a string and placed in the file
xml-builtin-generated.cc which is then built into gdbserver.
Now when GDB asks gdbserver for the target description, gdbserver
returns the fixed xmltarget string, which is the name of an xml file.
GDB will then ask gdbserver for that file and gdbserver will return
the contents of that file thanks to the xml-builtin-generated.cc
file's contents.
This is all rather complicated, but it does work. So what's the
problem that I'm fixing?
Well or1k-linux.xml does contain the osabi information, so this will
be returned from gdbserver to GDB. That's good.
However, the target_desc object created in init_registers_or1k_linux
will not have its osabi set correctly.
Now this doesn't really matter too much except
init_registers_or1k_linux includes a call to init_target_desc.
In the next commit I want to extend init_target_desc to require an
osabi to be passed in. The motivation for this will be explained in
the next commit, but if we accept for a moment that this is something
that should be done, then the question is what osabi should we use in
init_registers_or1k_linux?
Ideally we'd use the osabi which is set in or1k-linux.xml. If we do
that then everything will remain consistent, which is a good thing.
And so, to get the osabi from or1k-linux.xml into
init_registers_or1k_linux, we first need to get the osabi information
into or1k-linux.dat file, and this is what this commit does.
I've added a new xsl script print-osabi.xsl and updated
gdb/features/Makefile to make use of this script. Then I regenerated
all of the .dat files. Now every .dat file contains either:
osabi:GNU/Linux
osabi:unknown
The first is for xml files containing <osabi>GNU/Linux</osabi> and the
second is for xml files that don't contain an osabi element.
This commit doesn't attempt to make use of the osabi information in
the .dat files, that will come in the next commit. There should be no
user visible changes after this commit.
Approved-By: Kevin Buettner <kevinb@redhat.com>
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GDB deprecated the commands "show/set mpx bound" in GDB 15.1, as Intel
listed Intel(R) Memory Protection Extensions (MPX) as removed in 2019.
MPX is also deprecated in gcc (since v9.1), the linux kernel (since v5.6)
and glibc (since v2.35). Let's now remove MPX support in GDB completely.
This includes the removal of:
- MPX functionality including register support
- deprecated mpx commands
- i386 and amd64 implementation of the hooks report_signal_info and
get_siginfo_type
- tests
- and pretty printer.
We keep MPX register numbers to not break compatibility with old gdbservers.
Approved-By: Felix Willgerodt <felix.willgerodt@intel.com>
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Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3),
x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop). This
patch support gdb to fetch/store these registers.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn> # Framework
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> # Detail Optimizes
Signed-off-by: Hui Li <lihui@loongson.cn> # Error Fixes
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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Add LoongArch's vector extensions support, which including
128bit LSX (i.e., Loongson SIMD eXtension) and 256bit LASX
(i.e., Loongson Advanced SIMD eXtension). This patch support
gdb to fetch/store vector registers.
Signed-off-by: Hui Li <lihui@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
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This commit is the result of running the gdb/copyright.py script,
which automated the update of the copyright year range for all
source files managed by the GDB project to be updated to include
year 2023.
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With the AArch64 Scalable Matrix Extension we have a new TPIDR2 register, and
it will be added to the existing NT_ARM_TLS register set. Kernel patches are
being reviewed here:
https://lore.kernel.org/linux-arm-kernel/20220818170111.351889-1-broonie@kernel.org/
From GDB's perspective, we handle it in a similar way to the existing TPIDR
register. But we need to consider cases of systems that only have TPIDR and
systems that have both TPIDR and TPIDR2.
With that in mind, the following patch adds the required code to support
TPIDR2 and turns the org.gnu.gdb.aarch64.tls feature into a
dynamically-generated target description as opposed to a static target
description containing only TPIDR.
That means we can remove the gdb/features/aarch64-tls.xml file and replace the
existing gdb/features/aarch64-tls.c auto-generated file with a new file that
dynamically generates the target description containing either TPIDR alone or
TPIDR and TPIDR2.
In the future, when *BSD's start to support this register, they can just
enable it as is being done for the AArch64 Linux target.
The core file read/write code has been updated to support TPIDR2 as well.
On GDBserver's side, there is a small change to the find_regno function to
expose a non-throwing version of it.
It always seemed strange to me how find_regno causes the whole operation to
abort if it doesn't find a particular register name. The patch moves code
from find_regno into find_regno_no_throw and makes find_regno call
find_regno_no_throw instead.
This allows us to do register name lookups to find a particular register
number without risking erroring out if nothing is found.
The patch also adjusts the feature detection code for aarch64-fbsd, since
the infrastructure is shared amongst all aarch64 targets. I haven't added
code to support TPIDR2 in aarch64-fbsd though, as I'm not sure when/if
that will happen.
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This patch changes various global target_desc declarations to const, thereby
correcting a prominent source of ODR violations in PowerPC-related target code.
The majority of files/changes are mechanical const-ifications accomplished by
regenerating the C files in features/.
This also required manually updating mips-linux-tdep.h, s390-linux-tdep.h,
nios2-tdep.h, s390-tdep.h, arch/ppc-linux-tdesc.h, arch/ppc-linux-common.c,
and rs6000-tdep.c.
Patch tested against the sourceware trybot, and fully regression tested against
our (Red Hat's) internal test infrastructure on Rawhide aarch64, s390x, x86_64,
and powerpcle.
With this patch, I can finally enable LTO in our GDB package builds. [Tested
with a rawhide scratch build containing this patch.]
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=22395
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=24835
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This patch adds some missing .xml files to features/Makefile so that when the
directory's C files are regenerated, all files are appropriately remade.
This has demonstrated that there have been several "misses" in regenerating
files in this directory. Namely, arm-secext.c and sparc{32,64}-solaris.c. For
the former case, there was what essentially amounts to a typo regarding the
create feature function's name. In the later case, this file has missed at least
one important update in July, 2020, when allocate_target_description was
changed to return a unique pointer.
Those corrections are included.
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Add cskyv2-linux.xml for re-generating cskyv2-linux.c if needed.
Also update cskyv2-linux.c.
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This commit adds floating-point support for LoongArch gdb.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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This patch removes the hardcoded access to PSP in
arm_m_exception_cache() and relies on the definition with the XML
descriptions.
Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
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1. Since 32bit-pkeys.xml and 64bit-pkeys.xml are identical, consolidate
them into a single keys.xml.
2. Enable PKU for x32 to fix:
$ gdbserver :123456 x32-program
...
.../gdbserver/regcache.cc:255: A problem internal to GDBserver has been detected
.
Unknown register pkru requested
on Tiger Lake.
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This commit adds Makefile, configure and NEWS for LoongArch.
Signed-off-by: Zhensong Liu <liuzhensong@loongson.cn>
Signed-off-by: Qing zhang <zhangqing@loongson.cn>
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.
For the avoidance of doubt, all changes in this commits were
performed by the script.
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This patch adds gdbserver support for OpenRISC. This has been used for
debugging the glibc port that in being worked on here:
https://github.com/openrisc/or1k-glibc/tree/or1k-port-2
Hence the comment about registers definitions being inline with glibc.
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This patch adds support for the M-profile MVE extension, which includes the
following:
- New M-profile XML feature m-profile-mve
- MVE vector predication status and control register (VPR)
- p0 pseudo register (contained in the VPR)
- q0 ~ q7 pseudo vector registers
- New feature bits
- Documentation update
Pseudo register p0 is the least significant bits of vpr and can be accessed
as $p0 or displayed through $vpr. For more information about the register
layout, please refer to [1].
The q0 ~ q7 registers map back to the d0 ~ d15 registers, two d registers
per q register.
The register dump looks like this:
(gdb) info reg all
r0 0x0 0
r1 0x0 0
r2 0x0 0
r3 0x0 0
r4 0x0 0
r5 0x0 0
r6 0x0 0
r7 0x0 0
r8 0x0 0
r9 0x0 0
r10 0x0 0
r11 0x0 0
r12 0x0 0
sp 0x0 0x0 <__Vectors>
lr 0xffffffff -1
pc 0xd0c 0xd0c <Reset_Handler>
xpsr 0x1000000 16777216
d0 0 (raw 0x0000000000000000)
d1 0 (raw 0x0000000000000000)
d2 0 (raw 0x0000000000000000)
d3 0 (raw 0x0000000000000000)
d4 0 (raw 0x0000000000000000)
d5 0 (raw 0x0000000000000000)
d6 0 (raw 0x0000000000000000)
d7 0 (raw 0x0000000000000000)
d8 0 (raw 0x0000000000000000)
d9 0 (raw 0x0000000000000000)
d10 0 (raw 0x0000000000000000)
d11 0 (raw 0x0000000000000000)
d12 0 (raw 0x0000000000000000)
d13 0 (raw 0x0000000000000000)
d14 0 (raw 0x0000000000000000)
d15 0 (raw 0x0000000000000000)
fpscr 0x0 0
vpr 0x0 [ P0=0 MASK01=0 MASK23=0 ]
s0 0 (raw 0x00000000)
s1 0 (raw 0x00000000)
s2 0 (raw 0x00000000)
s3 0 (raw 0x00000000)
s4 0 (raw 0x00000000)
s5 0 (raw 0x00000000)
s6 0 (raw 0x00000000)
s7 0 (raw 0x00000000)
s8 0 (raw 0x00000000)
s9 0 (raw 0x00000000)
s10 0 (raw 0x00000000)
s11 0 (raw 0x00000000)
s12 0 (raw 0x00000000)
s13 0 (raw 0x00000000)
s14 0 (raw 0x00000000)
s15 0 (raw 0x00000000)
s16 0 (raw 0x00000000)
s17 0 (raw 0x00000000)
s18 0 (raw 0x00000000)
s19 0 (raw 0x00000000)
s20 0 (raw 0x00000000)
s21 0 (raw 0x00000000)
s22 0 (raw 0x00000000)
s23 0 (raw 0x00000000)
s24 0 (raw 0x00000000)
s25 0 (raw 0x00000000)
s26 0 (raw 0x00000000)
s27 0 (raw 0x00000000)
s28 0 (raw 0x00000000)
s29 0 (raw 0x00000000)
s30 0 (raw 0x00000000)
s31 0 (raw 0x00000000)
q0 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q1 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q2 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q3 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q4 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q5 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q6 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q7 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
p0 0x0 0
Built and regtested with a simulator.
[1] https://developer.arm.com/documentation/ddi0553/bn
Co-Authored-By: Luis Machado <luis.machado@linaro.org>
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Clean up some things I noticed:
- we generate a regformats/microblaze-with-stack-protect.dat file. I
don't think this is used. It could be used by a GDBserver built for
Microblaze, but GDBserver isn't ported to Microblaze. So I don't
think that's used at all. Remove the entry in features/Makefile and
the file itself.
- There are a bunch of *-expedite values in features/Makefile for
architectures for which we don't generate dat files. AFAIK, these
*-expedite values are only used when generating dat files. Remove
those that are not necessary.
- 32bit-segments.xml is not listed in the Makfile, but it's used. This
means that it wouldn't get re-generated if we were to change how C
files are generated from the XML. It looks like it was simply
forgotten, add it.
Change-Id: I112d00db317102270e1df924473c37122ccb6c3a
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Supported ISAs:
- Z80 (all undocumented instructions)
- Z180
- eZ80 (Z80 mode only)
Datasheets:
Z80: https://www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080&extn=.pdf
Z180: https://www.zilog.com/manage_directlink.php?filepath=docs/z180/ps0140&extn=.pdf
eZ80: http://www.zilog.com/force_download.php?filepath=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTlWVFRBd056Y3VjR1Jt
To debug Z80 programs using GDB you must configure and embed
z80-stub.c to your program (SDCC compiler is required). Or
you may use some simulator with GDB support.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add z80-tdep.c.
* NEWS: Mention z80 support.
* configure.tgt: Handle z80*.
* features/Makefile (XMLTOC): Add z80.xml.
* features/z80-cpu.xml: New.
* features/z80.c: Generate.
* features/z80.xml: New.
* z80-tdep.c: New file.
* z80-tdep.h: New file.
gdb/stubs/ChangeLog:
* z80-stub.c: New file.
Change-Id: Id0b7a6e210c3f93c6853c5e3031b7bcee47d0db9
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This patch adds a target description and feature "mte" for aarch64.
It includes one new register, tag_ctl, that can be used to configure the
tag generation rules and sync/async modes. It is 64-bit in size.
The patch also adjusts the code that creates the target descriptions at
runtime based on CPU feature checks.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Take MTE flag into
account.
Slight refactor to hwcap flag checking.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for
MTE.
(aarch64_read_description): Add mte_p parameter and update to use it.
Update the documentation.
(aarch64_gdbarch_init): Update call to aarch64_read_description.
* aarch64-tdep.h (aarch64_read_description): Add mte_p parameter.
* arch/aarch64.c: Include ../features/aarch64-mte.c.
(aarch64_create_target_description): Add mte_p parameter and update
the code to use it.
* arch/aarch64.h (aarch64_create_target_description): Add mte_p
parameter.
* features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml.
* features/aarch64-mte.c: New file, generated.
* features/aarch64-mte.xml: New file.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to
aarch64_linux_read_description.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag
into account.
* linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension
for MTE.
(aarch64_linux_read_description): Add mte_p parameter and update to
use it.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p
parameter.
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This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
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This commit started as adding rv32e support to gdb. The rv32e
architecture is a cut-down rv32i, it only has 16 x-registers compared
to the usual 32, and an rv32e target should not have any floating
point registers.
In order to add this I needed to adjust the target description
validation checks that are performed from riscv_gdbarch_init, and I
finally got fed up with the current scheme of doing these checks and
rewrote this code.
Unfortunately the rv32e changes are currently mixed in with the
rewrite of the validation scheme. I could split these apart if anyone
is really interested in seeing these two ideas as separate patches.
The main idea behind this change is that where previously I tried to
have a purely data driven approach, a set of tables one for each
expected feature, and then a single generic function that would
validate a feature given a table, I have created a new class for each
feature. Each class has its own check member function which allows
the logic for how to check each feature to be different. I think the
new scheme is much easier to follow.
There are some other changes that I made to the validation code as
part of this commit.
I've relaxed some of the checks related to the floating point CSRs.
Previously the 3 CSRs fflags, frm, and fcsr all had to be present in
either the fpu feature or the csr feature. This requirement is now
relaxed, if the CSRs are not present then gdb will not reject the
target description. My thinking here is that there's no gdb
functionality that specifically requires these registers, and so, if a
target offers a description without these registers nothing else in
gdb should stop working.
And as part of the rv32e support targets now only have to provide the
first 16 x-registers and $pc. The second half of the x-registers (x16
-> x31) are now optional.
gdb/ChangeLog:
* arch/riscv.c: Include 'rv32e-xregs.c'.
(riscv_create_target_description): Update to handle rv32e.
* arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New
member variable.
<operator==>: Update to account for new field.
<hash>: Likewise.
* features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml.
* features/riscv/rv32e-xregs.c: Generated.
* features/riscv/rv32e-xregs.xml: New file.
* riscv-tdep.c (riscv_debug_breakpoints): Move from later in the
file.
(riscv_debug_infcall): Likewise.
(riscv_debug_unwinder): Likewise.
(riscv_debug_gdbarch): Likewise.
(enum riscv_register_required_status): Delete.
(struct riscv_register_feature): Add constructor, delete default
constructor, copy, and assign constructors.
(struct riscv_register_feature::register_info) <required>: Delete.
<check>: Update comment and arguments.
(struct riscv_register_feature) <name>: Change to member function.
<prefer_first_name>: Delete.
<tdesc_feature>: New member function.
<registers>: Rename to...
<m_registers>: ...this.
<m_feature_name>: New member variable.
(riscv_register_feature::register_info::check): Update arguments.
(riscv_xreg_feature): Rewrite as class, create a single static
instance of the class.
(riscv_freg_feature): Likewise.
(riscv_virtual_feature): Likewise.
(riscv_csr_feature): Likewise.
(riscv_create_csr_aliases): Has become a member function inside
riscv_csr_feature class.
(riscv_abi_embedded): New function definition.
(riscv_register_name): Adjust to use new feature objects.
(struct riscv_call_info) <riscv_call_info>: Check for rv32e abi,
and adjust available argument registers.
(riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag.
(riscv_check_tdesc_feature): Delete.
(riscv_tdesc_unknown_reg): Adjust to use new feature objects.
(riscv_gdbarch_init): Delete target description checking code, and
instead call to the new feature objects to perform the checks.
Reorder handling of no abi information case, allows small code
simplification.
(_initialize_riscv_tdep): Remove call, this is now done in the
riscv_csr_feature constructor.
* riscv-tdep.h (riscv_abi_embedded): Declare.
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GDB has two approaches to generating the target descriptions found in
gdb/features/, the whole description approach, where the XML file
contains a complete target description which is then used to generate
a single C file that builds that target description. Or, the split
feature approach, where the XML files contain a single target feature,
each feature results in a single C file to create that one feature,
and then a manually written C file is used to build a complete target
description from individual features.
There's a Makefile, gdb/features/Makefile, which is responsible for
managing the regeneration of the C files from the XML files.
However, some of the logic that selects between the whole description
approach, or the split feature approach, is actually hard-coded into
GDB, inside target-descriptions.c:maint_print_c_tdesc_cmd we check the
path to the incoming XML file and use this to choose which type of C
file we should generate.
This commit removes this hard coding from GDB, and makes the Makefile
entirely responsible for choosing the approach. This makes sense as
the Makefile already has the XML files partitioned based on which
approach they should use.
In order to allow this change the 'maint print c-tdesc' command is
given a new command option '-single-feature', which tells GDB which
type of C file should be created. The makefile now supplies this flag
to GDB.
This did reveal a bug in features/Makefile, the rx.xml file was in the
wrong list, this didn't matter previously as the actual choice of
which approach to use was done in GDB. Now the Makefile decides, so
placing each XML file in the correct list is critical.
Tested this by doing 'make GDB=/path/to/gdb clean-cfiles cfiles' to
regenerate all the C files from their XML source. There are no
changes after this commit.
gdb/ChangeLog:
* features/Makefile (XMLTOC): Add rx.xml.
(FEATURE_XMLFILES): Remove rx.xml.
(FEATURE_CFILES rule): Pass '-single-feature' flag.
* features/rx.c: Regenerate.
* features/rx.xml: Wrap in `target` tags, and reindent.
* target-descriptions.c (struct maint_print_c_tdesc_options): New
structure.
(maint_print_c_tdesc_opt_def): New typedef.
(maint_print_c_tdesc_opt_defs): New static global.
(make_maint_print_c_tdesc_options_def_group): New function.
(maint_print_c_tdesc_cmd): Make use of command line flags, only
print single feature C file for target descriptions containing a
single feature.
(maint_print_c_tdesc_cmd_completer): New function.
(_initialize_target_descriptions): Update call to register command
completer, and include command line flag in help text.
gdb/doc/ChangeLog:
* gdb.texinfo (Maintenance Commands): Update description of 'maint
print c-tdesc'.
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A few changes have been made to make the register support simpler,
more flexible and extendible. The trigger for most of these changes
are the remarks [1] made earlier for v2 of this patch. The noticeable
improvements are:
- The arc XML target features are placed under gdb/features/arc
- There are two cores (based on ISA) and one auxiliary feature:
v1-core: ARC600, ARC601, ARC700
v2-core: ARC EM, ARC HS
aux: common in both
- The XML target features represent a minimalistic sane set of
registers irrespective of application (baremetal or linux).
- A concept of "feature" class has been introduced in the code.
The "feature" object is constructed from BFD and GDBARCH data.
It contains necessary information (ISA and register size) to
determine which XML target feature to use.
- A new structure (ARC_REGISTER_FEATURE) is added that allows
providing index, names, and the necessity of registers. This
simplifies the sanity checks and future extendibility.
- Documnetation has been updated to reflect ARC features better.
- Although the feature names has changed, there still exists
backward compatibility with older names through
find_obsolete_[core,aux]_names() functions.
The last two points were inspired from RiscV port.
[1]
https://sourceware.org/pipermail/gdb-patches/2020-May/168511.html
gdb/ChangeLog:
* arch/arc.h
(arc_gdbarch_features): New class to stir the selection of target XML.
(arc_create_target_description): Use FEATURES to choose XML target.
(arc_lookup_target_description): Use arc_create_target_description
to create _new_ target descriptions or return the already created
ones if the FEATURES is the same.
* arch/arc.c: Implementation of prototypes described above.
* gdb/arc-tdep.h (arc_regnum enum): Add more registers.
(arc_gdbarch_features_init): Initialize the FEATURES struct.
* arc-tdep.c (*_feature_name): Make feature names consistent.
(arc_register_feature): A new struct to hold information about
registers of a particular target/feature.
(arc_check_tdesc_feature): Check if XML provides registers in
compliance with ARC_REGISTER_FEATURE structs.
(arc_update_acc_reg_names): Add aliases for r58 and r59.
(determine_*_reg_feature_set): Which feature name to look for.
(arc_gdbarch_features_init): Given MACH and ABFD, initialize FEATURES.
(mach_type_to_arc_isa): Convert from a set of binutils machine types
to expected ISA enums to be used in arc_gdbarch_features structs.
* features/Makefile (FEATURE_XMLFILES): Add new files.
* gdb/features/arc/v1-aux.c: New file.
* gdb/features/arc/v1-aux.xml: Likewise.
* gdb/features/arc/v1-core.c: Likewise.
* gdb/features/arc/v1-core.xml: Likewise.
* gdb/features/arc/v2-aux.c: Likewise.
* gdb/features/arc/v2-aux.xml: Likewise.
* gdb/features/arc/v2-core.c: Likewise.
* gdb/features/arc/v2-core.xml: Likewise.
* NEWS (Changes since GDB 9): Announce obsolence of old feature names.
gdb/doc/ChangeLog:
* gdb.texinfo (Synopsys ARC): Update the documentation for ARC
Features.
gdb/testsuite/ChangeLog:
* gdb.arch/arc-tdesc-cpu.xml: Use new feature names.
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There is currently a bug in the RISC-V CSR/FPU feature files. The
CSRs containing the FPU status registers are mentioned in both the FPU
feature file and the CSR feature file.
My original thinking when adding the FPU feature file was that it made
more sense to group the FPU status registers with the other FPU
state. This opened up the possibility of debugging very
simple (possibly simulator only) targets that had little more than CPU
and FPU available for GDB to access.
When I then added code to automatically generate the CSR XML file I
forgot to filter out the FPU status CSRs, so these registers were
mentioned twice.
Now for GDB's default RISC-V target descriptions this doesn't actually
matter. I did consider adding the CSRs to the default target
description, but in the end I didn't bother. The reasoning again was
simplicity; the default target description is only to be used when the
target doesn't supply its own description, and NOT supplying the CSRs
actually serves to encourage targets to supply an accurate
description. Combine this with the fact that the CSRs change from
revision to revision, sometimes in non-backward compatible ways, then
having a "default" set of CSRs just feels like a path to confusion and
complaints.
However, having a broken CSR XML file in the GDB source tree has had
one negative effect, QEMU has copied this file into its source tree,
and is using this as its description that it passes to GDB. That is
QEMU announces the FPU status registers twice, once in the FPU
feature, and once in the CSR feature.
This commit starts along the path back to sanity by deleting the
default CSR XML files from within GDB. These files were not used in
any way by current GDB, so there is absolutely no loss of
functionality with this change.
gdb/ChangeLog:
* features/Makefile: Remove all references to the deleted files
below.
* features/riscv/32bit-csr.c: Deleted.
* features/riscv/32bit-csr.xml: Deleted.
* features/riscv/64bit-csr.c: Deleted.
* features/riscv/64bit-csr.xml: Deleted.
* features/riscv/rebuild-csr-xml.sh: Deleted.
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This patch removes the leftover regformats .dat files for the arm
architecture. There are no longer relevant, since the arm architecture
has been converted to use feature-based target-descriptions. These .dat
files are used by GDBserver ports that still use static target
descriptions.
These .dat files are generated from corresponding .xml files in the
features directory. And since the corresponding .xml files for these
arm .dat files don't exist anymore, it is impossible to re-generated
them. If you delete these .dat files and type "make" in the features
directory, you'll get:
make: *** No rule to make target '../regformats/arm/arm-with-iwmmxt.dat', needed by 'all'. Stop.
So it removes the entries in the `WHICH` variable of
gdb/features/Makefile.
Finally, it removes the rule in gdbserver/Makefile to generate .cc files
from `../gdb/regformats/arm/%.dat`.
gdb/ChangeLog:
* features/Makefile (WHICH): Remove arm files.
* regformats/arm/arm-with-iwmmxt.dat: Remove.
* regformats/arm/arm-with-neon.dat: Remove.
* regformats/arm/arm-with-vfpv2.dat: Remove.
* regformats/arm/arm-with-vfpv3.dat: Remove.
gdbserver/ChangeLog:
* Makefile.in (%-generated.cc: ../gdb/regformats/arm/%.dat):
Remove.
Change-Id: I3b7d989c50e2cb92235c1f7c7071a26839d84c78
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When trying to run `make` in the features directory, in a clean repo, we
get:
Makefile:254: warning: overriding recipe for target 'rx.c'
Makefile:250: warning: ignoring old recipe for target 'rx.c'
make: Nothing to be done for 'all'.
The warnings come from the fact that `rx.xml` is present in two lists,
causing two `rx.c` targets to be defined. It is ok for it to be in the
FEATURES_XMLFILES list, as this architecture uses the "feature-based"
target-descriptions. It shouldn't be in the XMLTOC list, as this is for
architectures that define complete/static target descriptions as XML
files.
gdb/ChangeLog:
* features/Makefile (XMLTOC): Remove rx.xml.
Change-Id: Iada4ab54b3d4542588fac543d16ee35a92537319
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This patch replaces usage of target descriptions in ARC, where the whole
description is fixed in XML, with new target descriptions where XML describes
individual features, and GDB assembles those features into actual target
description.
v2:
Removed arc.c from ALLDEPFILES in gdb/Makefile.in.
Removed vim modeline from arc-tdep.c to have it in a separate patch.
Removed braces from one line "if/else".
Undid the type change for "jb_pc" (kept it as "int").
Joined the unnecessary line breaks into one line.
No more moving around arm targets in gdb/features/Makefile.
Changed pattern checking for ARC features from "arc/{aux,core}" to "arc/".
v3:
Added include gaurds to arc.h.
Added arc_read_description to _create_ target descriptions less.
v4:
Got rid of ARC_SYS_TYPE_NONE.
Renamed ARC_SYS_TYPE_INVALID to ARC_SYS_TYPE_NUM.
Fixed a few indentations/curly braces.
Converted arc_sys_type_to_str from a macro to an inline function.
gdb/ChangeLog:
2020-03-16 Anton Kolesov <anton.kolesov@synopsys.com>
Shahab Vahedi <shahab@synopsys.com>
* Makefile.in: Add arch/arc.o
* configure.tgt: Likewise.
* arc-tdep.c (arc_tdesc_init): Use arc_read_description.
(_initialize_arc_tdep): Don't initialize old target descriptions.
(arc_read_description): New function to cache target descriptions.
* arc-tdep.h (arc_read_description): Add proto type.
* arch/arc.c: New file.
* arch/arc.h: Likewise.
* features/Makefile: Replace old target descriptions with new.
* features/arc-arcompact.c: Remove.
* features/arc-arcompact.xml: Likewise.
* features/arc-v2.c: Likewise
* features/arc-v2.xml: Likewise
* features/arc/aux-arcompact.xml: New file.
* features/arc/aux-v2.xml: Likewise.
* features/arc/core-arcompact.xml: Likewise.
* features/arc/core-v2.xml: Likewise.
* features/arc/aux-arcompact.c: Generate.
* features/arc/aux-v2.c: Likewise.
* features/arc/core-arcompact.c: Likewise.
* features/arc/core-v2.c: Likewise.
* target-descriptions (maint_print_c_tdesc_cmd): Support ARC features.
|
|
gdb/ChangeLog:
Update copyright year range in all GDB files.
|
|
This patch implements removal of Cell/B.E. support, including
- Support for the spu-*-* target
- Support for native stand-alone SPU debugging
- Support for integrated debugging of combined PPU/SPU applications
- Remote debugging (gdbserver) support for all the above.
The patch also removes the TARGET_OBJECT_SPU target object type,
as this is available only on Cell/B.E. targets, including
- Native Linux support
- Core file support (including core file generation)
- Remote target support, including removal of the qXfer:spu:read
and qXfer:spu:write remote protocal packets and associated
support in gdbserver.
gdb/ChangeLog
2019-09-20 Ulrich Weigand <uweigand@de.ibm.com>
* NEWS: Mention that Cell/B.E. debugging support was removed.
* MAINTAINERS: Remove spu target.
* config/djgpp/fnchange.lst: Remove entries for removed files.
* Makefile.in (ALL_TARGET_OBS): Remove solib-spu.o,
spu-multiarch.o, and spu-tdep.o.
(HFILES_NO_SRCDIR): Remove solib-spu.h and spu-tdep.h.
(ALLDEPFILES): Remove solib-spu.c, spu-linux-nat.c,
spu-multiarch.c, and spu-tdep.c.
* spu-linux-nat.c: Remove file.
* spu-multiarch.c: Remove file.
* spu-tdep.c: Remove file.
* spu-tdep.h: Remove file.
* solib-spu.c: Remove file.
* solib-spu.h: Remove file.
* configure.host (powerpc64*-*-linux*): Remove Cell/B.E. support.
* configure.nat (spu-linux): Remove.
* configure.tgt (powerpc*-*-linux*): Remove solib-spu.o and
solib-multiarch.o from gdb_target_obs.
(spu*-*-*): Remove.
* arch/ppc-linux-common.h (struct ppc_linux_features): Remove "cell"
feature flag.
(ppc_linux_no_features): Update.
* arch/ppc-linux-common.c (ppc_linux_match_description): Remove
Cell/B.E. support.
* arch/ppc-linux-tdesc.h (tdesc_powerpc_cell32l): Remove declaration.
(tdesc_powerpc_cell64l): Likewise.
* nat/ppc-linux.h (PPC_FEATURE_CELL): Remove.
* ppc-linux-nat.c (ppc_linux_nat_target::read_description): Remove
Cell/B.E. support.
* ppc-linux-tdep.h: Do not include "solib-spu.h" or "spu-tdep.h".
Do not include "features/rs6000/powerpc-cell32l.c" or
"features/rs6000/powerpc-cell64l.c".
(ppc_linux_spu_section): Remove.
(ppc_linux_core_read_description): Remove Cell/B.E. support.
(spe_context_objfile, spe_context_lm_addr, spe_context_offset,
spe_context_cache_ptid, spe_context_cache_ptid): Remove.
(ppc_linux_spe_context_lookup): Remove.
(ppc_linux_spe_context_inferior_created): Remove.
(ppc_linux_spe_context_solib_loaded): Remove.
(ppc_linux_spe_context_solib_unloaded): Remove.
(ppc_linux_spe_context): Remove.
(struct ppu2spu_cache): Remove.
(ppu2spu_prev_arch, ppu2spu_this_id, ppu2spu_prev_register): Remove.
(struct ppu2spu_data): Remove.
(ppu2spu_unwind_register, ppu2spu_sniffer, ppu2spu_dealloc_cache,
ppu2spu_unwind): Remove.
(ppc_linux_init_abi): Remove Cell/B.E. support.
* rs6000-tdep.h (rs6000_gdbarch_init): Remove Cell/B.E. support.
* features/Makefile (rs6000/powerpc-cell32l-expedite): Remove.
(rs6000/powerpc-cell64l-expedite): Likewise
(WHICH): Remove rs6000/powerpc-cell32l and rs6000/powerpc-cell64l.
(XMLTOC): Remove rs6000/powerpc-cell32l.xml and
rs6000/powerpc-cell64l.xml.
* features/rs6000/powerpc-cell32l.xml: Remove.
* features/rs6000/powerpc-cell64l.xml: Likewise.
* features/rs6000/powerpc-cell32l.c: Remove generated file.
* features/rs6000/powerpc-cell64l.c: Likewise.
* regformats/rs6000/powerpc-cell32l.dat: Remove generated file.
* regformats/rs6000/powerpc-cell64l.dat: Likewise.
* regformats/reg-spu.dat: Remove.
* target.h (enum target_object): Remove TARGET_OBJECT_SPU.
* corelow.c (struct spuid_list): Remove.
(add_to_spuid_list): Remove.
(core_target::xfer_partial): Remove support for TARGET_OBJECT_SPU.
* remote.c (PACKET_qXfer_spu_read, PACKET_qXfer_spu_write): Remove.
(remote_protocol_features): Remove associated entries.
(_initialize_remote): No longer initialize them.
(remote_target::xfer_partial): Remove support for TARGET_OBJECT_SPU.
* linux-nat.c (SPUFS_MAGIC): Remove.
(linux_proc_xfer_spu): Remove.
(spu_enumerate_spu_ids): Remove.
(linux_nat_target::xfer_partial): Remove support for TARGET_OBJECT_SPU.
* linux-tdep.c (-linux_spu_make_corefile_notes): Remove.
(linux_make_corefile_notes): No longer call it.
* regcache.c (cooked_read_test): Remove bfd_arch_spu special case.
(cooked_write_test): Likewise.
gdb/doc/ChangeLog
2019-09-20 Ulrich Weigand <uweigand@de.ibm.com>
* doc/gdb.texinfo (Remote Configuration): Remove documentation for
qXfer:spu:read and qXfer:spu:write.
(General Query Packets): Likewise.
(Cell Broadband Engine SPU architecture): Remove subsection.
gdb/gdbserver/ChangeLog
2019-09-20 Ulrich Weigand <uweigand@de.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Remove powerpc-cell32l-ipa.o
and powerpc-cell64l-ipa.o.
(powerpc*-*-linux*): Remove powerpc-cell32l.o and powerpc-cell64l.o
from srv_regobj. Remove rs6000/powerpc-cell32l.xml and
rs6000/powerpc-cell64l.xml from srv_xmlfiles.
(spu*-*-*): Remove.
* spu-low.c: Remove file.
* linux-ppc-low.c (INSTR_SC, NR_spu_run): Remove.
(parse_spufs_run): Remove.
(ppc_get_pc): Remove Cell/B.E. support.
(ppc_set_pc): Likewise.
(ppc_breakpoint_at): Likewise.
(ppc_arch_setup): Likewise.
(ppc_get_ipa_tdesc_idx): Do not handle tdesc_powerpc_cell64l or
tdesc_powerpc_cell32l.
(initialize_low_arch): Do not call init_registers_powerpc_cell64l
or init_registers_powerpc_cell32l.
* linux-ppc-ipa.c (get_ipa_tdesc): Do not handle PPC_TDESC_CELL.
(initialize_low_tracepoint): Do not call init_registers_powerpc_cell64l
or init_registers_powerpc_cell32l.
* linux-ppc-tdesc-init.h (PPC_TDESC_CELL): Mark as unused.
(init_registers_powerpc_cell32l): Remove prototype.
(init_registers_powerpc_cell64l): Likewise.
* target.h (struct target_ops): Remove qxfer_spu member.
* server.c (handle_qxfer_spu): Remove.
(qxfer_packets): Remove entry for "spu".
(handle_query): No longer support qXfer:spu:read or qXfer:spu:write.
* linux-low.c (SPUFS_MAGIC): Remove.
(spu_enumerate_spu_ids): Remove.
(linux_qxfer_spu): Remove.
(linux_target_ops): Remove qxfer_spu member.
* lynx-low.c (lynx_target_ops): Remove qxfer_spu member.
* nto-low.c (nto_target_ops): Remove qxfer_spu member.
* win32-low.c (win32_target_ops): Remove qxfer_spu member.
gdb/testsuite/ChangeLog
2019-09-20 Ulrich Weigand <uweigand@de.ibm.com>
* gdb.arch/spu-info.exp: Remove file.
* gdb.arch/spu-info.c: Remove file.
* gdb.arch/spu-ls.exp: Remove file.
* gdb.arch/spu-ls.c: Remove file.
* gdb.asm/asm-source.exp: Remove support for spu*-*-*.
* gdb.asm/spu.inc: Remove file.
* gdb.base/dump.exp: Remove support for spu*-*-*.
* gdb.base/stack-checking.exp: Likewise.
* gdb.base/overlays.exp: Likewise.
* gdb.base/ovlymgr.c: Likewise.
* gdb.base/spu.ld: Remove file.
* gdb.cp/bs15503.exp: Remove support for spu*-*-*.
* gdb.cp/cpexprs.exp: Likewise.
* gdb.cp/exception.exp: Likewise.
* gdb.cp/gdb2495.exp: Likewise.
* gdb.cp/mb-templates.exp: Likewise.
* gdb.cp/pr9167.exp: Likewise.
* gdb.cp/userdef.exp: Likewise.
* gdb.xml/tdesc-regs.exp: Remove support for spu*-*-*.
* gdb.cell: Remove directory.
* lib/cell.exp: Remove file.
|
|
gdb/ChangeLog
2019-08-25 Yoshinori Sato <ysato@users.sourceforge.jp>
* gdb/rx-tdep.c (rx_register_names): New.
(rx_register_name): Delete.
(rx_psw_type): Delete.
(rx_fpsw_type): Delete.
(rx_register_type): Delete.
(rx_gdbarch_init): Convert target-descriptions.
(_initialize_rx_tdep): Add initialize_tdesc_rx.
* gdb/features/Makefile: Add rx.xml.
* gdb/features/rx.xml: New.
* gdb/features/rx.c: Generated.
* gdb/NEWS: Mention target description support.
gdb/doc/ChangeLog:
2019-08-25 Yoshinori Sato <ysato@users.sourceforge.jp>
* gdb.texinfo (Standard Target Features): Add RX Features sub-section.
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Add Arm to the list of feature target description targets and generate the
relevant C files.
Add arm-m-profile-with-fpa.xml as the feature version of the exisiting
arm-with-m-fpa-layout.xml.
Add extra comments to the Makefile for readability.
New files are not yet used.
gdb/ChangeLog:
* features/Makefile: Use feature target descriptions for Arm.
* features/arm/arm-core.c: Generate new file.
* features/arm/arm-fpa.c: Likewise.
* features/arm/arm-m-profile-with-fpa.xml: Likewise.
* features/arm/arm-m-profile.c: Likewise.
* features/arm/arm-vfpv2.c: Likewise.
* features/arm/arm-vfpv3.c: Likewise.
* features/arm/xscale-iwmmxt.c: Likewise.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add Arm.
|
|
Remove all the xml files that are no longer used by gdbserver,
and remove their entries from the makefile.
gdb/ChangeLog:
* features/Makefile: Remove unused xml files.
* features/aarch64.xml: Remove.
* features/i386/amd64-avx-avx512-linux.xml: Remove.
* features/i386/amd64-avx-avx512.xml: Remove.
* features/i386/amd64-avx-linux.xml: Remove.
* features/i386/amd64-avx-mpx-avx512-pku-linux.xml: Remove.
* features/i386/amd64-avx-mpx-avx512-pku.xml: Remove.
* features/i386/amd64-avx-mpx-linux.xml: Remove.
* features/i386/amd64-avx-mpx.xml: Remove.
* features/i386/amd64-avx.xml: Remove.
* features/i386/amd64-linux.xml: Remove.
* features/i386/amd64-mpx-linux.xml: Remove.
* features/i386/amd64-mpx.xml: Remove.
* features/i386/amd64.xml: Remove.
* features/i386/i386-avx-avx512-linux.xml: Remove.
* features/i386/i386-avx-avx512.xml: Remove.
* features/i386/i386-avx-linux.xml: Remove.
* features/i386/i386-avx-mpx-avx512-pku-linux.xml: Remove.
* features/i386/i386-avx-mpx-avx512-pku.xml: Remove.
* features/i386/i386-avx-mpx-linux.xml: Remove.
* features/i386/i386-avx-mpx.xml: Remove.
* features/i386/i386-avx.xml: Remove.
* features/i386/i386-linux.xml: Remove.
* features/i386/i386-mmx-linux.xml: Remove.
* features/i386/i386-mmx.xml: Remove.
* features/i386/i386-mpx-linux.xml: Remove.
* features/i386/i386-mpx.xml: Remove.
* features/i386/i386.xml: Remove.
* features/i386/x32-avx-avx512-linux.xml: Remove.
* features/i386/x32-avx-linux.xml: Remove.
* features/i386/x32-linux.xml: Remove.
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Pointer Authentication is a new feature in AArch64 v8.3-a. When enabled in
the compiler, function return addresses will be mangled by the kernel.
Add register description xml and wire up to aarch64_linux_read_description.
This description includes the two pauth user registers.
Nothing yet uses the feature - that is added in later patches.
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Add pauth param.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (struct target_desc): Add in pauth.
(aarch64_read_description): Add pauth param.
(aarch64_gdbarch_init): Likewise.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/Makefile: Add new files.
* features/aarch64-pauth.c: New file.
* features/aarch64-pauth.xml: New file.
gdb/doc/ChangeLog:
* gdb.texinfo: Describe pauth feature.
gdb/gdbserver/ChangeLog:
* linux-aarch64-ipa.c (get_ipa_tdesc): Add pauth param.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.c (aarch64_arch_setup): Likewise.
* linux-aarch64-tdesc-selftest.c (aarch64_tdesc_test): Likewise.
* linux-aarch64-tdesc.c (struct target_desc): Likewise.
(aarch64_linux_read_description): Likewise.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Likewise.
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This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
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This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
|
|
This patch adds support for Hardware Transactional Memory registers
for the powerpc linux native and core file targets, and for the
pwoerpc linux server stub.
These registers include both the HTM special-purpose registers (TFHAR,
TEXASR and TFIAR) as well as the set of registers that are
checkpointed (saved) when a transaction is initiated, which the
processor restores in the event of a transaction failure.
The set of checkpointed general-purpose registers is returned by the
linux kernel in the same format as the regular general-purpose
registers, defined in struct pt_regs. However, the architecture
specifies that only some of the registers present in pt_regs are
checkpointed (GPRs 0-31, CR, XER, LR and CTR). The kernel fills the
slots for MSR and NIP with other info. The other fields usually don't
have meaningful values. GDB doesn't define registers that are not
checkpointed in the architecture, but when generating a core file, GDB
fills the slot for the checkpointed MSR with the regular MSR. These
are usually similar, although some bits might be different, and in
some cases the checkpointed MSR will have a value of 0 in a
kernel-generated core-file. The checkpointed NIP is filled with TFHAR
by GDB in the core-file, which is what the kernel does. The other
fields are set to 0 by GDB.
Core files generated by the kernel have a note section for
checkpointed GPRs with the same size for both 32-bit and 64-bit
threads, and the values for the registers of a 32-bit thread are
squeezed in the first half, with no useful data in the second half.
GDB generates a smaller note section for 32-bit threads, but can read
both sizes.
The checkpointed XER is required to be 32-bit in the target
description documentation, even though the more recent ISAs define it
as 64-bit wide, since the high-order 32-bits are reserved, and because
in Linux there is no way to get a 64-bit checkpointed XER for 32-bit
threads. If this changes in the future, the target description
feature requirement can be relaxed to allow for a 64-bit checkpointed
XER.
Access to the checkpointed CR (condition register) can be confusing.
The architecture only specifies that CR fields 1 to 7 (the 24 least
significant bits) are checkpointed, but the kernel provides all 8
fields (32 bits). The value of field 0 is not masked by ptrace, so it
will sometimes show the result of some kernel operation, probably
treclaim., which sets this field.
The checkpointed registers are marked not to be saved and restored.
Inferior function calls during an active transaction don't work well,
and it's unclear what should be done in this case. TEXASR and TFIAR
can be altered asynchronously, during transaction failure recording,
so they are also not saved and restored. For consistency neither is
TFHAR.
Record and replay also doesn't work well when transactions are
involved. This patch doesn't address this, so the values of the HTM
SPRs will sometimes be innacurate when the record/relay target is
enabled. For instance, executing a "tbegin." alters TFHAR and TEXASR,
but these changes are not currently recorded.
Because the checkpointed registers are only available when a
transaction is active (or suspended), ptrace can return ENODATA when
gdb tries to read these registers and the inferior is not in a
transactional state. The registers are set to the unavailable state
when this happens. When gbd tries to write to one of these registers,
and it is unavailable, an error is raised.
The "fill" functions for checkpointed register sets in the server stub
are not implemented for the same reason as for the EBB register set,
since ptrace can also return ENODATA for checkpointed regsets. The
same issues with 'G' packets apply here.
Just like for the EBB registers, tracepoints will not mark the
checkpointed registers as unavailable if the inferior was not in a
transaction, so their content will also show 0 instead of
<unavailable> when inspecting trace data.
The new tests record the values of the regular registers before
stepping the inferior through a "tbegin." instruction to start a
transaction, then the checkpointed registers are checked against the
recorded pre-transactional values. New values are written to the
checkpointed registers and recorded, the inferior continues until the
transaction aborts (which is usually immediately when it is resumed),
and the regular registers are checked against the recorded values,
because the abort should have reverted the registers to these values.
Like for the EBB registers, target_store_registers will ignore the
checkpointed registers when called with -1 as the regno
argument (store all registers in one go).
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_htm_vsx32l)
(tdesc_powerpc_isa207_htm_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TM_SPRREGSET)
(PPC32_LINUX_SIZEOF_CGPRREGSET, PPC64_LINUX_SIZEOF_CGPRREGSET)
(PPC_LINUX_SIZEOF_CFPRREGSET, PPC_LINUX_SIZEOF_CVMXREGSET)
(PPC_LINUX_SIZEOF_CVSXREGSET, PPC_LINUX_SIZEOF_CPPRREGSET)
(PPC_LINUX_SIZEOF_CDSCRREGSET, PPC_LINUX_SIZEOF_CTARREGSET):
Define.
(struct ppc_linux_features) <htm>: New field.
(ppc_linux_no_features): Add initializer for htm field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_HTM, NT_PPC_TM_CGPR)
(NT_PPC_TM_CFPR, NT_PPC_TM_CVMX, NT_PPC_TM_CVSX)
(NT_PPC_TM_SPR, NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR):
Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-htm-vsx32l
and rs6000/powerpc-isa207-htm-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-htm-vsx32l.xml and
rs6000/powerpc-isa207-htm-vsx64l.xml.
* features/rs6000/power-htm-spr.xml: New file.
* features/rs6000/power-htm-core.xml: New file.
* features/rs6000/power64-htm-core.xml: New file.
* features/rs6000/power-htm-fpu.xml: New file.
* features/rs6000/power-htm-altivec.xml: New file.
* features/rs6000/power-htm-vsx.xml: New file.
* features/rs6000/power-htm-ppr.xml: New file.
* features/rs6000/power-htm-dscr.xml: New file.
* features/rs6000/power-htm-tar.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-htm-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with HTM regsets.
(store_register, store_ppc_registers): Call store_regset with HTM
regsets.
(ppc_linux_nat_target::read_description): Set htm field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-htm-vsx32l.c and
features/rs6000/powerpc-isa207-htm-vsx64l.c.
(ppc32_regmap_tm_spr, ppc32_regmap_cgpr, ppc64_le_regmap_cgpr)
(ppc64_be_regmap_cgpr, ppc32_regmap_cfpr, ppc32_le_regmap_cvmx)
(ppc32_be_regmap_cvmx, ppc32_regmap_cvsx, ppc32_regmap_cppr)
(ppc32_regmap_cdscr, ppc32_regmap_ctar): New globals.
(ppc32_linux_tm_sprregset, ppc32_linux_cgprregset)
(ppc64_be_linux_cgprregset, ppc64_le_linux_cgprregset)
(ppc32_linux_cfprregset, ppc32_le_linux_cvmxregset)
(ppc32_be_linux_cvmxregset, ppc32_linux_cvsxregset)
(ppc32_linux_cpprregset, ppc32_linux_cdscrregset)
(ppc32_linux_ctarregset): New globals.
(ppc_linux_cgprregset, ppc_linux_cvmxregset): New functions.
(ppc_linux_collect_core_cpgrregset): New function.
(ppc_linux_iterate_over_regset_sections): Call back with the htm
regsets.
(ppc_linux_core_read_description): Check if the tm spr section is
present and set htm in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_htm_vsx32l and
initialize_tdesc_powerpc_isa207_htm_vsx64l.
* ppc-linux-tdep.h (ppc_linux_cgprregset, ppc_linux_cvmxregset):
Declare.
(ppc32_linux_tm_sprregset, ppc32_linux_cfprregset)
(ppc32_linux_cvsxregset, ppc32_linux_cpprregset)
(ppc32_linux_cdscrregset, ppc32_linux_ctarregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <have_htm_spr, have_htm_core>:
New fields.
<have_htm_fpu, have_htm_altivec, have_htm_vsx>:
Likewise.
<ppc_cppr_regnum, ppc_cdscr_regnum, ppc_ctar_regnum>: Likewise.
<ppc_cdl0_regnum, ppc_cvsr0_regnum, ppc_cefpr0_regnum>: Likewise.
(enum) <PPC_TFHAR_REGNUM, PPC_TEXASR_REGNUM, PPC_TFIAR_REGNUM>:
New enum fields.
<PPC_CR0_REGNUM, PPC_CCR_REGNUM, PPC_CXER_REGNUM>: Likewise.
<PPC_CLR_REGNUM, PPC_CCTR_REGNUM, PPC_CF0_REGNUM>: Likewise.
<PPC_CFPSCR_REGNUM, PPC_CVR0_REGNUM, PPC_CVSCR_REGNUM>: Likewise.
<PPC_CVRSAVE_REGNUM, PPC_CVSR0_UPPER_REGNUM>: Likewise.
<PPC_CPPR_REGNUM, PPC_CDSCR_REGNUM>: Likewise.
<PPC_CTAR_REGNUM>: Likewise.
(PPC_IS_TMSPR_REGNUM, PPC_IS_CKPTGP_REGNUM, PPC_IS_CKPTFP_REGNUM)
(PPC_IS_CKPTVMX_REGNUM, PPC_IS_CKPTVSX_REGNUM): Define.
* rs6000-tdep.c (IS_CDFP_PSEUDOREG, IS_CVSX_PSEUDOREG)
(IS_CEFP_PSEUDOREG): Define.
(rs6000_register_name): Hide the upper halves of checkpointed VSX
registers. Return names for the checkpointed DFP, VSX, and EFP
pseudo registers.
(rs6000_pseudo_register_type): Remove initial assert and raise an
internal error in the else clause instead. Return types for the
checkpointed DFP, VSX, and EFP pseudo registers.
(dfp_pseudo_register_read, dfp_pseudo_register_write): Handle
checkpointed DFP pseudo registers.
(vsx_pseudo_register_read, vsx_pseudo_register_write): Handle
checkpointed VSX pseudo registers.
(efp_pseudo_register_read, efp_pseudo_register_write): Rename
from efpr_pseudo_register_read and
efpr_pseudo_register_write. Handle checkpointed EFP pseudo
registers.
(rs6000_pseudo_register_read, rs6000_pseudo_register_write):
Handle checkpointed DFP, VSX, and EFP registers.
(dfp_ax_pseudo_register_collect, vsx_ax_pseudo_register_collect)
(efp_ax_pseudo_register_collect): New functions.
(rs6000_ax_pseudo_register_collect): Move DFP, VSX and EFP pseudo
register logic to new functions. Handle checkpointed DFP, VSX,
and EFP pseudo registers.
(rs6000_gdbarch_init): Look for and validate the htm features.
Include checkpointed DFP, VSX and EFP pseudo-registers.
* NEWS: Mention access to PPR, DSCR, TAR, EBB/PMU registers and
HTM registers.
gdb/gdbserver/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-htm-vsx32l-ipa.o and
powerpc-isa207-htm-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-htm-vsx32l.o and
powerpc-isa207-htm-vsx64l.o to srv_regobj. Add
rs6000/power-htm-spr.xml, rs6000/power-htm-core.xml,
rs6000/power64-htm-core.xml, rs6000/power-htm-fpu.xml,
rs6000/power-htm-altivec.xml, rs6000/power-htm-vsx.xml,
rs6000/power-htm-ppr.xml, rs6000/power-htm-dscr.xml,
rs6000/power-htm-tar.xml, rs6000/powerpc-isa207-htm-vsx32l.xml,
and rs6000/powerpc-isa207-htm-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_HTM_VSX>: New enum value.
(init_registers_powerpc_isa207_htm_vsx32l)
(init_registers_powerpc_isa207_htm_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tm_sprregset, ppc_store_tm_sprregset)
(ppc_store_tm_cgprregset, ppc_store_tm_cfprregset)
(ppc_store_tm_cvrregset, ppc_store_tm_cvsxregset)
(ppc_store_tm_cpprregset, ppc_store_tm_cdscrregset)
(ppc_store_tm_ctarregset): New functions.
(ppc_regsets): Add entries for HTM regsets.
(ppc_arch_setup): Set htm in features struct when needed. Set
sizes for the HTM regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-htm-regs.c: New file.
* gdb.arch/powerpc-htm-regs.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new features
"org.gnu.gdb.power.htm.spr", "org.gnu.gdb.power.htm.core",
"org.gnu.gdb.power.htm.fpu", "org.gnu.gdb.power.htm.altivec",
"org.gnu.gdb.power.htm.vsx", "org.gnu.gdb.power.htm.ppr",
"org.gnu.gdb.power.htm.dscr", "org.gnu.gdb.power.htm.tar".
|
|
This patch adds support for the Target Address Register for powerpc
linux native and core file targets, and in the powerpc linux server
stub.
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_vsx32l)
(tdesc_powerpc_isa207_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TARREGSET): Define.
(struct ppc_linux_features) <isa207>: New field.
(ppc_linux_no_features): Add initializer for isa207 field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_ARCH_2_07, PPC_FEATURE2_TAR)
(NT_PPC_TAR): Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-vsx32l and
rs6000/powerpc-isa207-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-vsx32l.xml and
rs6000/powerpc-isa207-vsx64l.xml.
* features/rs6000/power-tar.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with the TAR regset.
(store_register, store_ppc_registers): Call store_regset with the
TAR regset.
(ppc_linux_nat_target::read_description): Set isa207 field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-vsx32l.c and
features/rs6000/powerpc-isa207-vsx64l.c.
(ppc32_regmap_tar, ppc32_linux_tarregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the tar
regset.
(ppc_linux_core_read_description): Check if the tar section is
present and set isa207 in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_vsx32l and
initialize_tdesc_powerpc_isa207_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_tarregset): Declare.
* ppc-tdep.h (gdbarch_tdep) <ppc_tar_regnum>: New field.
(enum) <PPC_TAR_REGNUM>: New enum value.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate tar
feature.
(ppc_process_record_op31): Record changes to TAR.
gdb/gdbserver/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-vsx64l-ipa.o and powerpc-isa207-vsx32l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-vsx32l.o and
powerpc-isa207-vsx64l.o to srv_regobj, add rs6000/power-tar.xml,
rs6000/powerpc-isa207-vsx32l.xml, and
rs6000/powerpc-isa207-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_VSX>: New enum value.
(init_registers_powerpc_isa207_vsx32l): Declare.
(init_registers_powerpc_isa207_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tarregset): New function.
(ppc_store_tarregset): New function.
(ppc_regsets): Add entry for the TAR regset.
(ppc_arch_setup): Set isa207 in features struct when needed. Set
size for the TAR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX.
(initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l
and init_registers_powerpc_isa207_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_vsx32l and
init_registers_powerpc_isa207_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-tar.c: New file.
* gdb.arch/powerpc-tar.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new feature
"org.gnu.gdb.power.tar".
|
|
This patch adds gdb support for the Program Priorty Register and the
Data Stream Control Register, for the powerpc linux native and core
file targets, and for the powerpc linux server stub.
gdb/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa205_ppr_dscr_vsx32l)
(tdesc_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_PPRREGSET)
(PPC_LINUX_SIZEOF_DSCRREGSET): Define.
(struct ppc_linux_features) <ppr_dscr>: New field.
(ppc_linux_no_features): Add initializer for ppr_dscr field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_DSCR, NT_PPC_PPR, NT_PPC_DSCR):
Define if not already defined.
* features/Makefile (WHICH): Add
rs6000/powerpc-isa205-ppr-dscr-vsx32l and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml.
* features/rs6000/power-dscr.xml: New file.
* features/rs6000/power-ppr.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Generate.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat: Generate.
* ppc-linux-nat.c: Include <sys/uio.h>.
(fetch_regset, store_regset, check_regset): New functions.
(fetch_register, fetch_ppc_registers): Call fetch_regset with
DSCR and PPR regsets.
(store_register, store_ppc_registers): Call store_regset with
DSCR and PPR regsets.
(ppc_linux_get_hwcap2): New function.
(ppc_linux_nat_target::read_description): Call
ppc_linux_get_hwcap2 and check_regset, set ppr_dscr field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c and
features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c.
(ppc32_regmap_ppr, ppc32_regmap_dscr, ppc32_linux_pprregset)
(ppc32_linux_dscrregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the ppr
and dscr regsets.
(ppc_linux_core_read_description): Check if the ppr and dscr
sections are present and set ppr_dscr in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l and
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_pprregset)
(ppc32_linux_dscrregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <ppc_ppr_regnum>: New field.
<ppc_dscr_regnum>: New field.
(enum) <PPC_PPR_REGNUM, PPC_DSCR_REGNUM>: New enum values.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate ppr
and dscr features.
(ppc_process_record_op31): Record changes to PPR and DSCR.
gdb/gdbserver/ChangeLog:
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa205-ppr-dscr-vsx32l-ipa.o and
powerpc-isa205-ppr-dscr-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa205-ppr-dscr-vsx32l.o and
powerpc-isa205-ppr-dscr-vsx64l.o to srv_regobj, add
rs6000/power-dscr.xml, rs6000/power-ppr.xml,
rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml to srv_xmlfiles.
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA205_PPR_DSCR_VSX>: New enum value.
(init_registers_powerpc_isa205_ppr_dscr_vsx32l)
(init_registers_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* linux-ppc-low.c: Include "elf/common.h" and <sys/uio.h>.
(ppc_hwcap): Add comment.
(ppc_hwcap2): New global.
(ppc_check_regset, ppc_fill_pprregset, ppc_store_pprregset)
(ppc_fill_dscrregset, ppc_store_dscrregset): New functions.
(ppc_regsets): Add entries for the DSCR and PPR regsets.
(ppc_arch_setup): Get AT_HWCAP2. Set ppr_dscr in features struct
when needed. Set sizes for the the DSCR and PPR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
gdb/testsuite/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-ppr-dscr.c: New file.
* gdb.arch/powerpc-ppr-dscr.exp: New file.
gdb/doc/ChangeLog:
2018-10-26 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Describe new features
"org.gnu.gdb.power.ppr" and "org.gnu.gdb.power.dscr".
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For all targets which use the newer style target descriptions, add a
"feature" marker in the dat files.
Update regdat.sh to parse feature, but do not use it (yet).
gdb/
* features/Makefile: Add feature marker to targets with new style
target descriptions.
* regformats/aarch64.dat: Regenerate.
* regformats/i386/amd64-avx-avx512-linux.dat: Likewise.
* regformats/i386/amd64-avx-linux.dat: Likewise.
* regformats/i386/amd64-avx-mpx-avx512-pku-linux.dat: Likewise.
* regformats/i386/amd64-avx-mpx-linux.dat: Likewise.
* regformats/i386/amd64-linux.dat: Likewise.
* regformats/i386/amd64-mpx-linux.dat: Likewise.
* regformats/i386/amd64.dat: Likewise.
* regformats/i386/i386-avx-avx512-linux.dat: Likewise.
* regformats/i386/i386-avx-linux.dat: Likewise.
* regformats/i386/i386-avx-mpx-avx512-pku-linux.dat: Likewise.
* regformats/i386/i386-avx-mpx-linux.dat: Likewise.
* regformats/i386/i386-linux.dat: Likewise.
* regformats/i386/i386-mmx-linux.dat: Likewise.
* regformats/i386/i386-mpx-linux.dat: Likewise.
* regformats/i386/i386.dat: Likewise.
* regformats/i386/x32-avx-avx512-linux.dat: Likewise.
* regformats/i386/x32-avx-linux.dat: Likewise.
* regformats/i386/x32-linux.dat: Likewise.
* regformats/tic6x-c62x-linux.dat: Likewise.
* regformats/tic6x-c64x-linux.dat: Likewise.
* regformats/tic6x-c64xp-linux.dat: Likewise.
* regformats/regdat.sh: Parse feature marker.
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gdb/ChangeLog:
Update copyright year range in all GDB files
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This patch prepares the current GDB port of the OpenRISC processor from
https://github.com/openrisc/binutils-gdb for upstream merging.
Testing has been done with a cgen sim provided in a separate patch. This
has been tested with 2 toolchains. GCC [1] 5.4.0 from the OpenRISC
project with Newlib [2] and GCC 5.4.0 with Musl [3] 1.1.4.
It supports or1knd (no delay slot target).
The default target is or1k (with delay slot).
You can change the target arch with:
(gdb) set architecture or1knd
The target architecture is assumed to be or1knd
[1] https://github.com/openrisc/or1k-gcc
[2] https://github.com/openrisc/newlib
[3] https://github.com/openrisc/musl-cross
gdb/doc/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Stefan Wallentowitz <stefan@wallentowitz.de>
Franck Jullien <franck.jullien@gmail.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* gdb.texinfo: Add OpenRISC documentation.
gdb/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Stefan Wallentowitz <stefan@wallentowitz.de>
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Franck Jullien <franck.jullien@gmail.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure.tgt: Add targets for or1k and or1knd.
* or1k-tdep.c: New file.
* or1k-tdep.h: New file.
* features/Makefile: Add or1k.xml to build.
* features/or1k.xml: New file.
* features/or1k-core.xml: New file.
* features/or1k.c: Generated.
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gdb/
* aarch64-tdep.c (_initialize_aarch64_tdep): Remove init.
* arch/aarch64.c (aarch64_create_target_description): Create
new target description.
* features/Makefile: Add new files.
* features/aarch64.c: Remove file.
* features/aarch64-core.c: New autogenerated file.
* features/aarch64-fpu.c: New autogenerated file.
* target-descriptions.c (maint_print_c_tdesc_cmd): Check for aarch64.
gdbserver/
* linux-aarch64-ipa.c (initialize_low_tracepoint): Remove init.
* linux-aarch64-low.c (initialize_low_arch): Remove init.
* linux-aarch64-tdesc.c (aarch64_linux_read_description): Add init.
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This patch changes tic6x target descriptions to be more flexible. Rebuild
tic6x-uclinux GDBserver with my x86 g++, and the unit test passes.
gdb:
2017-11-24 Yao Qi <yao.qi@linaro.org>
* arch/tic6x.c: New file.
* arch/tic6x.h: New file.
* features/Makefile (FEATURE_XMLFILES): Add tic6x-c6xp.xml,
tic6x-core.xml and tic6x-gp.xml.
* features/tic6x-c6xp.c: Generated.
* features/tic6x-core.c: Generated.
* features/tic6x-gp.c: Generated.
* target-descriptions.c (maint_print_c_tdesc_cmd): Match
"tic6x-".
gdb/gdbserver:
2017-11-24 Yao Qi <yao.qi@linaro.org>
* configure.srv: Set $srv_regobj for tic6x-linux.
* linux-tic6x-low.c: Include "arch/tic6x.h" and "tdesc.h".
(tic6x_read_description): Move some code to tic6x_arch_setup.
(tic6x_tdesc_test): New function.
(initialize_low_arch): Call selftests::register_test.
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tdesc_nios2_linux is not used at all. Remove features/nios2-linux.c,
and don't generate it anymore.
gdb:
2017-11-15 Yao Qi <yao.qi@linaro.org>
* features/Makefile (XMLTOC): Remove nios2-linux.xml.
* features/nios2-linux.c: Remove.
* nios2-linux-tdep.c (_initialize_nios2_linux_tdep): Don't call
initialize_tdesc_nios2_linux.
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features/*.c are generated from *.xml files, in order to get pre-defined
target descriptions, (for native debugging, for example). However, these
pre-generated tdesc_tic6x_* are not used in GDB at all. This patch removes
features/tic6x-*.c files.
gdb:
2017-10-16 Yao Qi <yao.qi@linaro.org>
* features/Makefile (XMLTOC): Remove tic6x-*.xml.
* features/tic6x-c62x.c: Remove.
* features/tic6x-c64x-linux.c: Remove.
* features/tic6x-c64x.c: Remove.
* features/tic6x-c64xp-linux.c: Remove.
* features/tic6x-c64xp.c: Remove.
* tic6x-linux-tdep.c (_initialize_tic6x_linux_tdep): Don't call
initialize_tdesc_tic6x_*_linux functions.
* tic6x-tdep.c (_initialize_tic6x_tdep): Don't call
initialize_tdesc_tic6x_* functions.
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tic6x-uclinux GDBserver uses linux target descriptions, instead of these
non-linux target descriptions. So we can remove these *.dat files.
gdb:
2017-10-16 Yao Qi <yao.qi@linaro.org>
* features/Makefile (WHICH): Remove tic6x-c64xp, tic6x-c64x
tic6x-c62x.
* regformats/tic6x-c62x.dat: Remove.
* regformats/tic6x-c64x.dat: Remove.
* regformats/tic6x-c64xp.dat: Remove.
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Nowadays, we have six tic6x expedite registers, which are duplicated.
tic6x-c64xp-expedite = A15,PC
tic6x-c64x-expedite = A15,PC
tic6x-c62x-expedite = A15,PC
tic6x-c64xp-linux-expedite = A15,PC
tic6x-c64x-linux-expedite = A15,PC
tic6x-c62x-linux-expedite = A15,PC
in features/Makefile, we have
echo "expedite:$(if $($*-expedite),$($*-expedite),$($(firstword $(subst -, ,$(notdir $*)))-expedite))" \
>> $(outdir)/$*.tmp
which means for a given bar/foo-baz.xml, we'll look for either
bar/foo-baz-expedite or foo-expedite. We can define only one generic
expedite register for all different ti6cx and s390x target descriptions.
Actually, we've done that for x86 target descriptions.
Re-run 'make GDB=/path/build/gdb all' to regenerate regformats/*.dat files,
and they are not changed.
gdb:
2017-10-13 Yao Qi <yao.qi@linaro.org>
* features/Makefile: Remove tic6x-*-expedite, add tic6x-expedite.
Remove s390x-*-expedite, add s390x-expedite.
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