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AgeCommit message (Expand)AuthorFilesLines
2018-06-01Add SVE register definesAlan Hayward1-1/+14
2018-05-31Function for reading the Aarch64 SVE vector lengthAlan Hayward1-0/+17
2018-05-31Add Aarch64 SVE target descriptionAlan Hayward2-4/+16
2018-05-22[PowerPC] Recognize isa205 in linux core filesPedro Franco de Carvalho2-2/+2
2018-05-22[PowerPC] Consolidate linux vector regset sizesPedro Franco de Carvalho1-0/+9
2018-05-22[PowerPC] Consolidate linux target description selectionPedro Franco de Carvalho3-0/+178
2018-05-04Fix "fall through" commentsTom Tromey1-1/+2
2018-02-27Explicitly specify common tdesc.h for use with aarch64.hAlan Hayward1-1/+1
2018-02-26Move arch/tdesc.h to common/tdesc.hAlan Hayward5-99/+4
2018-02-21Add "common-defs.h" include to files in arch/ subdir not yet including it.John Baldwin3-1/+3
2018-01-02Update copyright year range in all GDB filesJoel Brobecker18-18/+18
2017-12-05Split tdesc_type into multiple classesSimon Marchi1-11/+14
2017-11-24Use flexible target descriptors for aarch64Alan Hayward1-3/+15
2017-11-24Add aarch64_create_target_descriptionAlan Hayward2-0/+34
2017-11-24Change tic6x target descriptionsYao Qi2-0/+73
2017-10-25Add common AARCH64 REGNUM definesAlan Hayward1-0/+47
2017-09-05Convert the rest x86 target descriptionsYao Qi4-9/+15
2017-09-05Convert amd64-linux target descriptionsYao Qi2-0/+92
2017-09-05Share i386-linux target description between GDB and GDBserverYao Qi3-0/+97
2017-09-05Dynamically composite xml in reply to GDBYao Qi1-1/+3
2017-09-05[GDBserver] Centralize tdesc for i386-linuxYao Qi1-0/+80
2017-05-02Change return type of gdbarch_software_single_step to vector<CORE_ADDR>Simon Marchi2-48/+46
2017-03-27gdb: gdbserver: xtensa: make C0_NREGS availableMax Filippov1-0/+2
2017-01-01update copyright year range in GDB filesJoel Brobecker9-9/+9
2016-10-10Share enum arm_breakpoint_kindsYao Qi1-0/+8
2016-04-20Move ARM_CPSR_GREGNUM to arch/arm-linux.hYao Qi1-0/+3
2016-02-16Remove PC from syscall_next_pcYao Qi2-3/+3
2016-02-12[ARM] Software single step cross kernel helpersYao Qi1-4/+66
2016-02-12[ARM] Fixup PC in software single stepYao Qi4-0/+39
2016-01-26Remove argument pc in get_next_pcsYao Qi2-13/+14
2016-01-14[ARM] Make thumb2_breakpoint static againYao Qi2-6/+7
2016-01-13Read instruction with byte_order_for_codeYao Qi1-1/+2
2016-01-06Make {arm,thumb}_get_next_pcs_raw staticYao Qi2-38/+28
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker9-9/+9
2015-12-19Fix ARI warning in gdb/arch/arm-get-next-pcs.cJoel Brobecker1-1/+1
2015-12-18Support software single step on ARM in GDBServerAntoine Tremblay6-0/+1445
2015-12-18Share some ARM target dependent code from GDB with GDBServerAntoine Tremblay2-2/+94
2015-10-21Implement breakpoint_kind_from_pc and sw_breakpoint_from_kind for ARM in GDBS...Antoine Tremblay2-1/+44
2015-10-14Define enum out of structYao Qi1-6/+9
2015-10-12Rename emit_load_store to aarch64_emit_load_storeYao Qi2-12/+12
2015-10-12Rename emit_insn to aarch64_emit_insnYao Qi2-32/+33
2015-10-12Support displaced stepping in aarch64-linuxYao Qi2-0/+290
2015-10-12Move aarch64_relocate_instruction to arch/aarch64-insn.cYao Qi2-0/+143
2015-09-21Make aarch64_decode_adrp handle both ADR and ADRP instructionsPierre Langlois2-6/+26
2015-09-21Move instruction decoding into new arch/ directoryPierre Langlois2-0/+256
2015-08-21xtensa: implement NPTL helpersMax Filippov1-0/+46
2015-07-30Move ARM register numbers enum to arch/arm.hYao Qi1-0/+61
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