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2006-02-27bfd/doc/Carlos O'Donell4-5/+11
2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * Makefile.am: Add html target. * Makefile.in: Regenerate. bfd/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * po/Make-in: Add html target. binutils/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * po/Make-in: Add html target. gas/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * doc/Makefile.am: Add html target. * doc/Makefile.in: Regenerate. * po/Make-in: Add html target. gprof/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * po/Make-in: Add html target. ld/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * Makefile.am: Add html target. * Makefile.in: Regenerate. * po/Make-in: Add html target. opcodes/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * po/Make-in: Add html target. etc/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * Makefile.in: TEXI2HTML uses makeinfo. Define HTMLFILES. Add html targets. * configure.texi: Use ifnottex. Add alternative image format specifier as jpg. * standards.texi: Use ifnottex. intl/ 2006-10-14 Carlos O'Donell <carlos@codesourcery.com> * intl/Makefile.in: Add html target.
2006-02-27gas/H.J. Lu9-10/+330
2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (output_insn): Support Intel Merom New Instructions. * gas/config/tc-i386.h (CpuMNI): New. (CpuUnknownFlags): Add CpuMNI. gas/testsuite/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add merom and x86-64-merom. * gas/i386/merom.d: New file. * gas/i386/merom.s: Likewise. * gas/i386/x86-64-merom.d: Likewise. * gas/i386/x86-64-merom.s: Likewise. include/opcode/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Merom New Instructions. opcodes/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by Intel Merom New Instructions. (THREE_BYTE_0): Likewise. (THREE_BYTE_1): Likewise. (three_byte_table): Likewise. (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use THREE_BYTE_1 for entry 0x3a. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (print_insn): Handle 3-byte opcodes used by Intel Merom New Instructions.
2006-02-26missing from 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> commitNathan Sidwell2-0/+15
2006-02-252006-02-24 David S. Miller <davem@sunset.davemloft.net>David S. Miller12-2/+90
* gas/sparc/rdhpr.s: New test. * gas/sparc/rdhpr.d: New test. * gas/sparc/wrhpr.s: New test. * gas/sparc/wrhpr.d: New test. * gas/sparc/window.s: New test. * gas/sparc/window.d: New test. * gas/sparc/rdpr.s: Add case for reading %gl register. * gas/sparc/rdpr.d: Likewise. * gas/sparc/wrpr.s: Add case for writing %gl register. * gas/sparc/wrpr.d: Likewise. * gas/sparc/sparc.exp: Update for new tests.
2006-02-252006-02-24 David S. Miller <davem@sunset.davemloft.net>David S. Miller2-1/+56
* config/tc-sparc.c (priv_reg_table): Add entry for "gl". (hpriv_reg_table): New table for hyperprivileged registers. (sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged register encoding.
2006-02-24[include/elf]DJ Delorie3-8/+217
* m32c.h: Add relax relocs. [cpu] * m32c.cpu (RL_TYPE): New attribute, with macros. (Lab-8-24): Add RELAX. (unary-insn-defn-g, binary-arith-imm-dst-defn, binary-arith-imm4-dst-defn): Add 1ADDR attribute. (binary-arith-src-dst-defn): Add 2ADDR attribute. (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP attribute. (jsri16, jsri32): Add 1ADDR attribute. (jsr32.w, jsr32.a): Add JUMP attribute. [opcodes] * m32c-desc.c: Regenerate with linker relaxation attributes. * m32c-desc.h: Likewise. * m32c-dis.c: Likewise. * m32c-opc.c: Likewise. [gas] * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix. (tc_gen_reloc): Don't define. * config/tc-m32c.c (rl_for, relaxable): New convenience macros. (OPTION_LINKRELAX): New. (md_longopts): Add it. (m32c_relax): New. (md_parse_options): Set it. (md_assemble): Emit relaxation relocs as needed. (md_convert_frag): Emit relaxation relocs as needed. (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16. (m32c_apply_fix): New. (tc_gen_reloc): New. (m32c_force_relocation): Force out jump relocs when relaxing. (m32c_fix_adjustable): Return false if relaxing. [bfd] * elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs. (m32c_elf_relocate_section): Don't relocate them. (compare_reloc): New. (relax_reloc): Remove. (m32c_offset_for_reloc): New. (m16c_addr_encodings): New. (m16c_jmpaddr_encodings): New. (m32c_addr_encodings): New. (m32c_elf_relax_section): Relax jumps and address displacements. (m32c_elf_relax_delete_bytes): Adjust for internal syms. Fix up short jumps. * reloc.c: Add m32c relax relocs. * libbfd.h: Regenerate.
2006-02-24Check in correct version of previous patch.Paul Brook1-5/+5
2006-02-242006-02-24 Paul Brook <paul@codesourcery.com>Paul Brook10-57/+513
gas/ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7, arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables. (struct asm_barrier_opt): Define. (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables. (parse_psr): Accept V7M psr names. (parse_barrier): New function. (enum operand_parse_code): Add OP_oBARRIER. (parse_operands): Implement OP_oBARRIER. (do_barrier): New function. (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions. (do_t_cpsi): Add V7M restrictions. (do_t_mrs, do_t_msr): Validate V7M variants. (md_assemble): Check for NULL variants. (v7m_psrs, barrier_opt_names): New tables. (insns): Add V7 instructions. Mark V6 instructions absent from V7M. (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh. (arm_cpu_option_table): Add Cortex-M3, R4 and A8. (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m. (struct cpu_arch_ver_table): Define. (cpu_arch_ver): New. (aeabi_set_public_attributes): Use cpu_arch_ver. Set Tag_CPU_arch_profile. * doc/c-arm.texi: Document new cpu and arch options. gas/testsuite/ * gas/arm/thumb32.d: Fix expected msr and mrs output. * gas/arm/arch7.d: New test. * gas/arm/arch7.s: New test. * gas/arm/arch7m-bad.l: New test. * gas/arm/arch7m-bad.d: New test. * gas/arm/arch7m-bad.s: New test. include/opcode/ * arm.h: Add V7 feature bits. opcodes/ * arm-dis.c (arm_opcodes): Add V7 instructions. (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. (print_arm_address): New function. (print_insn_arm): Use it. Add 'P' and 'U' cases. (psr_name): New function. (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-23bfd/H.J. Lu7-3/+115
2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * cpu-ia64-opc.c (ins_immu5b): New. (ext_immu5b): Likewise. (elf64_ia64_operands): Add IMMU5b. gas/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b. gas/testsuite/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/opc-i.s: Add tests for tf. * gas/ia64/pseudo.s: Likewise. * gas/ia64/opc-i.d: Updated. * gas/ia64/pseudo.d: Likewise. include/opcode/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. opcodes/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64-opc-i.c (bXc): New. (mXc): Likewise. (OpX2TaTbYaXcC): Likewise. (TF). Likewise. (TFCM). Likewise. (ia64_opcodes_i): Add instructions for tf. * ia64-opc.h (IMMU5b): New. * ia64-asmtab.c: Regenerated.
2006-02-23Update copyright years.H.J. Lu2-1/+5
2006-02-23gas/H.J. Lu7-5/+33
2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (specify_resource): Add the rule 17 from SDM 2.2. gas/testsuite/ 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add check for vmsw.0. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1. * gas/ia64/opc-b.d: Updated. opcodes/ 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> * ia64-gen.c (lookup_regindex): Handle ".vm". (print_dependency_table): Handle '\"'. * ia64-ic.tbl: Updated from SDM 2.2. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated. * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
2006-02-222005-02-22 Paul Brook <paul@codesourcery.com>Paul Brook4-5/+14
gas/ * config/tc-arm.c (do_pld): Remove incorrect write to inst.instruction. (encode_thumb32_addr_mode): Use correct operand. gas/testsuite/ * gas/arm/thumb32.d: Fix expected pld opcode.
2006-02-212006-02-21 Paul Brook <paul@codesourcery.com>Paul Brook2-4/+8
* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
2006-02-17Add support for the Infineon XC16X.Nick Clifton58-11/+2898
2006-02-16 bfd:Nick Hudson2-1/+5
* config.bfd (mips*el-*-netbsd*, mips*-*-netbsd*): Use traditional MIPS ELF targets. gas: * configure.tgt: set emulation for mips-*-netbsd* ld: * configure.tgt (mips*el-*-netbsd*, mips*-*-netbsd*): Use the traditional target.
2006-02-14gas/Jakub Jelinek2-0/+8
* config.in: Rebuilt. binutils/ * config.in: Rebuilt.
2006-02-14 * config/tc-xtensa.c (xg_add_opcode_fix): Number operands startingBob Wilson2-21/+16
from 1, not 0, in error messages. (md_assemble): Simplify special-case check for ENTRY instructions. (tinsn_has_invalid_symbolic_operands): Do not include opcode and operand in error message.
2006-02-13gas:Joseph Myers2-1/+6
* configure.tgt (arm-*-linux-gnueabi*): Change to arm-*-linux-*eabi*. ld: * configure.tgt (arm*b-*-linux-gnueabi): Change to arm*b-*-linux-*eabi. (arm*-*-linux-gnueabi): Change to arm*-*-linux-*eabi.
2006-02-122006-02-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-0/+5
* gas/i386/x86-64-crx-suffix.d: Undo the last change.
2006-02-11gas/testsuite/H.J. Lu6-1/+71
2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix". * gas/i386/x86-64-crx-suffix.d: Minor update. * gas/i386/x86-64-drx-suffix.d: New file. * gas/i386/x86-64-drx.d: Likewise. * gas/i386/x86-64-drx.s: Likewise. opcodes/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "movZ" for debug register moves.
2006-02-11gas/testsuite/H.J. Lu5-0/+70
2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix". * gas/i386/x86-64-crx-suffix.d: New file. * gas/i386/x86-64-crx.d: Likewise. * gas/i386/x86-64-crx.s: Likewise. opcodes/ 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c ('Z'): Add a new macro. (dis386_twobyte): Use "movZ" for control register moves.
2006-02-10(check_range): Ensure that the sign bit of a 32-bit value is propagated intoNick Clifton2-0/+9
the upper bits of a 64-bit long.
2006-02-10Fix casts to allow for a 64-bit host.Nick Clifton2-7/+13
2006-02-10 * config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken forBob Wilson2-1/+6
each relaxation step.
2006-02-09Add missing ChangeLog entries.H.J. Lu1-0/+10
2006-02-092006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>Eric Botcazou4-35/+113
* configure.in (CHECK_DECLS): Add vsnprintf. * configure: Regenerate. * messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not include/declare here, but... * as.h: Move code detecting VARARGS idiom to the top. (errno.h, stdarg.h, varargs.h, va_list): ...here. (vsnprintf): Declare if not already declared.
2006-02-092006-02-08 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-4/+19
* as.c (close_output_file): New. (main): Register close_output_file with xatexit before dump_statistics. Don't call output_file_close.
2006-02-07 * bfd/archures.c (bfd_mach_mcf5200, bfd_mach_mcf5206e,Nathan Sidwell6-291/+655
bfd_mach_mcf5307, bfd_mach_mcf5407, bfd_mach_mcf528x, bfd_mach_mcfv4e, bfd_mach_mcf521x, bfd_mach_mcf5249, bfd_mach_mcf547x, bfd_mach_mcf548x): Remove. (bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_div, bfd_mach_mcf_isa_a_div_mac, bfd_mach_mcf_isa_a_div_emac, bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac, bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_aplus_usp, bfd_mach_mcf_isa_aplus_usp_mac, bfd_mach_mcf_isa_aplus_usp_emac, bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_usp_float, bfd_mach_mcf_isa_b_usp_float_mac, bfd_mach_mcf_isa_b_usp_float_emac): New. (bfd_default_scan): Update coldfire mapping. * bfd/bfd-in.h (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Declare. * bfd/bfd-in2.h: Rebuilt. * bfd/cpu-m68k.c (arch_info_struct): Add new coldfire machines, adjust legacy names. (m68k_arch_features): New. (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Define. * bfd/elf32-m68k.c (elf32_m68k_object_p): New. (elf32_m68k_merge_private_bfd_data): Merge the CF EF flags. (elf32_m68k_print_private_bfd_data): Print the CF EF flags. (elf_backend_object_p): Define. * bfd/ieee.c (ieee_write_processor): Update coldfire machines. * bfd/libbfd.h: Rebuilt. * gas/config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs, mcf5329_control_regs): New. (not_current_architecture, selected_arch, selected_cpu): New. (m68k_archs, m68k_extensions): New. (archs): Renamed to ... (m68k_cpus): ... here. Adjust. (n_arches): Remove. (md_pseudo_table): Add arch and cpu directives. (find_cf_chip, m68k_ip): Adjust table scanning. (no_68851, no_68881): Remove. (md_assemble): Lazily initialize. (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329. (md_init_after_args): Move functionality to m68k_init_arch. (mri_chip): Adjust table scanning. (md_parse_option): Reimplement 'm' processing to add -march & -mcpu options with saner parsing. (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension, m68k_init_arch): New. (s_m68k_cpu, s_m68k_arch): New. (md_show_usage): Adjust. (m68k_elf_final_processing): Set CF EF flags. * gas/config/tc-m68k.h (m68k_init_after_args): Remove. (tc_init_after_args): Remove. * gas/doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options. (M68k-Directives): Document .arch and .cpu directives. * gas/testsuite/gas/m68k/all.exp: Add arch-cpu-1 test. * gas/testsuite/gas/m68k/arch-cpu-1.[sd]: New. * include/elf/m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ... (EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here. (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New. * include/opcode/m68k.h (m68008, m68ec030, m68882): Remove. (m68k_mask): New. (cpu_m68k, cpu_cf): New. (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. * opcodes/m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. * binutils/readelf.c (get_machine_flags): Add logic for EF_M68K flags.
2006-02-05Cleanup of pseudo-ops for constants and new def24,def32 pseudo-ops on z80Arnold Metselaar4-72/+135
2006-02-022006-02-02 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+4
* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
2006-02-022005-02-02 Paul Brook <paul@codesourcery.com>Paul Brook5-1/+139
gas/ * config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND, T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR, T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB, T2_OPCODE_RSB): Define. (thumb32_negate_data_op): New function. (md_apply_fix): Use it. gas/testsuite/ * gas/arm/thumb2_invert.d: New test. * gas/arm/thumb2_invert.s: New test.
2006-01-31 * config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbolBob Wilson4-113/+70
fields. * config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field. * config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of subtracted symbols. (relaxation_requirements): Add pfinish_frag argument and use it to replace setting tinsn->record_fix fields. (xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements and vinsn_to_insnbuf. Remove references to record_fix and slot_sub_symbols fields. (xtensa_mark_narrow_branches): Delete unused code. (is_narrow_branch_guaranteed_in_range): Handle expr that is not just a symbol. (convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set record_fix fields. (tinsn_immed_from_frag): Remove code for handling slot_sub_symbols. (vinsn_to_insnbuf): Change use of record_fixup argument, replacing use of the record_fix field. Simplify error messages for unexpected symbolic operands. (set_expr_symbol_offset_diff): Delete.
2006-01-312006-01-31 Paul Brook <paul@codesourcery.com>Paul Brook5-2/+13
gas/ * config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL. gas/testsuite/ * gas/testsuite/gas/arm/iwmmxt-bad.s: Add check for bad register name. * gas/testsuite/gas/arm/iwmmxt-bad.l: Ditto.
2006-01-312006-01-31 Paul Brook <paul@codesourcery.com>Paul Brook2-296/+399
Richard Earnshaw <rearnsha@arm.com> * gas/config/tc-arm.c: Use arm_feature_set. (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none, arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1, fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2): New variables. (insns): Use them. (md_atof, opcode_select, opcode_select, md_assemble, md_assemble, md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch, arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes, s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU feature flags. (arm_legacy_option_table, arm_option_cpu_value_table): New types. (arm_opts): Move old cpu/arch options from here... (arm_legacy_opts): ... to here. (md_parse_option): Search arm_legacy_opts. (arm_cpus, arm_archs, arm_extensions, arm_fpus) (arm_float_abis, arm_eabis): Make const. * include/opcode/arm.h: Use ARM_CPU_FEATURE. (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. (arm_feature_set): Change to a structure. (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, ARM_FEATURE): New macros.
2006-01-26* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.Bob Wilson2-5/+9
2006-01-20 * config/bfin-parse.y (asm_1): Check value range for 16 bit immediateJie Zhang2-14/+20
in load immediate intruction.
2006-01-20 * config/bfin-parse.y (value_match): Use correct conversionJie Zhang2-3/+10
specifications in template string for __FILE__ and __LINE__. (binary): Ditto. (unary): Ditto.
2006-01-18include/elf/ChangeLog:Alexandre Oliva2-4/+51
Introduce TLS descriptors for i386 and x86_64. * common.h (DT_TLSDESC_GOT, DT_TLSDESC_PLT): New. * i386.h (R_386_TLS_GOTDESC, R_386_TLS_DESC_CALL, R_386_TLS_DESC): New. * x86-64.h (R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL, R_X86_64_TLSDESC): New. bfd/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * reloc.c (BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC, BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL): New. * libbfd.h, bfd-in2.h: Rebuilt. * elf32-i386.c (elf_howto_table): New relocations. (R_386_tls): Adjust. (elf_i386_reloc_type_lookup): Map new relocations. (GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros. (GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros. (struct elf_i386_link_hash_entry): Add tlsdesc_got field. (struct elf_i386_obj_tdata): Add local_tlsdesc_gotent field. (elf_i386_local_tlsdesc_gotent): New macro. (struct elf_i386_link_hash_table): Add sgotplt_jump_table_size. (elf_i386_compute_jump_table_size): New macro. (link_hash_newfunc): Initialize tlsdesc_got. (elf_i386_link_hash_table_create): Set sgotplt_jump_table_size. (elf_i386_tls_transition): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf_i386_check_relocs): Likewise. Allocate space for local_tlsdesc_gotent. (elf_i386_gc_sweep_hook): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (allocate_dynrelocs): Count function PLT relocations. Reserve space for TLS descriptors and relocations. (elf_i386_size_dynamic_sections): Reserve space for TLS descriptors and relocations. Set up sgotplt_jump_table_size. Don't zero reloc_count in srelplt. (elf_i386_always_size_sections): New. Set up _TLS_MODULE_BASE_. (elf_i386_relocate_section): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf_i386_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P. (elf_backend_always_size_sections): Define. * elf64-x86-64.c (x86_64_elf_howto): Add R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC, R_X86_64_TLSDESC_CALL. (R_X86_64_standard): Adjust. (x86_64_reloc_map): Map new relocs. (elf64_x86_64_rtype_to_howto): New, split out of... (elf64_x86_64_info_to_howto): ... this function, and... (elf64_x86_64_reloc_type_lookup): ... use it to map elf_reloc_val. (GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros. (GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros. (struct elf64_x86_64_link_hash_entry): Add tlsdesc_got field. (struct elf64_x86_64_obj_tdata): Add local_tlsdesc_gotent field. (elf64_x86_64_local_tlsdesc_gotent): New macro. (struct elf64_x86_64_link_hash_table): Add tlsdesc_plt, tlsdesc_got and sgotplt_jump_table_size fields. (elf64_x86_64_compute_jump_table_size): New macro. (link_hash_newfunc): Initialize tlsdesc_got. (elf64_x86_64_link_hash_table_create): Initialize new fields. (elf64_x86_64_tls_transition): Handle R_X86_64_GOTPC32_TLSDESC and R_X86_64_TLSDESC_CALL. (elf64_x86_64_check_relocs): Likewise. Allocate space for local_tlsdesc_gotent. (elf64_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPC32_TLSDESC and R_X86_64_TLSDESC_CALL. (allocate_dynrelocs): Count function PLT relocations. Reserve space for TLS descriptors and relocations. (elf64_x86_64_size_dynamic_sections): Reserve space for TLS descriptors and relocations. Set up sgotplt_jump_table_size, tlsdesc_plt and tlsdesc_got. Make room for them. Don't zero reloc_count in srelplt. Add dynamic entries for DT_TLSDESC_PLT and DT_TLSDESC_GOT. (elf64_x86_64_always_size_sections): New. Set up _TLS_MODULE_BASE_. (elf64_x86_64_relocate_section): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf64_x86_64_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P. (elf64_x86_64_finish_dynamic_sections): Set DT_TLSDESC_PLT and DT_TLSDESC_GOT. Set up TLS descriptor lazy resolver PLT entry. (elf_backend_always_size_sections): Define. binutils/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * readelf.c (get_dynamic_type): Handle DT_TLSDESC_GOT and DT_TLSDESC_PLT. gas/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL. (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the displacement bits. (build_modrm_byte): Set up zero modrm for TLS desc calls. (lex_got): Handle @tlsdesc and @tlscall. (md_apply_fix, tc_gen_reloc): Handle the new relocations. ld/testsuite/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * ld-i386/i386.exp: Run on x86_64-*-linux* and amd64-*-linux*. Add new tests. * ld-i386/pcrel16.d: Add -melf_i386. * ld-i386/pcrel8.d: Likewise. * ld-i386/tlsbindesc.dd: New. * ld-i386/tlsbindesc.rd: New. * ld-i386/tlsbindesc.s: New. * ld-i386/tlsbindesc.sd: New. * ld-i386/tlsbindesc.td: New. * ld-i386/tlsdesc.dd: New. * ld-i386/tlsdesc.rd: New. * ld-i386/tlsdesc.s: New. * ld-i386/tlsdesc.sd: New. * ld-i386/tlsdesc.td: New. * ld-i386/tlsgdesc.dd: New. * ld-i386/tlsgdesc.rd: New. * ld-i386/tlsgdesc.s: New. * ld-x86-64/x86-64.exp: Run new tests. * ld-x86-64/tlsbindesc.dd: New. * ld-x86-64/tlsbindesc.rd: New. * ld-x86-64/tlsbindesc.s: New. * ld-x86-64/tlsbindesc.sd: New. * ld-x86-64/tlsbindesc.td: New. * ld-x86-64/tlsdesc.dd: New. * ld-x86-64/tlsdesc.pd: New. * ld-x86-64/tlsdesc.rd: New. * ld-x86-64/tlsdesc.s: New. * ld-x86-64/tlsdesc.sd: New. * ld-x86-64/tlsdesc.td: New. * ld-x86-64/tlsgdesc.dd: New. * ld-x86-64/tlsgdesc.rd: New. * ld-x86-64/tlsgdesc.s: New.
2006-01-18fix typoArnold Metselaar2-3/+3
2006-01-18Add tests for instructions with offsets.Arnold Metselaar4-0/+55
2006-01-16split changelogsAlan Modra6-9784/+9816
2006-01-162006-01-16 Paul Brook <paul@codesourcery.com>Paul Brook4-0/+342
opcodes/ * m68k-opc.c(m68k_opcodes): Fix opcodes for ColdFire f?abss, f?add?, and f?sub? instructions. gas/testsuite/ * gas/m68k/all.exp: Add mcf-fpu. * gas/m68k/mcf-fpu.d: New file. * gas/m68k/mcf-fpu.s: New file.
2006-01-11Fixes for building on 64-bit hosts:Nick Clifton28-135/+247
* config/tc-avr.c (mod_index): New union to allow conversion between pointers and integers. (md_begin, avr_ldi_expression): Use it. * config/tc-i370.c (md_assemble): Add cast for argument to print statement. * config/tc-tic54x.c (subsym_substitute): Likewise. * config/tc-mn10200.c (md_assemble): Use a union to convert the opindex field of fr_cgen structure into a pointer so that it can be stored in a frag. * config/tc-mn10300.c (md_assemble): Likewise. * config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer types. * config/tc-v850.c: Replace uses of (int) casts with correct types. * gas/tic54x/address.d: Work with 64bit hosts. * gas/tic54x/addrfar.d: Likewise. * gas/tic54x/align.d: Likewise. * gas/tic54x/all-opcodes.d: Likewise. * gas/tic54x/asg.d: Likewise. * gas/tic54x/cons.d: Likewise. * gas/tic54x/consfar.d: Likewise. * gas/tic54x/extaddr.d: Likewise. * gas/tic54x/field.d: Likewise. * gas/tic54x/labels.d: Likewise. * gas/tic54x/loop.d: Likewise. * gas/tic54x/lp.d: Likewise. * gas/tic54x/macro.d: Likewise. * gas/tic54x/math.d: Likewise. * gas/tic54x/opcodes.d: Likewise. * gas/tic54x/sections.d: Likewise. * gas/tic54x/set.d: Likewise. * gas/tic54x/struct.d: Likewise. * gas/tic54x/subsym.d: Likewise.
2006-01-09gas/H.J. Lu12-1/+127
2006-01-09 H.J. Lu <hongjiu.lu@intel.com> PR gas/2117 * symbols.c (snapshot_symbol): Don't change a defined symbol. gas/testsuite/ 2006-01-09 H.J. Lu <hongjiu.lu@intel.com> PR gas/2117 * gas/ia64/ia64.exp: Add ltoff22x-2, ltoff22x-3, ltoff22x-4 and ltoff22x-5. * gas/ia64/ltoff22x-2.d: New file. * gas/ia64/ltoff22x-2.s: Likewise. * gas/ia64/ltoff22x-3.d: Likewise. * gas/ia64/ltoff22x-3.s: Likewise. * gas/ia64/ltoff22x-4.d: Likewise. * gas/ia64/ltoff22x-4.s: Likewise. * gas/ia64/ltoff22x-5.d: Likewise. * gas/ia64/ltoff22x-5.s: Likewise.
2006-01-03fix last-minute typoHans-Peter Nilsson1-1/+1
2006-01-03 PR gas/2101Hans-Peter Nilsson2-1/+9
* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as a local-label reference.
2006-01-03 PR gas/2101Hans-Peter Nilsson3-0/+37
* gas/mmix/hex2.s, gas/mmix/hex2.d: New test.
2005-12-30include:Bob Wilson3-172/+164
* xtensa-config.h (XCHAL_HAVE_WIDE_BRANCHES): New. gas: * config/tc-xtensa.c (op_placement_info_struct): Delete single, single_size, widest, and widest_size fields. Add narrowest_slot. (xg_emit_insn_to_buf): Remove fmt parameter and compute it here. Use xg_get_single_slot to find the slot. (finish_vinsn): Use emit_single_op instead of bundle_single_op. (bundle_single_op): Rename this to.... (bundle_tinsn): ...this function, which builds a vliw_insn but does not call finish_vinsn. (emit_single_op): Use bundle_tinsn instead of bundle_single_op. (relax_frag_immed): Get num_slots from cur_vinsn. (convert_frag_narrow): Update call to xg_emit_insn_to_buf. (convert_frag_immed): Likewise. Also, get num_slots from cur_vinsn. (init_op_placement_info_table): Set narrowest_slot field. Remove code for deleted fields. (xg_get_single_size): Return narrowest_size field, not single_size. (xg_get_single_format): Return narrowest field, not single. (xg_get_single_slot): New. (tinsn_to_insnbuf): Rewrite to use tinsn_to_slotbuf. * config/xtensa-relax.c (widen_spec_list): Add wide branch relaxations. (transition_applies): Check wide branch option availability.
2005-12-30 * config/tc-xtensa.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define.Bob Wilson2-0/+5
2005-12-29 * config/tc-xtensa.c (tinsn_to_slotbuf): Do not zero slotbuf.Bob Wilson2-2/+4
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