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2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess13-2/+125
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich3-34/+41
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich3-21/+45
2019-11-14x86: make AnySize an insn attributeJan Beulich2-1/+5
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich3-39/+45
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich10-0/+386
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-1/+5
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu4-44/+131
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu4-2/+94
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu5-2/+32
2019-11-12x86: fold EsSeg into IsStringJan Beulich2-34/+31
2019-11-12x86: eliminate ImmExt abuseJan Beulich12-352/+343
2019-11-12x86: introduce operand type "instance"Jan Beulich2-29/+55
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich3-0/+10
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu6-44/+69
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2-6/+13
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2-43/+53
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2-14/+20
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich3-9/+18
2019-11-08x86: introduce operand type "class"Jan Beulich2-41/+73
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson3-0/+20
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson6-5/+171
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson11-0/+330
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson5-0/+98
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson5-0/+96
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson3-29/+63
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson18-24/+807
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson10-0/+372
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson3-1/+8
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich10-55/+45
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich12-201/+80
2019-11-04x86: re-arrange process_operands()Jan Beulich2-57/+54
2019-10-31i386; Add .code16gcc fldenv testsH.J. Lu3-2/+20
2019-10-31Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu6-0/+68
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv6-44/+86
2019-10-30x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich8-0/+392
2019-10-30x86: drop stray WJan Beulich2-5/+11
2019-10-29Re: Optimise away eh_frame advance_loc 0Alan Modra2-1/+12
2019-10-26Add some missing casts to suppress implicit cast warningsJohn David Anglin2-5/+12
2019-10-26Optimise away eh_frame advance_loc 0Alan Modra3-4/+28
2019-10-25PR25125, relaxation chooses wrong branch sizeAlan Modra2-4/+13
2019-10-16qsort: tc-xtensa.c tidyAlan Modra2-22/+33
2019-10-15remove more xmalloc in bfdAlan Modra2-6/+12
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton3-0/+19
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel3-4/+5
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz17-4/+252
2019-10-07add missing ChangeLog entry for d241b91073Jan Beulich1-0/+13
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich9-12/+233
2019-09-24Arm: Fix out of range conditional branch (PR/24991)Tamar Christina5-7/+38
2019-09-24[ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni5-6/+81
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