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2016-06-24alpha-openbsd build failureAlan Modra2-2/+5
This target doesn't build, due to a missing gas/config/te-obsd.h file. It's been that way since the commit switching to elf, in 2002. https://lists.gnu.org/archive/html/bug-gnu-utils/2002-07/msg00128.html * configure.tgt (alpha-*-openbsd*): Use em=nbsd.
2016-06-23MIPS/GAS: Keep the original microMIPS symbol reference in branch relocsMaciej W. Rozycki8-13/+161
Keep original microMIPS symbols in references from branch relocations so that the ISA bit is retained and can be verified for validity in static link. No need to update WRT MIPS16 symbols because we keep them all anyway for other reasons. gas/ * config/tc-mips.c (b_reloc_p): New function. (mips_fix_adjustable): Also keep the original microMIPS symbol referred from branch relocations. * testsuite/gas/mips/branch-local-1.d: New test. * testsuite/gas/mips/branch-local-n32-1.d: New test. * testsuite/gas/mips/branch-local-n64-1.d: New test. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Update relocations. * testsuite/gas/mips/branch-local-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new cases.
2016-06-23[ARC] Misc minor edits/fixesGraham Markall2-36/+44
The code supporting -mspfp, -mdpfp, and -mfpuda options are in sections of code that are commented as being for backward compatibility only, and having no effect. However, they do have an effect, enabling the SPX, DPX, and DPA instruction subclasses respectively. This commit moves the code supporting these options away from the comments indicating that they are dummy options, and also fixes a small issue where -mnps400 had the additional effect of enabling SPX instructions. A couple of other minor edits (that make no functional change) are also included. gas/ChangeLog: * config/tc-arc.c (options, md_longopts, md_parse_option): Move -mspfp, -mdpfp and -mfpuda out of the sections for dummy options. Correct erroneous enabling of SPFP instructions when using -mnps400. include/ChangeLog: * opcode/arc.h: Make insn_class_t alphabetical again. opcodes/ChangeLog: * arc-opc.c: Correct description of availability of NPS400 features.
2016-06-23MIPS/GAS: Handle resolved R6 PC-relative relocations (ChangeLog)Maciej W. Rozycki1-0/+19
Add missing ChangeLog entry for commit 41947d9e38c4 ("MIPS/GAS: Handle resolved R6 PC-relative relocations").
2016-06-22Add support for yet some more new ISA 3.0 instructions.Peter Bergner3-0/+59
opcodes/ * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, xor3>: New mnemonics. <setb>: Change to a VX form instruction. (insert_sh6): Add support for rldixor. (extract_sh6): Likewise. gas/ * testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, xor3>: New tests. * testsuite/gas/ppc/power9.s: Likewise.
2016-06-22xtensa: include elf/xtensa.h in tc-xtensa.cTrevor Saunders2-4/+5
There's no reason to define these macros twice. gas/ChangeLog: 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c: Include elf/xtensa.h.
2016-06-21MIPS/GAS: Handle resolved R6 PC-relative relocationsMaciej W. Rozycki10-8/+427
Complement commit 7361da2c952e ("Add support for MIPS R6.") and fix internal errors like: foo.s: Assembler messages: foo.s: Internal error! Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028. Please report this bug. triggered by resolved R6 PC-relative relocations in sources containing R6 code fragments wrapped into ISA override blocks embedded within code otherwise assembled for an older ISA. gas/ * config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL> <BFD_RELOC_LO16_PCREL>: New switch cases. (md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>: Move switch cases along `BFD_RELOC_MIPS_JMP'. <BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2> <BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle the resolved case. * testsuite/gas/mips/pcrel-reloc-4.d: New test. * testsuite/gas/mips/pcrel-reloc-4-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-5.d: New test. * testsuite/gas/mips/pcrel-reloc-5-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-6.d: New test. * testsuite/gas/mips/pcrel-reloc-6.l: New list test. * testsuite/gas/mips/pcrel-reloc-4.s: New test source. * testsuite/gas/mips/pcrel-reloc-6.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21MIPS/GAS: Fix null pointer dereferences in R6 PC-relative relocation checksMaciej W. Rozycki2-2/+8
Avoid segmentation faults in alignment checks made in `md_apply_fix' for BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2 relocations caused by dereferencing `fixP->fx_addsy' which will be null if the relocation processed has been fully resolved. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3> <BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences via `fixP->fx_addsy'.
2016-06-21MIPS/GAS: Correct BFD_RELOC_MIPS_18_PCREL_S3 calculationMaciej W. Rozycki2-1/+21
The PC-relative R_MIPS_PC18_S3 relocation and consequently its BFD internal BFD_RELOC_MIPS_18_PCREL_S3 representation is calculated from the address of the aligned doubleword containing the location being relocated: (sign_extend(A) + S - (P & ~0x7)) >> 3 rather than the address of the location itself. Reflect this in calculations made by GAS so that the relocated field is set correctly if resolved by GAS, such as with local symbols in the same section which do not require relocations to be propagated to the link stage. gas/ * config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate relocation from the containing aligned doubleword. (tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the addend from the containing aligned doubleword.
2016-06-21MIPS/GAS: Use the module level ISA setting for R6 relaxationMaciej W. Rozycki10-2/+112
Use the module level ISA setting rather than the last ISA selected with a `.set' directive in the source file in determination as to whether to keep PC-relative relocations and then with the original symbol referred, for the purpose of R6 linker relaxation. This is so that with e.g. code like this: b foo .set mips32r2 ... it's the command line options or any `.module' directive that decides how to encode any relocation for `foo' rather than the presence of `.set mips32r2'. gas/ * config/tc-mips.c (mips_force_relocation): Use `file_mips_opts' rather than `mips_opts' for the R6 ISA check. (mips_fix_adjustable): Likewise. * testsuite/gas/mips/pcrel-reloc-1.d: New test. * testsuite/gas/mips/pcrel-reloc-1-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-2.d: New test. * testsuite/gas/mips/pcrel-reloc-2-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-3.d: New test. * testsuite/gas/mips/pcrel-reloc-3-r6.d: New test. * testsuite/gas/mips/pcrel-reloc-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall16-100/+194
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-20MIPS/GAS/testsuite: Uniquely identify MIPS64r6 testsMaciej W. Rozycki3-2/+7
gas/ * testsuite/gas/mips/r6-64-n32.d: Change the `name' tag. * testsuite/gas/mips/r6-64-n64.d: Likewise.
2016-06-20MIPS/GAS: Update comment on jump reloc conversionMaciej W. Rozycki2-2/+7
Complement commit 44d3da233815 ("MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA") and update and clarify the comment on jump reloc conversion. gas/ * config/tc-mips.c (mips_fix_adjustable): Update comment on jump reloc conversion.
2016-06-20Update the feature set for the Vulcan AArch64 cpu.Virendra Pathak2-2/+6
gas * config/tc-aarch64.c (aarch64_cpus): Update vulcan feature set.
2016-06-17opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.Jose E. Marchesi14-77/+467
This patch fixes and expands the definition of the read/write instructions for ancillary-state, privileged and hyperprivileged registers in opcodes. It also adds support for three new v9m hyperprivileged registers: %hmcdper, %hmcddfr and %hva_mask_nz. Finally, the patch expands existing tests (and adds several new ones) in order to cover all the read/write instructions in all its variants. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (rdasr): New macro. (wrasr): Likewise. (rdpr): Likewise. (wrpr): Likewise. (rdhpr): Likewise. (wrhpr): Likewise. (sparc_opcodes): Use the macros above to fix and expand the definition of read/write instructions from/to asr/privileged/hyperprivileged instructions. * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and %hva_mask_nz. Prefer softint_set and softint_clear over set_softint and clear_softint. (print_insn_sparc): Support %ver in Rd. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper, %hmcddfr and %hva_mask_nz. (sparc_ip): New handling of asr/privileged/hyperprivileged registers, adapted to the new form of the sparc opcodes table. * testsuite/gas/sparc/rdasr.s: New file. * testsuite/gas/sparc/rdasr.d: Likewise. * testsuite/gas/sparc/wrasr.s: Likewise. * testsuite/gas/sparc/wrasr.d: Likewise. * testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and wrasr tests. * testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged registers require it. * testsuite/gas/sparc/wrpr.s: Complete to cover all privileged registers and write instruction modalities. * testsuite/gas/sparc/wrpr.d: Likewise. * testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged registers. * testsuite/gas/sparc/rdhpr.d: Likewise. * testsuite/gas/sparc/wrhpr.s: Likewise. * testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17opcodes,gas: adjust sparc insns and make GAS aware of itJose E. Marchesi7-22/+75
This patch marks the SPARC instructions in the opcodes table with their proper opcode architectures, and makes the assembler aware of them. This allows the assembler to properly realize when a new instruction needs a higher architecture (after v9b) and to react accordingly emitting an error message or bumping the architecture. It also expands architecture mismatch tests to cover architectures higher than v9b, and fixes a couple of minor bugs in the GAS testsuite. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Adjust instructions opcode architecture according to the hardware capabilities they require. (sparc_priv_regs): New table. (sparc_hpriv_regs): Likewise. (sparc_asr_regs): Likewise. (v9anotv9m): Define. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): adjust the GAS architectures to use the right opcode architecture. (sparc_md_end): Handle v9{c,d,e,v,m}. (sparc_ip): Fix some comments. * testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this instruction, which is v9d. * testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1' instruction from the test, as %mwait is not readable. * testsuite/gas/sparc/mwait.d: Likewise. * testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e mismatch architecture errors. * testsuite/gas/sparc/mism-2.s: New file.
2016-06-17gas: sparc: fix collision of registers and pseudo-ops.Jose E. Marchesi2-141/+264
The current sparc assembler breaks when the name of an ancillary-state register, privileged register or hyperprivileged register has a %-pseudo-operation name as a prefix. For example, %hmcdper and %hm(), or %hintp and %hi(). This patch fixes it by introducing a new table `perc_table' (for %-table) that contains an entry for every %name supported by the assembler, other than the general registers. This table is used to detect name collisions when the assembler tries to detect a %-pseudo-op. This patch also fixes a related bug, making sure that v9a_asr_table and hpriv_reg_table are sorted in reverse lexicographic order, as otherwise the search code may fail. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (priv_reg_table): Use NULL instead of the empty string to mark the end of the array. (hpriv_reg_table): Likewise. (v9a_asr_table): Likewise. (cmp_reg_entry): Handle entries with NULL names. (F_POP_V9): Define. (F_POP_PCREL): Likewise. (F_POP_TLS_CALL): Likewise. (F_POP_POSTFIX): Likewise. (struct pop_entry): New type. (pop_table): New variable. (enum pop_entry_type): New type. (struct perc_entry): Likewise. (NUM_PERC_ENTRIES): Define. (perc_table): New variable. (cmp_perc_entry): New function. (md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize perc_table. (sparc_ip): Handle entries with NULL names in priv_reg_table, hpriv_reg_table and v9a_asr_table. Use perc_table to handle %-pseudo-ops.
2016-06-15Fix simple gas testsuite failures.Nick Clifton31-529/+626
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 reloc. gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the instruction size. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mn10200.c (md_assemble): Likewise. * config/tc-moxie.c (md_assemble): Likewise. * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of exception targets. Add alpha, hppa, microblaze and rl78 to list of exceptions. (forward): Add microblaze to list of exceptions. (fwdexp): Add alpha to list of exceptions. (redef2): Add arm-epoc-pe and rl78 to list of exceptions. (redef3): Add rl78 and x86_64 cygwin to list of exceptions. (do_930509a): Alpha sort list of exception targets. Add h8300 and mn10200 to list of exceptions. (align2): Expect to fail for nds32. (cond): Add alpha and rl78 to list of exceptions. * testsuite/gas/all/none.d: Skip for ft32 and hppa. * testsuite/gas/all/string.d: Skip for tic4x. * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff target does not support ELF. * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH tests for sh-pe and sh-rtemscoff targets. * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to list of exceptions. (type): Run the noifunc version for alpha-freebsd and visium. * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, mn10200 or moxie targets. * testsuite/gas/ft32/insn.d: Update expected disassembly. * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin targets. * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for mcore and rx targets. * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, rl78 and vax. (purge): Expect to fail on the ns32k and vax. * testsuite/gas/nds32/alu-2.d: Update expected disassembly. * testsuite/gas/nds32/ls.d: Likewise. * testsuite/gas/nds32/sys-reg.d: Likewise. * testsuite/gas/nds32/usr-spe-reg.d: Likewise. * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. * testsuite/gas/pe/section-align-3.d: Likewise. * testsuite/gas/pe/section-exclude.d: Likewise. * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required data has been seen. * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow for variations in whitespace. * testsuite/gas/tilepro/t_constants.d: Pass once all the required data has been seen. * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. Installs a 32-bit value without generating warnings on 64-bit hosts. Use the new macro to replace the .word directives. opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer constants to match expected behaviour. (nds32_parse_opcode): Likewise. Also for whitespace.
2016-06-15opcodes/arc: Fix extract for some add_s instructionsAndrew Burgess3-0/+17
The extract function used for some arc_s instructions was not implemented, and instead always returned 0. Fixed in this commit. opcodes/ChangeLog: * arc-opc.c (extract_rhv1): Extract value from insn. gas/ChangeLog: * testsuite/gas/arc/add_s.d: New file. * testsuite/gas/arc/add_s.s: New file.
2016-06-14opcode/gas: Fix incorrect dates on ChangeLog entriesGraham Markall1-3/+3
When committing three recent patches incorrect dates were left on the ChangeLog entries in gas/ChangeLog and opcodes/ChangeLog. Fixed in this commit.
2016-06-14[ARC] Add ldbit for npsGraham Markall3-0/+71
This commit adds the ldbit instruction for the NPS-400. The ldbit instruction uses the same encoding as the ld instruction, but sets the ZZ field to 11 (which is a reserved setting), and sets the AA field to 1 or 2 for the x2 and x4 flags respectively.
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall3-35/+142
With the exception of ldbit, this commit adds implementations of all DPI instructions for the NPS-400. These instructions are: - hash / hash.p[0-3] - tr - utf8 - e4by - addf
2016-06-14[ARC] Add arithmetic and logic instructions for npsGraham Markall3-0/+289
This commit completes the implementation of arithmetic and logic instructions for the NPS-400. These instructions are: - calcbsd / calcbxd - calckey / calcxkey - mxb / imxb - addl, subl, orl, andl, xorl - andab / orab - lbdsize - bdlen - csms, csma, cbba - zncv - hofs
2016-06-14Fix compile time warning building gas for the NDS32 with gcc v6.1.1Nick Clifton2-1/+6
gas * config/tc-nds32.c (nds32_get_align): Avoid left shifting a signed constant.
2016-06-13MIPS/GAS: Don't convert RELA JALR relocations on R6Maciej W. Rozycki13-5/+342
Revert an inadvertent change to make RELA JALR relocations section-relative on MIPS R6 targets made with commit 7361da2c952e ("Add support for MIPS R6."). There is no need to make this a special case and the comment introduced with the said change clearly indicates this was not intended. gas/ * config/tc-mips.c (mips_fix_adjustable): Don't convert RELA JALR relocations on R6. * testsuite/gas/mips/jal-svr4pic-local.d: New test. * testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test. * testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test. * testsuite/gas/mips/jal-svr4pic-local-n32.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New test. * testsuite/gas/mips/jal-svr4pic-local-n64.d: New test. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New test. * testsuite/gas/mips/jal-svr4pic-local.s: New test source. * testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-13Accept vulcan as a cpu name for the AArch64 port of GAS.Virendra Pathak3-0/+10
* config/tc-aarch64.c (aarch64_cpus): Add Broadcom Vulcan. * doc/c-aarch64.texi: Document that vulcan is a valid processor name.
2016-06-13Fix compile time warning messages building with gcc v6.1.1Nick Clifton6-4/+24
etc * texi2pod.pl: Escape curly braces, whilst searching for keyword strong. gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets that are not supported. * config/tc-arc.c (md_apply_fix): Avoid left shifting a signed constant. * config/tc-cr16.c (check_range): Likewise. * config/tc-nios2.c (nios2_check_overflow): Likewise.
2016-06-09[AARCH64][GAS] Fix two -Wstack-usage warnings.Renlin Li2-7/+10
Warning triggerd by gcc 5 with -O0 flag. error: stack usage might be unbounded [-Werror=stack-usage=] gas/ 2016-06-08 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (print_operands): Substitute size. (output_operand_error_record): Likewise.
2016-06-07PowerPC VLEAlan Modra2-18/+24
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab5-4/+76
This patch adds the architecture extension "+ras" to enable RAS support. It is enabled by default for -march=armv8.2-a and available but disabled by default for armv8-a and armv8.1-a. gas/ * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras. (arm_ext_ras): Renamed from arm_ext_v8_2. (insns): Update for arm_ext_v8_2 renaming. (arm_extensions): Add "ras". * doc/c-arm.texi (ARM Options): Add an entry for "ras". * testsuite/gas/arm/armv8-a+ras.d: New. * testsuite/gas/arm/armv8_2-a.d: Add explicit command line options. include/ * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding entries. (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. opcodes/ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with ARM_EXT_RAS in relevant entries.
2016-06-05fixup another old style function definitionTrevor Saunders2-2/+5
gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * itbl-parse.y (yyerror): Use modern argument declaration style.
2016-06-05sh{,64}: make arg type enumTrevor Saunders3-9/+23
The values are always members of the enum, except the two places -1 is assigned only to playcate -Wuninitialized because gcc isn't or at least didn't used to be smart enough to figure out its only used if it was set. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sh.c (parse_reg): Change type of mode argument to sh_arg_type. (get_operand): Adjust. (insert): Change type of how to bfd_reloc_code_real_type. (insert4): Likewise. * config/tc-sh64.c (shmedia_get_operand): Adjust. (shmedia_parse_reg): Change type of mode to shmedia_arg_type.
2016-06-05nds32: constify ptr_argTrevor Saunders2-1/+6
it points to the result of strchr on a const char *, so it aliases something that is const. Further its only passed to a function that expects a const char *, so there's no reason for it to not be const. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg const char *.
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner7-1/+127
opcodes/ PR binutils/20196 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable opcodes for E6500. gas/ PR binutils/20196 * gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx, stbcx., sthcx., stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/e6500.d: Likewise. * gas/testsuite/gas/ppc/power8.s: Likewise. * gas/testsuite/gas/ppc/power8.d: Likewise. * gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu6-24/+83
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode. AMD64 supports indirect branches with 16-bit address via the data size prefix while the data size prefix is ignored by Intel64. gas/ PR binutis/18386 * testsuite/gas/i386/i386.exp: Run x86-64-branch-4. * testsuite/gas/i386/x86-64-branch.d: Updated. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. * testsuite/gas/i386/x86-64-branch-4.l: New file. * testsuite/gas/i386/x86-64-branch-4.s: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. (indir_v_mode): New. Add comments for '&'. (reg_table): Replace "{T|}" with "{&|}" on call and jmp. (putop): Handle '&'. (intel_operand_size): Handle indir_v_mode. (OP_E_register): Likewise. * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 64-bit indirect call/jmp for AMD64. * i386-tbl.h: Regenerated
2016-06-03[AArch64][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry. * doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
2016-06-03[ARM][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry. * doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
2016-06-02Allow ARC Linux targets that do not use uclibc.Vineet Gupta2-1/+5
bfd * config.bfd: Replace -uclibc with *. gas * configure.tgt: Replace -uclibc with *. ld * configure.tgt: Replace -uclibc with *.
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess4-69/+276
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-01ns32k: remove dupplicate definition of input_line_pointerTrevor Saunders2-1/+4
gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ns32k.c: Remove definition of input_line_pointer.
2016-06-01avr: replace sentinal with iteration from 0 to ARRAY_SIZETrevor Saunders2-4/+8
This seems a little easier to understand than using a sentinal, and will hopefully let the compiler optimize the loop better. It also has the effect that we stop initializing a field of the sentinal that is an enum with zero. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-avr.c (avr_parse_cons_expression): Replace iteration to sentinal with iteration to array size.
2016-06-01xtensa: typedef enums when defining themTrevor Saunders2-10/+11
I think this is the more typical way to do this. Its also slightly shorter and less repeditive. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/xtensa-relax.h: Move typedefs of enums to the enums definition.
2016-06-01ns32k: use XOBNEW in another spotTrevor Saunders2-1/+6
gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ns32k.c (bit_fix_new): Replace obstack-alloc with XOBNEW macro.
2016-06-01Add support for some variants of the ARC nps400 rflt instruction.Graham Markall3-50/+62
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with operands of types a,b,u6, 0,b,u6, and 0,b,limm. * testsuite/gas/arc/nps-400-1.d: Likewise. opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and 0,b,limm to the rflt instruction.
2016-05-29Add missing ChangeLog entriesH.J. Lu1-0/+15
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu7-0/+801
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq, .noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2. * testsuite/gas/i386/noavx512-1.l: New file. * testsuite/gas/i386/noavx512-1.s: Likewise. * testsuite/gas/i386/noavx512-2.l: Likewise. * testsuite/gas/i386/noavx512-2.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. * i386-init.h: Regenerated.
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu17-10/+482
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C, FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives to x86 assembler. TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_arch): Add 687. (cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. (parse_real_register): Check cpuregmmx instead of cpummx for MMX register. Check cpuregxmm instead of cpusse for XMM register. Check cpuregymm instead of cpuavx for YMM register. Check cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register. * doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. * testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx. * testsuite/gas/i386/arch-10.d (as): Likewise. * testsuite/gas/i386/arch-11.s: Add ".arch .mmx". * testsuite/gas/i386/i386.exp: Pass mmx to assembler for arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3 and noavx-4. * testsuite/gas/i386/no87-3.l: New file. * testsuite/gas/i386/no87-3.s: Likewise. * testsuite/gas/i386/noavx-3.l: Likewise. * testsuite/gas/i386/noavx-3.s: Likewise. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-4.s: Likewise. * testsuite/gas/i386/nosse-4.l: Likewise. * testsuite/gas/i386/nosse-4.s: Likewise. * testsuite/gas/i386/nosse-5.d: Likewise. * testsuite/gas/i386/nosse-5.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and CpuRegMask for AVX512. (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM and CpuRegMask. (set_bitfield_from_cpu_flag_init): New function. (set_bitfield): Remove const on f. Call set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. * i386-opc.h (CpuRegMMX): New. (CpuRegXMM): Likewise. (CpuRegYMM): Likewise. (CpuRegZMM): Likewise. (CpuRegMask): Likewise. (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm and cpuregmask. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2-7/+11
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel syntax. Since cpu_flags isn't sorted by position, we need to check the whole cpu_flags array for the maximum position when verifying CpuMax. gas/ PR gas/20154 * config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor cpuintel64. (match_template): Check Intel64/AMD64 ISA. opcodes/ PR gas/20154 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. (opcode_modifiers): Add AMD64 and Intel64. (main): Properly verify CpuMax. * i386-opc.h (CpuAMD64): Removed. (CpuIntel64): Likewise. (CpuMax): Set to CpuNo64. (i386_cpu_flags): Remove cpuamd64 and cpuintel64. (AMD64): New. (Intel64): Likewise. (i386_opcode_modifier): Add amd64 and intel64. (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 on call and jmp. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu2-8/+19
CpuMax should be CpuIntel64, not CpuNo64. i386-gen.c is updated to verify that CpuMax is correct. X86 assembler is updated to properly set cpuamd64 and cpuintel64. gas/ PR gas/20154 * config/tc-i386.c (intel64): New. (cpu_flags_match): Set cpuamd64 and cpuintel64. (md_parse_option): Set intel64 instead of cpuamd64 and cpuintel64. opcodes/ PR gas/20154 * i386-gen.c (main): Fail if CpuMax is incorrect. * i386-opc.h (CpuMax): Set to CpuIntel64. * i386-tbl.h: Regenerated.
2016-05-27Don't clear cpu64 nor cpuno64H.J. Lu2-2/+5
No need to clear cpu64 nor cpuno64 since they will be cleared by cpu_flags_and. * config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor cpuno64.
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