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2022-12-12x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich4-5/+26
In commit 1212781b35c9 ("ix86: allow HLE store of accumulator to absolute address") I was wrong to exclude 64-bit code. Dropping the check also leads to better diagnostics in 64-bit code ("MOV", after all, isn't invalid with "XRELEASE"). While there also limit the amount of further checks done: The operand type checks that were there were effectively redundant with other ones anyway, plus it's quite fine to also have "xrelease mov <disp>, %eax" look for the next MOV template (in fact again also improving diagnostics).
2022-12-12ix86: don't recognize/derive Q suffix in the common caseJan Beulich14-51/+140
Have its use, except where actually legitimate, result in the same "only supported in 64-bit mode" diagnostic as emitted for other 64-bit only insns. Also suppress deriving of the suffix in Intel mode except in the legitimate cases. This in exchange allows dropping the respective code from match_template(). To maintain reasonable diagnostics (in particular to avoid "`mov' is only supported in 64-bit mode" on the SIMD forms of MOVQ) we need to defer parse_insn()'s emitting of errors unrelated to prefix parsing. Utilize i.error just like match_template() does. Oddly enough despite gcc's preference towards FILDQ and FIST{,T}Q we had no testcase whatsoever for these. Therefore such tests are being added. Note that the removed line in the x86-64-lfence-load testcase was redundant with the exact same one a few lines up.
2022-12-12x86: re-work insn/suffix recognitionJan Beulich7-163/+195
Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
2022-12-12x86: constify parse_insn()'s inputJan Beulich1-7/+8
The function doesn't alter its input buffer: Reflect this in its prototype. To avoid using any kind of cast, simply calculate the update of "line" from the function's input and output.
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ↵Jan Beulich6-52/+52
and LSL" This reverts the disassembler parts of 859aa2c86dc9 ("x86: Allow 16-bit register source for LAR and LSL"), adjusting testcases as necessary. That change was itself a partial revert of c9f5b96bdab0 ("x86: correct handling of LAR and LSL"), without actually saying so. While the earlier commit was properly agreed upon, the partial revert was not, and hence should not have been committed. This is even more so that the revert part of that change wasn't even necessary to address PR gas/29844.
2022-12-12gas/codeview: avoid "shadowing" of glibc function nameJan Beulich1-4/+4
While not "index" this time, old enough glibc also has an (unguarded) declaration of fileno() in stdio.h, which triggers a "shadows a global declaration" warning with our choice of warning level and with at least some gcc versions.
2022-12-12x86: generate template sets data at build timeJan Beulich1-15/+10
Speed up gas startup by avoiding runtime allocation of the instances of type "templates". At the same time cut the memory requirement to just very little over half (not even accounting for any overhead notes_alloc() may incur) by reusing the "end" slot of a preceding entry for the "start" slot of the subsequent one.
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich1-22/+11
Now that the table is local to gas, ARRAY_SIZE() can be used to determine the end of the table. Re-arrange the processing loop in md_begin() accordingly, at the same time folding the two calls to notes_alloc() into just one.
2022-12-12x86: add generated tables dependency check to gasJan Beulich2-0/+22
As requested by H.J., just for the sake of people potentially building in gas/ alone, add a check that the generated files in opcodes/ are actually up-to-date. Personally I think this should at best be a warning, but I can see how this may not be easily noticable among other make output (depending in particular on the verbosity level).
2022-12-12x86: break gas dependency on libopcodesJan Beulich2-2/+2
gas doesn't use anything from libopcodes anymore - suppress linking in that library.
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich1-0/+2
Unlike many other architectures, x86 does not share an opcode table between assembly and disassembly. Any consumer of libopcodes would only ever access one of the two. Since gas is the only consumer of the assembly data, move it there. While doing so mark respective entities "static" in i386-gen (we may want to do away with i386_regtab_size altogether). This also shrinks the number of relocations to be processed for libopcodes.so by about 30%.
2022-12-09gas: sframe: fine tune the fragment fixup for SFrame func infoIndu Bhagat2-21/+68
SFrame function info is an unsigned 8-bit field comprising of the following (from LSB to MSB): - 4-bits: FRE type - 1-bit: FRE start address encoding - 3-bits: Unused At the moment, the most-significat 4-bits are zero (The FRE start address encoding of SFRAME_FDE_TYPE_PCINC has a value of zero, and the upper 3-bits are unused). So the current implementation works without this patch. To be precise, however, the fragment fixup logic is meant to fixup only the least-significant 4-bits (i.e., only the FRE type needs to be updated according to the function size). This patch makes the gas implementation a bit more resilient: In the future, when the format does evolve to make use of the currently unused 3-bits in various ways, the values in those 3-bits can be propagated unchanged while the fragment fixup continues to update the lowermost 4-bits to indicate the selected FRE type. ChangeLog: * gas/gen-sframe.c (create_func_info_exp): New definition. (output_sframe_funcdesc): Call create_func_info_exp. * gas/sframe-opt.c (sframe_estimate_size_before_relax): The associated fragment uses O_modulus now. (sframe_convert_frag): Adjust the fragment fixup code according to the new composite exp.
2022-12-09sframe: gas: libsframe: define constants and remove magic numbersIndu Bhagat1-6/+6
Define constants in sframe.h for the various limits associated with the range of offsets that can be encoded in the start address of an SFrame FRE. E.g., sframe_frame_row_entry_addr1 is used when start address offset can be encoded as 1-byte unsigned value. Update the code in gas to use these defined constants as it checks for these limits, and remove the usage of magic numbers. ChangeLog: * gas/sframe-opt.c (sframe_estimate_size_before_relax): (sframe_convert_frag): Do not use magic numbers. * libsframe/sframe.c (sframe_calc_fre_type): Likewise. include/ChangeLog: * sframe.h (SFRAME_FRE_TYPE_ADDR1_LIMIT): New constant. (SFRAME_FRE_TYPE_ADDR2_LIMIT): Likewise. (SFRAME_FRE_TYPE_ADDR4_LIMIT): Likewise.
2022-12-07PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner5-0/+52
opcodes/ * ppc-opc.c (XOL): New define. (XOL_MASK): Likewise. (powerpc_opcodes): Add subfus, subfus., subwus, subwus., subdus, subdus. gas/ * testsuite/gas/ppc/rfc02655.s: New test. * testsuite/gas/ppc/rfc02655.d: Likewise * testsuite/gas/ppc/future-raw.s: Likewise. * testsuite/gas/ppc/future-raw.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run them.
2022-12-07PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner3-0/+30
opcodes/ * ppc-opc.c (PPCVSXF): New define. (powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl, stxvrll, stxvprl, stxvprl. gas/ * testsuite/gas/ppc/rfc02656.s: New test. * testsuite/gas/ppc/rfc02656.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
2022-12-07gas compress_debug tidyAlan Modra1-22/+14
* write.c (compress_debug): Don't set up "ob" until after seginfo NULL check. Simplify SEC_CONTENTS test. Localise variables. Use bfd_debug_name_to_zdebug.
2022-12-07Compression tidy and fixesAlan Modra1-8/+9
Tidies: - Move stuff from bfd-in.h and libbfd.c to compress.c - Delete COMPRESS_DEBUG from enum compressed_debug_section_type - Move compress_debug field out of link_info to ld_config. Fixes: - Correct test in bfd_convert_section_setup to use obfd flags, not ibfd. - Apply bfd_applicable_file_flags to compression bfd flags added by gas and ld to the output bfd. bfd/ * bfd-in.h (enum compressed_debug_section_type), (struct compressed_type_tuple), (bfd_get_compression_algorithm), (bfd_get_compression_algorithm_name), * libbfd.c (compressed_debug_section_names), (bfd_get_compression_algorithm), (bfd_get_compression_algorithm_name): Move.. * compress.c: ..to here, deleting COMPRESS_DEBUG from enum compressed_debug_section_type. (bfd_convert_section_setup): Test obfd flags not ibfd for compression flags. * elf.c (elf_fake_sections): Replace link_info->compress_debug test with abfd->flags test. * bfd-in2.h: Regenerate. binutils/ * objcopy.c (copy_file): Tidy setting of bfd compress flags. Expand comment. gas/ * write.c (compress_debug): Test bfd compress flags rather than flag_compress_debug. (write_object_file): Apply bfd_applicable_file_flags to compress debug flags added to output bfd. include/ * bfdlink.h (struct bfd_link_info): Delete compress_debug. ld/ * ld.h (ld_config_type): Add compress_debug. * emultempl/elf.em: Replace references to link_info.compress_debug with config.compress_debug. * lexsup.c (elf_static_list_options): Likewise. * ldmain.c (main): Likewise. Apply bfd_applicable_file_flags to compress debug flags added to output bfd.
2022-12-05gas: add Dwarf line number test for .macro expansionsJan Beulich3-0/+56
Before fiddling with the code let's put in place a test covering what PR/gas 16908 aimed at.
2022-12-05gas: squash (some) .linefile from listingsJan Beulich1-1/+4
Not so long ago we started to insert these artificially when expanding certain macro-like constructs; zap them as cluttering what actually results from user input.
2022-12-05gas: avoid inserting extra newline in buffer_and_nest()Jan Beulich1-3/+3
In "-alm" listings I've noticed an odd blank line following the inserted .linefile one. This results from the explicit NL inserted being redundant with the one left in place from the original input line by all respective callers. Note that we need to compensate for the removed line by bumping the directive argument (which in turn is decremented again in s_linefile() before calling new_logical_line_flags(), and I have to confess that when putting together the original change I was a little puzzled by the imbalance of increments/decrements, but then I forgot to actually go look for the cause). While there also switch to sb_add_string() instead of effectively open- coding it to some degree.
2022-12-05opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess13-514/+514
While working on disassembler styling for MIPS, I noticed that undefined instructions are printed by the disassembler as raw number with no assembler directive prefix (e.g. without .word or .short). I think adding something like .word, or .short, helps to make it clearer the size of the value that is being displayed, and is inline with what many of the other libopcode disassemblers do. In this commit I've added the .word and .short directives, and updated all the tests that I spotted that failed as a result.
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu10-8/+170
Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
2022-12-02x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich1-47/+81
With the general use of C99 there's no need anymore to have i386-gen produce these. For more frequently used ones introduce local #define-s, while others are simply spelled out directly. While doing this move some static constants into more narrow scopes. Note that as a "side effect" this corrects type_names[]'es imm8s entry.
2022-12-02x86: simplify and slightly correct XCHG vs NOP checkingJan Beulich1-5/+3
For one, because of CheckRegSize, there's no need to check the size of both (register) operands. And then in process_suffix() check opcode space rather than the (potentially ambiguous) extension opcode.
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-4/+8
Leverage the C (commutative) attribute to also reduce the number of XCHG and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for XCHG) forms can also be folded into a single template each, utilizing D.
2022-12-01x86: rework of match_template()'s suffix checkingJan Beulich1-27/+5
(Ab)using i386_opcode_modifier for this has been overkill, as the logic doesn't really require the full structure. With the removal of LONG_DOUBLE_MNEM_SUFFIX and No_ldSuf there's no good reason at all anymore to pull out such a loop invariant: We're dealing a check of a bit in the loop for a simple comparison. Do the original compares inside the loop, thus also making it easier to understand what is actually being checked.
2022-12-01x86: drop No_ldSufJan Beulich1-2/+0
With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf anymore.
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-24/+24
With the removal of its use for FPU insns the suffix is now finally properly misnamed. Drop its use altogether, replacing it by a separate boolean instead.
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-7/+7
As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.)
2022-11-30x86/Intel: adjustment to restricted suffix derivationJan Beulich1-3/+8
In "x86/Intel: restrict suffix derivation" I think I screwed up slightly, bringing a piece of code out of sync with its comment, and resulting in a suffix potentially being derived when one isn't needed.
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich1-14/+17
At the very least a comment in process_operands() is stale. Beyond that there are effectively two options: 1) It is possible that FADDP and FMULP were mistakenly not marked as being in need of dealing with the compiler anomaly, and hence the respective templates weren't removed at the time when they should have been. 2) It is also possible that there are indeed uses known beyond compiler generated output for these two commutative opcodes, and hence the templates need to stay. To be on the safe side assume 2: Update the comment and fold the templates into their "normal" ones (utilizing D), adjusting consuming code accordingly. For FMULP also add a comment paralleling a similar one FADDP has.
2022-11-30x86: drop FloatRJan Beulich1-4/+8
There are just 4 templates using it, which can be easily identified by other means, as D is set only on a very limited number of FPU templates. Also move the respective conditional out of the code path taken by all "reverse match" insns (it probably should have been this way already before, to avoid the one conditional in the common case). With this the templates which had FloatR dropped no longer differ from their AT&T syntax + mnemonic counterparts - the only difference is now which of the two would be recognized. For this, however, we don't need two templates - we can simply arrange the condition for setting Opcode_FloatR accordingly.
2022-11-30x86: extend FPU test coverage for AT&T / Intel mnemonic differencesJan Beulich5-0/+44
Before touching the templates, let's ensure we actually cover things: For one FSUB{,R} and FDIV{,R} would better be tested with operands in both possible orders. And then -mmnemonic=intel wasn't tested at all.
2022-11-28xtensa: allow dynamic configurationMax Filippov3-20/+3
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields of a structure returned from the xtensa_get_config_v<x> function call. Define that structure and fill it with default parameter values specified in the include/xtensa-config.h. Define reusable function xtensa_load_config that tries to load configuration and return an address of an exported object from it. Define functions xtensa_get_config_v{1,2} that use xtensa_load_config to get structures xtensa_config_v{1,2}, either dynamically configured or the default. bfd/ * Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Append xtensa-dynconfig.c. * Makefile.in: Regenerate. * configure: Regenerate. * configure.ac (xtensa_elf32_be_vec, xtensa_elf32_le_vec): Add xtensa-dynconfig.lo to the tb. * elf32-xtensa.c (xtensa-config.h): Replace #include with xtensa-dynconfig.h. (XSHAL_ABI, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove definitions. * xtensa-dynconfig.c: New file. * xtensa-isa.c (xtensa-dynconfig.h): New #include. (xtensa_get_modules): New function. (xtensa_isa_init): Call xtensa_get_modules instead of taking address of global xtensa_modules. gas/ * config/tc-xtensa.c (xtensa-config.h): Replace #include with xtensa-dynconfig.h. (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0, XTENSA_MARCH_EARLIEST): Remove definitions. * config/tc-xtensa.h (xtensa-config.h): Replace #include with xtensa-dynconfig.h. * config/xtensa-relax.c (xtensa-config.h): Replace #include with xtensa-dynconfig.h. (XCHAL_HAVE_WIDE_BRANCHES): Remove definition. include/ * xtensa-dynconfig.h: New file. ld/ * emultempl/xtensaelf.em (xtensa-config.h): Replace #include with xtensa-dynconfig.h. (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove definitions.
2022-11-28regen gas/Makefile.inAlan Modra1-8/+9
2022-11-28RISC-V: Better support for long instructions (tests)Tsukasa OI4-1/+48
This commit tests both (assembler and disassembler) fixes of "Better support for long instructions". gas/ChangeLog: * testsuite/gas/riscv/insn.s: Add testcases such that big number handling is required and should be disassembled as long ".byte" sequence with correct instruction bits. * testsuite/gas/riscv/insn.d: Likewise. * testsuite/gas/riscv/insn-na.d: Likewise. * testsuite/gas/riscv/insn-dwarf.d: Likewise.
2022-11-28RISC-V: Better support for long instructions (assembler)Tsukasa OI1-9/+32
Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length and 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing. To resolve these problems, this commit: 1. Handles bignum (and its encodings) precisely and 2. Incorporates long opcode handling into regular instruction handling. This commit will be tested on the separate commit. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected maximum length.
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner12-0/+882
This commit adds the AIA extensions (Smaia and Ssaia) CSRs. bfd/ChangeLog: * elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list of known standard extensions. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): (riscv_csr_address): Add CSR classes for Smaia/Ssaia. * testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MISELECT): New CSR macro. (CSR_MIREG): Likewise. (CSR_MTOPEI): Likewise. (CSR_MTOPI): Likewise. (CSR_MVIEN): Likewise. (CSR_MVIP): Likewise. (CSR_MIDELEGH): Likewise. (CSR_MIEH): Likewise. (CSR_MVIENH): Likewise. (CSR_MVIPH): Likewise. (CSR_MIPH): Likewise. (CSR_SISELECT): Likewise. (CSR_SIREG): Likewise. (CSR_STOPEI): Likewise. (CSR_STOPI): Likewise. (CSR_SIEH): Likewise. (CSR_SIPH): Likewise. (CSR_HVIEN): Likewise. (CSR_HVICTL): Likewise. (CSR_HVIPRIO1): Likewise. (CSR_HVIPRIO2): Likewise. (CSR_VSISELECT): Likewise. (CSR_VSIREG): Likewise. (CSR_VSTOPEI): Likewise. (CSR_VSTOPI): Likewise. (CSR_HIDELEGH): Likewise. (CSR_HVIENH): Likewise. (CSR_HVIPH): Likewise. (CSR_HVIPRIO1H): Likewise. (CSR_HVIPRIO2H): Likewise. (CSR_VSIEH): Likewise. (CSR_VSIPH): Likewise. (DECLARE_CSR): Add CSRs for Smaia and Ssaia. Changes for v3: - Imply ssaia for smaia - Imply zicsr for ssaia (and transitively smaia) - Move hypervisor CSRs to Ssaia+H - Rebase on upstream/master Changes for v2: - Add hypervisor and VS CSRs - Fix whitespace issue Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-24Impport libiberty commit: 885b6660c17f from gcc mainline. Fix gas's ↵Nick Clifton2-0/+2
acinclude.m4 to stop a potwntial configure time warning message.
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich3-9/+65
First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
2022-11-24x86: correct handling of LAR and LSLJan Beulich6-20/+66
Both uniformly only ever take 16-bit memory operands while at the same time requiring matching (in size) register operands, which then also should disassemble that way. This in particular requires splitting each of the templates for the assembler and separating decode of the register and memory forms in the disassembler.
2022-11-24gas: Disable --gcodeview on PE targets with no O_secrelMark Harmstone2-5/+5
2022-11-23regen POTFILES.inAlan Modra1-0/+2
2022-11-23gas: Add --gcodeview optionMark Harmstone11-4/+1018
2022-11-22gas/sframe: avoid "shadowing" of glibc function nameJan Beulich1-11/+11
Once again: Old enough glibc has an (unguarded) declaration of index() in string.h, which triggers a "shadows a global declaration" warning with our choice of wanring level and with at least some gcc versions.
2022-11-21Fix ARM and AArch64 assembler tests to work in a multi-arch environment.Nick Clifton5-4/+14
PR 29764 gas * testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m option passed to objdump. * testsuite/gas/arm/cpu-cortex-a77.d: Likewise. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to the -m option passed to objdump. * testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise. bfd * cpu-arm.c (scan): Accept machine names prefixed with "arm:". * cpu-aarch64.c (scan): Accept machine names prefixed with "aarch64:". bin * doc/binutils.texi (objdump): Note that the -m option supports the <architecture>:<machine> syntax.
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI9-105/+166
This commit adds 'Ssstateen' extension, which is a supervisor-visible view of the 'Smstateen' extension. It means, this extension implements sstateen* and hstateen* CSRs of the 'Smstateen' extension. Note that 'Smstateen' extension itself is unchanged but due to implementation simplicity, it is implemented so that 'Smstateen' implies 'Ssstateen' (just like 'M' implies 'Zmmul'). This is based on the latest version of RISC-V Profiles (version 0.9-draft, Frozen): <https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Update implication rules. (riscv_supported_std_s_ext) Add 'Ssstateen' extension. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Rename CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_... Add CSR_CLASS_SSSTATEEN. (riscv_csr_address): Support new/renamed CSR classes. * testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment. * testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to error messages. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that supervisor/hypervisor part of 'Smstateen' CSRs are accessible from 'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested in ssstateen-csr.d. include/ChangeLog: * opcode/riscv-opc.h: Update DECLARE_CSR declarations with new CSR classes.
2022-11-18GAS fix alignment for aarch64-peZac Walker1-0/+3
Fixes issue where various values of '.align' causes writing of COFF files to fail. Specific to the aarch64-pe target.
2022-11-18Regen potfiles for sframeAlan Modra1-0/+3
2022-11-17[gas, aarch64]: fix build breakage for aarch64-peIndu Bhagat1-19/+22
SFrame is supported for ELF only. Keep the definitions and declarations guarded with OBJ_ELF consistently. ChangeLog: * gas/config/tc-aarch64.h: Guard SFrame related definitions with OBJ_ELF.
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