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2011-09-22binutils/Tristan Gingold2-0/+6
2011-09-22 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.22. gas/ 2011-09-22 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.22. ld/ 2011-09-22 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.22.
2011-09-22Add new sparc options to control instruction availability.David S. Miller5-26/+170
gas/ * config/tc-sparc.c (hwcap_allowed): New. (struct sparc_arch): New field 'hwcap_allowed' containing a bitmask of F_FOO flags which are enabled by the particular arch setting. Add new options that provide explicit access to new instructions. (md_parse_option): Only bump max_architecture if the requested one is larger, or this is the first explicit request. (get_hwcap_name): New function. (sparc_ip): Validate that hwcaps used by an instruction have actually been enabled. * doc/c-sparc.texi: Document new sparc options.
2011-09-21Fix sparc testcases when building with 64-bit default.David S. Miller5-6/+11
gas/testsuite/ * gas/sparc/imm-plus-rreg.d: Fix address regex for 64-bit. * gas/sparc/save-args.d: Likewise. * gas/sparc/ticc-imm-reg.d: Likewise, add -32 to options. * gas/sparc/v8-movwr-imm.d: Likewise.
2011-09-21Annotate sparc objects with cpu hardware capabilities used.David S. Miller5-3/+71
bfd/ * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New. * elfxx-sparc.h: Declare it. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. binutils/ * readelf.c (display_sparc_hwcaps): New. (display_sparc_gnu_attribute): New. (process_sparc_specific): New. (process_arch_specific): When EM_SPARC, EM_SPARC32PLUS, or EM_SPARCV9 invoke process_sparc_specific. gas/ * config/tc-sparc.c (hwcap_seen): New bitmask, defined when not TE_SOLARIS. (sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from sparc_opcode->flags of instruction into hwcap_seen. (sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if hwcap_seen is non-zero and not TE_SOLARIS. gas/testsuite/ * gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic. * gas/sparc/hpcvis3.d: Likewise. include/elf/ * sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute. (ELF_SPARC_HWCAP_*): New HWCAPS bitmask values. include/opcode/ * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. opcodes/ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag bits. Fix "fchksm16" mnemonic.
2011-09-192011-09-19 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-1/+6
* config/tc-alpha.c (insert_operand): Call as_bad_value_out_of_range instead of as_warn_out_of_range.
2011-09-10Add PR markersAndreas Schwab1-0/+1
2011-09-08opcodes/David S. Miller4-0/+22
* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd' This has been reported as being accepted by the Sun assmebler. gas/testsuite/ * gas/sparc/save-args.[sd]: New test. * gas/sparc/sparc.exp: Run new test.
2011-09-08opcodes/David S. Miller6-0/+130
The changes below bring 'mov' and 'ticc' instructions into line with the V8 SPARC Architecture Manual. * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'. * sparc-opc.c (sparc_opcodes): Add alias entries for 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs'; 'mov regrs2,%wim' and 'mov regrs2,%tbr'. * sparc-opc.c (sparc_opcodes): Move/Change entries for 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim' and 'mov imm,%tbr'. * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above mov aliases. gas/testsuite/ * gas/sparc/ticc-imm-reg.[sd]: New test. * gas/sparc/v8-movwr-imm.[sd]: New test. * gas/sparc/sparc.exp: Run new tests.
2011-09-08gas/David S. Miller6-1/+34
* config/tc-sparc.c (sparc_ip): Handle 'i' + r<0..31> in addition to 'i' + [goli]<0..7>. gas/testsuite/ * gas/sparc/imm-plus-rreg.[sd]: New test. * gas/sparc/sparc.exp: Run new test.
2011-09-08opcodes/David S. Miller3-2/+7
* sparc-opc.c (pdistn): Destination is integer not float register. gas/testsuite/ * gas/sparc/hpcvis3.s: Correct pdistn test. * gas/sparc/hpcvis3.d: Likewise.
2011-09-08 * cgen.c (gas_cgen_pcrel_r_type): New function.Nick Clifton3-7/+39
(gas_cgen_tc_gen_reloc): Check for GAS_CGEN_PCREL_R_TYPE. * cgen.h (gas_cgen_pcrel_r_type): Declare.
2011-09-08gas/Richard Sandiford6-1/+67
PR gas/13167 * dwarf2dbg.c (dwarf2_flush_pending_lines): Use symbol_temp_new_now. gas/testsuite/ PR gas/13167 * gas/ia64/pr13167.d, gas/ia64/pr13167.s: New test. * gas/ia64/ia64.exp: Run it.
2011-09-07* gas/testsuite/gas/m68k/all.exp: Run "mode5" test also with -mcpu=5200.Andreas Schwab4-0/+11
* gas/testsuite/gas/m68k/mode5.s: Add moveml testcases. * gas/testsuite/gas/m68k/mode5.d: Update. * opcodes/m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
2011-09-05gas/Richard Sandiford8-13/+233
PR gas/13024 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables. (dwarf2_gen_line_info_1): Delete. (dwarf2_push_line, dwarf2_flush_pending_lines): New functions. (dwarf2_gen_line_info, dwarf2_emit_label): Use them. (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines. (dwarf2_directive_loc): Push previous .locs instead of generating them immediately. gas/testsuite/ * gas/mips/loc-swap-2.s, gas/mips/loc-swap-2.d, gas/mips/micromips@loc-swap-2.d, gas/mips/mips16@loc-swap-2.d: New test. * gas/mips/mips.exp: Run it.
2011-08-26Updated Spanish translations.Nick Clifton2-2784/+2789
2011-08-262011-08-26 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-17/+21
* config/tc-alpha.c (s_alpha_linkage): Simplify. Add comments.
2011-08-262011-08-26 Tristan Gingold <gingold@adacore.com>Tristan Gingold1-2/+4
* config/tc-alpha.c (add_to_link_pool): Improve comment. (s_alpha_fp_save): Fix indentation.
2011-08-19Update AVX tests.H.J. Lu13-48/+353
2011-08-19 Sergey A. Guriev <sergeya.a.guriev@intel.com> * gas/i386/avx-gather-intel.d: Added missing vpgather tests. * gas/i386/avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/avx-intel.d: Added missing vpinsrd and removed duplicated vpinsrb instructions. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * gas/i386/ilp32/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise.
2011-08-19 * doc/as.texinfo: Include c-xstormy16.texi.Nick Clifton2-0/+11
2011-08-18 * write.c (resolve_reloc_expr_symbols): Convert local symbolsAlan Modra2-39/+90
on relocs to section+offset. (get_frag_for_reloc): New function. (write_relocs): Merge sort fixup relocs with those from .reloc directives.
2011-08-10 * config/tc-mips.c (can_swap_branch_p): Update the comment onMaciej W. Rozycki2-3/+7
MIPS16 fixups.
2011-08-10 * gas/mips/micromips@mips5.d: Rename to...Maciej W. Rozycki6-4/+16
* gas/mips/micromips@mips5-fp.d: ... this. * gas/mips/mips5.d: Rename to... * gas/mips/mips5-fp.d: ... this. * gas/mips/mips5.l: Rename to... * gas/mips/mips5-fp.l: ... this. * gas/mips/mips5.s: Rename to... * gas/mips/mips5-fp.s: ... this. * gas/mips/mips.exp: Update accordingly.
2011-08-10 * gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"Maciej W. Rozycki2-12/+22
architecture properties adding them to "mips3", "mips4", "mips5" and "mips32r2" architectures. Use the new properties for the "24k-triple-stores-1", "24k-triple-stores-3", "mips4-fp", "mips5" and "alnv_ps-swap" tests.
2011-08-09 * config/tc-mips.c (mips_cpu_info_table): Add "m14k" andMaciej W. Rozycki3-0/+12
"m14kc". * doc/c-mips.texi (MIPS architecture options): Add "m14k" and "m14kc" to the list of -march options.
2011-08-09 gas/Maciej W. Rozycki9-6/+450
* config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-08-09 include/opcode/Maciej W. Rozycki8-71/+101
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. (INSN2_READ_GPR_MMN): Likewise. (INSN2_READ_FPR_D): Change the bit used. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. (INSN2_COND_BRANCH): Likewise. (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. (INSN2_MOD_GPR_MN): Likewise. gas/ * config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG, INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode register use checks. (gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN, INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use checks. (gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB, INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP opcode register use checks. (can_swap_branch_p): Enable microMIPS branch swapping. (append_insn): Likewise. gas/testsuite/ * gas/mips/micromips.d: Update according to changes to enable microMIPS branch swapping. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. opcodes/ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. (WR_s): Update macro. (micromips_opcodes): Update register use flags of: "addiu", "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", "swm" and "xor" instructions.
2011-08-09 * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Remove forced 16-bitMaciej W. Rozycki2-44/+63
branch size information. (RELAX_MICROMIPS_U16BIT): Remove macro. (RELAX_MICROMIPS_UNCOND): Adjust accordingly. (RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise. (RELAX_MICROMIPS_RELAX32): Likewise. (RELAX_MICROMIPS_TOOFAR16): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR16): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise. (RELAX_MICROMIPS_TOOFAR32): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR32): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise. (append_insn): Always check forced_insn_length for microMIPS relaxation. Adjust code for the removal of RELAX_MICROMIPS_U16BIT. (mips_ip) <'D', 'E'>: If forced_insn_length, then emit the relocation straight away. (relaxed_micromips_16bit_branch_length): Adjust code for the removal of RELAX_MICROMIPS_U16BIT.
2011-08-082011-08-08 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-1/+265
* config/obj-macho.c (obj_mach_o_section): New function. (struct known_section): New type. (known_sections): Declare. (obj_mach_o_known_section): New function. (obj_mach_o_common_parse): Ditto. (obj_mach_o_comm): Ditto. (obj_mach_o_subsections_via_symbols): Ditto. (mach_o_pseudo_table): Add new pseudos.
2011-08-07 * dw2gencfi.c (all_fde_data): Export.Richard Henderson4-1/+19
* dw2gencfi.h (all_fde_data): Declare. * config/tc-alpha.c (alpha_elf_md_end): Don't convert legacy unwind info to cfi unwind info if the user already has supplied some.
2011-08-06gas/Richard Sandiford2-28/+34
* config/tc-mips.c (emit_nop): Delete. (get_delay_slot_nop): New function. (nops_for_insn_or_target): Use it. (append_insn): Likewise. When avoiding hazards, call add_fixed_insn and insert_into_history directly.
2011-08-06gas/Richard Sandiford2-45/+71
* config/tc-mips.c (delayed_branch_p, compact_branch_p) (uncond_branch_p, branch_likely_p): New functions. (insns_between, nops_for_insn_or_target, append_insn) (macro_start): Use them. (get_append_method): Likewise. Remove redundant test.
2011-08-05include/opcode/David S. Miller6-0/+201
* sparc.h: Document new format codes '4', '5', and '('. (OPF_LOW4, RS3): New macros. opcodes/ * sparc-dis.c (v9a_ast_reg_names): Add "cps". (X_RS3): New macro. (print_insn_sparc): Handle '4', '5', and '(' format codes. Accept %asr numbers below 28. * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 instructions. gas/ * config/tc-sparc.c (v9a_asr_table): Add "cps". (sparc_ip): Handle '4', '5' and '(' format codes. gas/testsuite * gas/sparc/hpcvis3.d: New test. * gas/sparc/hpcvis3.s: New test source. * gas/sparc/sparc.exp: Run new test.
2011-08-05Update gas/i386/x86-64-branch.d to support win64.H.J. Lu2-5/+10
2011-08-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.d: Pass -dw to objdump and support win64.
2011-08-04Call bfd_cache_close_all on errorH.J. Lu3-3/+13
2011-08-04 H.J. Lu <hongjiu.lu@intel.com> PR gas/13056 * output-file.c (output_file_close): Call bfd_cache_close_all on error. * write.c (write_object_file): Revert the last change.
2011-08-04Add a testcase for group error.H.J. Lu5-0/+24
2011-08-04 H.J. Lu <hongjiu.lu@intel.com> * gas/elf/bad-group.d: New. * gas/elf/bad-group.err: Likewise. * gas/elf/bad-group.s: Likewise. * gas/elf/elf.exp: Run bad-group.
2011-08-04 * write.c (write_object_file): Call set_symtab even if we hadAlan Modra2-1/+7
errors.
2011-08-042011-08-04 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-3/+4
* config/obj-elf.c (obj_elf_section): Do not free name.
2011-08-03 * config/tc-arm.c (do_t_strexbh): New.Nick Clifton8-3/+114
(insns): Update accordingly. * gas/arm/strex-bad-t.d: New testcase. * gas/arm/strex-bad-t.s: Likewise. * gas/arm/strex-bad-t.l: Likewise. * gas/arm/strex-t.s: Likewise. * gas/arm/strex-t.d: Likewise.
2011-08-01Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.H.J. Lu10-93/+56
bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check.
2011-08-01Add Disp32S to 64bit call.H.J. Lu4-0/+19
gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * gas/i386/x86-64-branch.s: Add tests for direct branch. * gas/i386/x86-64-branch.d: Updated. * gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR gas/13046 * i386-opc.tbl: Add Disp32S to 64bit call. * i386-tbl.h: Regenerated.
2011-08-01 PR ld/12974Nick Clifton2-2/+27
* config/tc-arm.c (literal_pool): Add locs field. (add_to_lit_pool): Initialise the locs entry for the new literal. (s_ltorg): Generate a DWARF2 line number entry for each emitted literal pool entry.
2011-08-012011-08-01 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-11/+15
* write.c (write_relocs): Fix -Wshadow in DEBUG3 and DEBUG4.
2011-08-012011-08-01 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-18/+29
* frags.c (frag_grow): Simplify the code.
2011-07-30gas/Richard Sandiford2-1/+4
* config/tc-mips.c (nops_for_vr4130): Revert previous commit.
2011-07-29 bfd/Maciej W. Rozycki2-111/+84
* elfxx-mips.c: Adjust comments throughout. (mips_elf_relax_delete_bytes): Reshape code. (_bfd_mips_elf_relax_section): Remove check for R_MICROMIPS_GPREL16 relocations. Reshape code. gas/ * config/tc-mips.c: Adjust comments throughout. (reglist_lookup): Reshape code. (jmp_reloc_p, jalr_reloc_p): Reformat. (got16_reloc_p, hi16_reloc_p, lo16_reloc_p): Handle microMIPS relocations. (gpr_mod_mask): Remove unused variable. (gpr_read_mask, gpr_write_mask): Reshape code. (fpr_read_mask, fpr_write_mask): Likewise. (nops_for_vr4130): Ensure non-microMIPS mode. (can_swap_branch_p): Correct pinfo2 reference. Reshape code. (append_insn): Skip Loongson 2F workaround in MIPS16 mode. Use the outermost operator of a compound relocation to determines the relocated field. Fix formatting. (md_convert_frag): Reshape code. include/opcode/ * mips.h: Clarify the description of microMIPS instruction manipulation macros. (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
2011-07-29 * gas/elf/warn-2.s: Add other types of NOP insn.Nick Clifton2-6/+21
2011-07-292011-07-29 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-32/+36
* frags.c (frag_var_init): New function. (frag_var): Call frag_var_init to initialize. (frag_variant): Ditto.
2011-07-28 * dwarf2dbg.c (out_debug_line): Ignore non-normal segments, with aNick Clifton6-1/+44
warning. * doc/as.texinfo (Offset): Document .offset directive. testsuite/ * gas/elf/warn-2.s: New.
2011-07-272011-07-27 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-26/+24
* frags.c (frag_grow): Revert previous patch.
2011-07-26 * config/tc-rx.c (md_convert_frag): Fix encoding of beq.aNick Clifton4-3/+13
synthetic instruction. * gas/rx/r-bcc.d: Update expected disassembly of synthetic beq.a instruction.
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