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2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus6-1/+169
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus6-1/+51
2020-11-16arm: Add support for Cortex-A78CPrzemyslaw Wirkus4-0/+16
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov36-392/+430
2020-11-13gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm modeAndre Vieira3-2/+16
2020-11-12MSP430: gas: Ignore -md option required for GCC backward compatibilityJozef Lawrynowicz5-0/+30
2020-11-12Fix up changelog entry of previous deltaNick Clifton1-2/+4
2020-11-12Stop Gas from generating line info or address ranges for sections that do not...Nick Clifton6-17/+54
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus2-1/+5
2020-11-09Revert delta accidentally applied with commit 9372689d72f902c8bae90536acc4747...Nick Clifton1-24/+0
2020-11-09gas: improve reproducibility for stabs debugging data formatDenys Zagorui2-1/+7
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson4-0/+36
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus4-1/+71
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus5-34/+271
2020-11-09Fix regexp for development.expAndreas Schwab3-2/+7
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu18-47/+211
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus11-141/+85
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus7-0/+76
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+90
2020-11-03gas: fix symbol value calculation for versioned symbol aliasesChristian Eggers2-1/+7
2020-10-30x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE markerH.J. Lu16-56/+86
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus3-2/+67
2020-10-29aarch64: Fix DSB instruction 'missing immediate expression' errorsPrzemyslaw Wirkus3-1/+34
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus7-0/+57
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus3-1/+75
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus7-0/+107
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus3-2/+3
2020-10-26gas: Clear all auto-assigned file slotsH.J. Lu5-11/+89
2020-10-26Update gas/ChangeLog of last commitLifang Xia1-0/+5
2020-10-26C-SKY: Fix the literal dump of big vector constant.Cooper Qu1-1/+2
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu3-2/+7
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu2-2/+5
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu3-27/+47
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili3-32/+38
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus6-2/+425
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus6-1/+70
2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni5-1/+864
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert3-3522/+3347
2020-10-21aarch64: Add testcase for HCR_EL2 system registerPrzemyslaw Wirkus2-0/+11
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian18-3/+263
2020-10-17gas: Add a -gdwarf-5 debug_line test with .s fileH.J. Lu4-0/+62
2020-10-17gas: Replace dwarf5-line-2.S with dwarf5-line-3.SH.J. Lu3-4/+12
2020-10-17gas: Always use as_where for preprocessed assembly codesH.J. Lu7-19/+155
2020-10-16gas: Reuse the input file entry in the file tableH.J. Lu5-19/+84
2020-10-16Enhancement for avx-vnni patchCui,Lili11-28/+41
2020-10-14x86: Support Intel AVX VNNIH.J. Lu9-2/+171
2020-10-14x86: Add support for Intel HRESET instructionLili Cui8-1/+50
2020-10-14x86: Support Intel UINTRLili Cui7-1/+46
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2-24/+29
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu2-30/+53
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