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2021-06-24gas: update csect alignment for PPC prefixed instructions on XCOFFClément Chigot2-0/+10
Power10 prefixed instructions must not cross 64-byte boundaries. This is already handled. However, on XCOFF, the csect must be updated to match the new alignment. * config/tc-ppc.c (md_assemble): Update ppc_current_csect alignment when finding prefixed instructions.
2021-06-22picojava assembler and disassembler fixesAlan Modra4-173/+159
Commit 54758c3e398d made changes to the picojava support based on https://sourceware.org/pipermail/binutils/2005-November/045136.html An update from picojava to picojava II, I think. Unfortunately the patch neglected any changes to the gas testsuite, resulting in "FAIL: pj" since that date. This patch makes a few relatively simple changes to cure the regression. gas/ * config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs. * testsuite/gas/pj/ops.s: Update jsr, ret, getstatic, putstatic, getfield, putfield, invokevirtual, invokespecial, invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete version 1 picojava opcodes. * testsuite/gas/pj/ops.d: Match expected output. opcodes/ * pj-dis.c (print_insn_pj): Don't print trailing tab. Do print separator for pcrel insns.
2021-06-19ubsan errors when 32-bit bfdAlan Modra2-3/+7
A shift count exceeding the size of the value is undefined behaviour, and so is negating a signed LONG_MIN. * config/tc-z80.c (signed_overflow, unsigned_overflow): Avoid UB.
2021-06-19ppc raw test failure when 32-bit bfdAlan Modra3-2/+7
The test contained an expression that can't be evaluated unless expressions are 64-bit. * testsuite/gas/ppc/raw.s: Use 0 as pli constant. * testsuite/gas/ppc/raw.d: Update to suit.
2021-06-18gas: fold symbol table entries generated for .startof.() / .sizeof.()Jan Beulich5-8/+71
When the same such construct is used multiple times in a source file, there's still no need to emit a separate symbol each time. Under the assumption that there won't be many of these, use a simple array lookup method to record previously used symbols.
2021-06-17Fix an assertion failure in the AArch64 assembler triggered by incorrect ↵Nick Clifton5-3/+24
instruction syntax. PR 27904 * config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type): Generate a syntax error message if the reloc qualifier does not match the instruction's size.
2021-06-17gas: handle csect in bss section for XCOFFClément Chigot2-3/+14
Latest gcc versions are now generating csects instead of .lcomm for bss symbols. Some adjustements are needed in order to handle them. * config/tc-ppc.c (md_begin): Create bss section with dummy symbol. (ppc_frob_symbol): Output XTY_CM for bss csects. (ppc_fix_adjustable): Adjust condition to avoid bss csects.
2021-06-17gas: ensure sections contents is zero for BFD_RELOC_PPC*_TLSM on XCOFF.Clément Chigot6-5/+107
AIX ld expects the section contents for relocations BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM to be zero. Actually, it seems to be the case for all the TLS relocations generated by AIX assembly but only these two are mandatory. * config/tc-ppc.c (md_apply_fix): Adjust addend to nullify section contents for BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM. * testsuite/gas/ppc/xcoff-tlsm-32.d: New test. * testsuite/gas/ppc/xcoff-tlsm-64.d: New test. * testsuite/gas/ppc/xcoff-tlsm.s: New test. * testsuite/gas/ppc/aix.exp: Run new tests.
2021-06-16gas: fix hex float parsing from .dcb.? directivesJan Beulich3-71/+75
Unlike for .dc.? the parsing here failed to skip the colon before calling hex_float(). To avoid both variants of parsing going out of sync again, introduce a helper used by both.
2021-06-16gas: fix overflow diagnosticsJan Beulich6-10/+72
While the logic in fixup_segment() so far was off by 1 for fixups dealing with quantities without known signedness, thus failing to report an overflow when e.g. a byte-sized resulting value is -0x100, the logic in emit_expr_with_reloc() reported an overflow even on large negative values when the respective positive ones would not be warned about, and when fixup_segment() wouldn't do so either. Such diagnostics all ought to follow a similar pattern of what value range is acceptable. (If expressions' X_unsigned was reliably set, emit_expr_with_reloc()'s checking might make sense to tighten based on that flag.) Note that with commit 80aab57939a0 ("Changes to let cons handle bignums like general expressions") having added handling of nbytes > sizeof(valueT) in the O_constant case, converting to O_big, the setting to zero of "hibit" had become dead. With "hibit" no longer used, this code now gets dropped altogether. But additionally a respective know() gets inserted.
2021-06-15x86: bring "gas --help" output for --32 etc in sync with realityJan Beulich3-4/+15
The testsuite uses the output to determine whether BFD64 is in effect. --x32 is supported for ELF only; don't advertise it for PE/COFF. --64 is also supported for Mach-O; advertise it. Adjust the testsuite's BFD64 check accordingly. Also replace "code" by "object", since it's the object format that the options primarily control. It's also _initial_ code bitness, but this can be changed by directives.
2021-06-15x86: simplify .dispNN settingJan Beulich2-51/+24
First of all eliminate the disp{16,32,32s} static variables, which are used solely for setting a temporary variable in build_modrm_byte(). The effect there can be had without use of such a temporary and without operand_type_or(), by just setting the single bit each that needs setting. Then use operand_type_and_not(..., anydisp) when all dispNN bits want clearing together.
2021-06-15x86: slightly simplify offset_in_range()Jan Beulich2-2/+7
Applying a mask with all bits set (or its inverse, with hence all bits clear) won't alter the result (or won't trigger the warning). Re-arrange the code to eliminate two more of the somewhat odd (2 << width_minus_1) constructs.
2021-06-15x86: harmonize disp with imm handlingJan Beulich5-23/+79
Certain disp values may trigger "... shortened to ..." warnings when equivalent imm ones don't. In some of the cases there are also differences (for non-64-bit code) between BFD64 and !BFD64 builds. The resulting encodings (i.e. use [or not] of the shorter disp8 / imm8 forms) are also different in some cases. Make this handling consistent. Note that using equivalent 16-bit mode displacements / immediates continues to expose entirely different behavior (see the disp-imm-16 testcase added by an earlier patch). This may want to be the subject of further changes, but it'll then quickly become obvious that e.g. keying use of extend_to_32bit_address() to non-64-bit mode isn't appropriate either: Once we allow wrapping operands, we would better do so consistently, in which case all of this would need to become dependent upon address or operand size instead of mode.
2021-06-15x86: make offset_in_range()'s warning contents useful (again)Jan Beulich2-6/+7
In case there is something which gets shortened (perhaps only on a BFD64 build targeting a 32-bit binary), seeing the full original value is often helpful to understand what's actually going wrong. Of course for non-64-bit binaries we better wouldn't be seeing such warnings at all, as they're often indicative of a behavioral difference between BFD64 and !BFD64 builds. Prior to "gas: drop sprint_value()", which introduced the use of bfd_sprintf_vma(), the output had other shortcomings.
2021-06-15x86: off-by-1 in offset_in_range()Jan Beulich7-1/+89
Just like e.g. 0x10000 triggers a warning for size 2, -0x10000 ought to as well. Note that some of the encodings produced aren't ones one would expect, and hence the generated code is not being checked for in the new testcases.
2021-06-15x86: permit parenthesized expressions again as addressing scale factorJan Beulich5-2/+26
The description of e68c3d59acd0 ("x86: better respect quotes in parse_operands()") wrongly states: "In i386_att_operand(), which needs adjustment to remain in sync, besides respecting double quotes now, also change the logic such that we don't count parentheses anymore: Finding any opening or closing parenthesis or any double quote means we're done, because the subsequent parsing code wouldn't accept (extra) instances of these anyway." I didn't pay attention to the possibility of the scale factor being specified as an expression, which may contain parentheses. Thanks to Martin for pointing this out. Restore prior behavior or matching parentheses (backwards), while giving the variable a more suitable name. Note that this simple and immediate fix is not ging to be enough: This expression could itself involve quoted symbols. However, to address this backwards parsing needs to be done away with altogether here (such that parentheses which are part of such a quoted symbol name can also properly be accounted for), which is going to be a more intrusive change.
2021-06-14gas: fold three as_warn() in emit_expr_with_reloc()Jan Beulich2-12/+6
Simply use the available abstraction instead of, effectively, trying to open-code it.
2021-06-14gas: drop TC_ADDRESS_BYTES conditionalsJan Beulich3-5/+8
I've been repeatedly confused by, in particular, the .dc.a potable[] entry being conditional. Grepping in gas/config/ reveals only very few targets actually #define-ing it. But as of 7be1c4891a20 the symbol is always defined, so #ifdef-s are pointless (and, as said, potentially confusing). Also adjust documentation to reflect this.
2021-06-11x86: Always define TC_PARSE_CONS_EXPRESSIONH.J. Lu3-3/+12
Always define TC_PARSE_CONS_EXPRESSION to properly wrap constants for all x86 targets. * config/tc-i386.c (x86_cons): Handle GOT/PLT relocations only if needed. * config/tc-i386.h (TC_PARSE_CONS_EXPRESSION): Always define.
2021-06-11RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.Nelson Chu2-10/+14
We also need to update the riscv_opts.[rvc|rve] for elf attributes. Otherwise, the following case will fail, $ cat cadd.s .attribute arch, "rv64gc" c.add a0, a1 $ riscv64-unknown-elf-as cadd.s -o cadd.o cadd.s: Assembler messages: cadd.s:2: Error: illegal operands `c.add a0,a1 After applying this patch, $ riscv64-unknown-elf-as cadd.s -o cadd.o $ riscv64-unknown-elf-objdump -d cadd.o cadd.o: file format elf64-littleriscv Disassembly of section .text: 0000000000000000 <.text>: 0: 952e add a0,a0,a1 ... gas/ * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc and riscv_set_rve both for -march and elf attributes. (riscv_after_parse_args): Likewise.
2021-06-10arm: avoid "shadowing" of glibc function nameJan Beulich2-16/+24
Old enough glibc has an (unguarded) declaration of index() in string.h, which triggers a "shadows a global declaration" warning.
2021-06-10arm: fix array-out-of-bounds upon register parsing errorJan Beulich2-1/+6
Despite the comment ahead of the enum explicitly pointing out the need to also update the corresponding array, 1b8833198c0 ("Add support for MVE instructions: vcmp and vpt") failed to do so. Oddly enough the issue appears to be spotted only by rather old gcc (4.3-ish in my case).
2021-06-10x86: suppress LEA optimization in a specific 16-bit caseJan Beulich5-3/+69
In 16-bit mode a 16-bit address size LEA with a 16-bit displacement and a 32-bit destination is shorter to encode than the corresponding MOV. Commit fe134c656991 ("x86: optimize LEA")'s promise was to only do the transformation when the encoding size wouldn't grow, i.e. it did go a little too far. Restrict this specific case of the transformation to -O2.
2021-06-08x86: cover a.out in recently added testsJan Beulich4-41/+47
Follow the pattern found elsewhere when relocations are involved. For wrap32-data also drop a mistakenly left "ELF" from the test name. (Note that Darwin, for which the wrap32 tests are also failing, is left as-is, for there being numerous other failures already anyway, and it hence being questionable whether that target is actually properly maintained.)
2021-06-08x86: minor improvements to optimize_imm() (part II)Jan Beulich2-3/+7
Don't kind-of-open-code fits_in_unsigned_{word,long}().
2021-06-08x86: minor improvements to optimize_disp() (part II)Jan Beulich2-7/+10
- Don't kind-of-open-code fits_in_unsigned_{word,long}(). - Fold two if()s both using fits_in_unsigned_long().
2021-06-08x86-64: avoid bogus warnings with 32-bit addressingJan Beulich9-0/+89
With optimize_disp() adjusting i.types[].bitfield.disp after adjusting the value to be used as displacement, it better also stores the updated value, to avoid subsequent "... shortened to ..." warnings. Note how optimize_imm() already does so. The -0xffffffff tests being added expose a separate issue: The encoding chosen should be 1 for ModR/M.mod, not 2. This will want to be taken care of, but not right here. This at the same time addresses a similar warning and demonstrates a similar encoding issue with 16-bit addressing. Since it was omitted when introducing the lea16-optimize test, add a plain lea16 one to also cover this.
2021-06-08x86: minor improvements to optimize_disp() (part I)Jan Beulich2-11/+18
- Do the zero checking first - there's no point in doing anything else in this case. - Drop two pointless & where just before it was checked that the respective bits are clear already anyway.
2021-06-07x86: honor quoted figure braces in i386_att_operand()Jan Beulich4-8/+43
When AVX512 support was added, symbol quotation was not paid attention to. Just like the (base,index,scale) specifier gets parsed from the end of the expression, the {...} also wants parsing from the end; in no case is the first { found a guarantee of a masking or broadcasting specifier.
2021-06-07x86: better respect quotes in parse_operands()Jan Beulich4-14/+40
When d02603dc201f ("Allow symbol and label names to be enclosed in double quotes") added the check for a double quote to the loop body there, it didn't go quite far enough: Parentheses inside quotes shouldn't be counted, and character restrictions also shouldn't apply inside quoted regions. In i386_att_operand(), which needs adjustment to remain in sync, besides respecting double quotes now, also change the logic such that we don't count parentheses anymore: Finding any opening or closing parenthesis or any double quote means we're done, because the subsequent parsing code wouldn't accept (extra) instances of these anyway. Note that in parse_operands() this mimics get_symbol_name()'s questionable behavior of treating \ specially only when ahead of ". (The behavior is suspicious because the meaning of \\ then is ambiguous. It is in particular impossible to have a (quoted) symbol name end in a single \.) I would have used get_symbol_name() here, if that didn't require fiddling with input_line_pointer.
2021-06-07x86: allow unary operators to start a memory operandJan Beulich5-14/+40
So far only - was permitted, but +, !, and ~ ought to be treated the same. Rather than adding them to digit_chars[], which was at least odd to have held - so far, drop this array and its wrapper macro for being used just once. While adjusting this logic, also include [ in the characters which may start a displacement expression - gas generally treats [] as equivalent to ().
2021-06-07x86: make symbol quotation check consistent in i386_att_operand()Jan Beulich5-7/+44
When d02603dc201f ("Allow symbol and label names to be enclosed in double quotes") added the check for a leading double quote to i386_att_operand(), it missed a second similar check after having found a segment override. To avoid the two checks going out of sync again, introduce an inline helper.
2021-06-07x86: correct absolute branch check with segment overrideJan Beulich2-9/+14
This needs to happen before checking of what may legitimately start a memory operand (like is done when there's no segment override). Plus a second '*' shouldn't be permitted when one was already found before the segment override.
2021-06-07x86/Intel: drop unnecessary bracket matching from parse_operands()Jan Beulich2-13/+8
While subsequent processing in AT&T mode relies on this simplistic early checking, Intel mode hasn't been for quite a long time (or perhaps never really did).
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich3-6/+11
In the one case where non-NULL gets passed, passing NULL has the same effect. Hence the parameter is not needed at all.
2021-06-07x86: immediate operands don't allow for vector operationsJan Beulich2-10/+4
Neither masking nor broadcast are possible here, and RC/SAE get dealt with elsewhere. This also fixes gas crashes (i.e. "Fatal error: unable to continue with assembly"), since the return path being removed failed to restore input_line_pointer from save_input_line_pointer.
2021-06-07ix86: wrap constantsJan Beulich6-6/+165
Non-64-bit code should get handled the same with or without BFD64. This wasn't the case though in a number of situations (and quite likely there are more that I haven't spotted yet). It's not very nice to tie the check in md_apply_fix() to object_64bit, but afaict at that time we have no record anymore of the mode an insn was assembled in (it might also have been data). This doesn't look to be the first inconsistency of this kind, though. In x86_cons() it's even less clear what the right approach would be: flag_code shouldn't matter for data emission, but instead we'd need to know from which mode(s) the data actually gets accessed. On this basis, signed_cons() also gets adjusted.
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-1/+6
Fixes a 16 year old bug report, which even came with a patch. opcodes/ PR 1202 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. Use unsigned int for inst. gas/ PR 1202 * testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra4-0/+121
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki54-0/+7580
Add tests for the generic C0, C1, C2, C3 coprocessor instructions. gas/ * testsuite/gas/mips/c0.d: New test. * testsuite/gas/mips/mips1@c0.d: New test. * testsuite/gas/mips/mips2@c0.d: New test. * testsuite/gas/mips/mips3@c0.d: New test. * testsuite/gas/mips/mips4@c0.d: New test. * testsuite/gas/mips/mips5@c0.d: New test. * testsuite/gas/mips/mips32@c0.d: New test. * testsuite/gas/mips/mips64@c0.d: New test. * testsuite/gas/mips/r3000@c0.d: New test. * testsuite/gas/mips/r3900@c0.d: New test. * testsuite/gas/mips/r4000@c0.d: New test. * testsuite/gas/mips/vr5400@c0.d: New test. * testsuite/gas/mips/r5900@c0.d: New test. * testsuite/gas/mips/sb1@c0.d: New test. * testsuite/gas/mips/interaptiv-mr2@c0.d: New test. * testsuite/gas/mips/octeon@c0.d: New test. * testsuite/gas/mips/xlr@c0.d: New test. * testsuite/gas/mips/c1.d: New test. * testsuite/gas/mips/mips1@c1.d: New test. * testsuite/gas/mips/mips2@c1.d: New test. * testsuite/gas/mips/mips3@c1.d: New test. * testsuite/gas/mips/mips4@c1.d: New test. * testsuite/gas/mips/mips5@c1.d: New test. * testsuite/gas/mips/mips32@c1.d: New test. * testsuite/gas/mips/mips64@c1.d: New test. * testsuite/gas/mips/mipsr6@c1.d: New test. * testsuite/gas/mips/r3000@c1.d: New test. * testsuite/gas/mips/r3900@c1.d: New test. * testsuite/gas/mips/r4000@c1.d: New test. * testsuite/gas/mips/vr5400@c1.d: New test. * testsuite/gas/mips/r5900@c1.d: New test. * testsuite/gas/mips/sb1@c1.d: New test. * testsuite/gas/mips/interaptiv-mr2@c1.d: New test. * testsuite/gas/mips/octeon@c1.d: New test. * testsuite/gas/mips/xlr@c1.d: New test. * testsuite/gas/mips/c2.d: New test. * testsuite/gas/mips/vr5400@c2.d: New test. * testsuite/gas/mips/r5900@c2.d: New test. * testsuite/gas/mips/octeon@c2.d: New test. * testsuite/gas/mips/c3.d: New test. * testsuite/gas/mips/mips1@c3.d: New test. * testsuite/gas/mips/mips2@c3.d: New test. * testsuite/gas/mips/mips32@c3.d: New test. * testsuite/gas/mips/r3000@c3.d: New test. * testsuite/gas/mips/r3900@c3.d: New test. * testsuite/gas/mips/c0.l: New test stderr output. * testsuite/gas/mips/c2.l: New test stderr output. * testsuite/gas/mips/c3.l: New test stderr output. * testsuite/gas/mips/c0.s: New test source. * testsuite/gas/mips/c1.s: New test source. * testsuite/gas/mips/c2.s: New test source. * testsuite/gas/mips/c3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki8-7/+39
Verify that the RFE instruction is not only accepted where supported, but rejected where it is not as well. gas/ * testsuite/gas/mips/mips.exp: Run RFE test across all ISAs. * testsuite/gas/mips/rfe.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@rfe.d: New test. * testsuite/gas/mips/mips2@rfe.d: New test. * testsuite/gas/mips/r3000@rfe.d: New test. * testsuite/gas/mips/r3900@rfe.d: New test. * testsuite/gas/mips/rfe.l: New test stderr output.
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki96-467/+1646
Verify that individual coprocessor instructions are not only accepted where supported, but rejected where they are not as well. gas/ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all ISAs. * testsuite/gas/mips/cp0b.d: Update for ISA exclusions. * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp0c.d: Update for ISA exclusions. * testsuite/gas/mips/cp0m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3.d: Update for ISA exclusions. * testsuite/gas/mips/cp3b.d: Update for ISA exclusions. * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp3m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3d.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0b.d: New test. * testsuite/gas/mips/mips3@cp0b.d: New test. * testsuite/gas/mips/r3000@cp0b.d: New test. * testsuite/gas/mips/r3900@cp0b.d: New test. * testsuite/gas/mips/r4000@cp0b.d: New test. * testsuite/gas/mips/r5900@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0bl.d: New test. * testsuite/gas/mips/mips3@cp0bl.d: New test. * testsuite/gas/mips/r3900@cp0bl.d: New test. * testsuite/gas/mips/r4000@cp0bl.d: New test. * testsuite/gas/mips/r5900@cp0bl.d: New test. * testsuite/gas/mips/mips1@cp0c.d: New test. * testsuite/gas/mips/mips2@cp0c.d: New test. * testsuite/gas/mips/mips3@cp0c.d: New test. * testsuite/gas/mips/mips4@cp0c.d: New test. * testsuite/gas/mips/mips5@cp0c.d: New test. * testsuite/gas/mips/r3000@cp0c.d: New test. * testsuite/gas/mips/r3900@cp0c.d: New test. * testsuite/gas/mips/r4000@cp0c.d: New test. * testsuite/gas/mips/vr5400@cp0c.d: New test. * testsuite/gas/mips/r5900@cp0c.d: New test. * testsuite/gas/mips/mips1@cp0m.d: New test. * testsuite/gas/mips/r3000@cp0m.d: New test. * testsuite/gas/mips/octeon@cp2.d: New test. * testsuite/gas/mips/mipsr6@cp2b.d: New test. * testsuite/gas/mips/vr5400@cp2b.d: New test. * testsuite/gas/mips/octeon@cp2b.d: New test. * testsuite/gas/mips/mips1@cp2bl.d: New test. * testsuite/gas/mips/mipsr6@cp2bl.d: New test. * testsuite/gas/mips/r3000@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2bl.d: New test. * testsuite/gas/mips/octeon@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2m.d: New test. * testsuite/gas/mips/r5900@cp2m.d: New test. * testsuite/gas/mips/octeon@cp2m.d: New test. * testsuite/gas/mips/mips1@cp2d.d: New test. * testsuite/gas/mips/r3000@cp2d.d: New test. * testsuite/gas/mips/r3900@cp2d.d: New test. * testsuite/gas/mips/vr5400@cp2d.d: New test. * testsuite/gas/mips/r5900@cp2d.d: New test. * testsuite/gas/mips/octeon@cp2d.d: New test. * testsuite/gas/mips/mips1@cp2-64.d: New test. * testsuite/gas/mips/mips2@cp2-64.d: New test. * testsuite/gas/mips/mips32@cp2-64.d: New test. * testsuite/gas/mips/mips32r2@cp2-64.d: New test. * testsuite/gas/mips/mips32r3@cp2-64.d: New test. * testsuite/gas/mips/mips32r5@cp2-64.d: New test. * testsuite/gas/mips/mips32r6@cp2-64.d: New test. * testsuite/gas/mips/r3000@cp2-64.d: New test. * testsuite/gas/mips/r3900@cp2-64.d: New test. * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test. * testsuite/gas/mips/mips1@cp3.d: New test. * testsuite/gas/mips/mips2@cp3.d: New test. * testsuite/gas/mips/mips32@cp3.d: New test. * testsuite/gas/mips/r3000@cp3.d: New test. * testsuite/gas/mips/r3900@cp3.d: New test. * testsuite/gas/mips/mips1@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3b.d: New test. * testsuite/gas/mips/mips32@cp3b.d: New test. * testsuite/gas/mips/r3000@cp3b.d: New test. * testsuite/gas/mips/r3900@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3bl.d: New test. * testsuite/gas/mips/mips32@cp3bl.d: New test. * testsuite/gas/mips/r3900@cp3bl.d: New test. * testsuite/gas/mips/mips1@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3m.d: New test. * testsuite/gas/mips/r3000@cp3m.d: New test. * testsuite/gas/mips/r3900@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3d.d: New test. * testsuite/gas/mips/cp0b.l: New test stderr output. * testsuite/gas/mips/cp0bl.l: New test stderr output. * testsuite/gas/mips/cp0c.l: New test stderr output. * testsuite/gas/mips/cp0m.l: New test stderr output. * testsuite/gas/mips/cp2.l: New test stderr output. * testsuite/gas/mips/cp2-64.l: New test stderr output. * testsuite/gas/mips/cp2b.l: New test stderr output. * testsuite/gas/mips/cp2bl.l: New test stderr output. * testsuite/gas/mips/cp2m.l: New test stderr output. * testsuite/gas/mips/cp2d.l: New test stderr output. * testsuite/gas/mips/cp3.l: New test stderr output. * testsuite/gas/mips/cp3b.l: New test stderr output. * testsuite/gas/mips/cp3bl.l: New test stderr output. * testsuite/gas/mips/cp3m.l: New test stderr output. * testsuite/gas/mips/cp3d.l: New test stderr output.
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki3-2/+53
Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki16-0/+215
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across the relevant ISA levels. Omit CP1 branches, covered elsewhere. gas/ * testsuite/gas/mips/cp0b.d: New test. * testsuite/gas/mips/cp0bl.d: New test. * testsuite/gas/mips/cp2b.d: New test. * testsuite/gas/mips/micromips@cp2b.d: New test. * testsuite/gas/mips/cp2bl.d: New test. * testsuite/gas/mips/micromips@cp2bl.d: New test. * testsuite/gas/mips/cp3b.d: New test. * testsuite/gas/mips/cp3bl.d: New test. * testsuite/gas/mips/cp0b.s: New test source. * testsuite/gas/mips/cp0bl.s: New test source. * testsuite/gas/mips/cp2b.s: New test source. * testsuite/gas/mips/cp2bl.s: New test source. * testsuite/gas/mips/cp3b.s: New test source. * testsuite/gas/mips/cp3bl.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki4-0/+26
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki9-29/+47
The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki27-0/+2180
Cover basic CP0, CP2, CP3 move, load and store instructions across the relevant ISA levels. Omit CP0 move and CP1 instructions as they are covered elsewhere. gas/ * testsuite/gas/mips/cp0c.d: New test. * testsuite/gas/mips/cp0m.d: New test. * testsuite/gas/mips/r3900@cp0m.d: New test. * testsuite/gas/mips/cp2.d: New test. * testsuite/gas/mips/micromips@cp2.d: New test. * testsuite/gas/mips/cp2m.d: New test. * testsuite/gas/mips/mipsr6@cp2m.d: New test. * testsuite/gas/mips/micromips@cp2m.d: New test. * testsuite/gas/mips/cp2d.d: New test. * testsuite/gas/mips/mipsr6@cp2d.d: New test. * testsuite/gas/mips/micromips@cp2d.d: New test. * testsuite/gas/mips/cp2-64.d: New test. * testsuite/gas/mips/micromips@cp2-64.d: New test. * testsuite/gas/mips/cp3.d: New test. * testsuite/gas/mips/cp3m.d: New test. * testsuite/gas/mips/cp3d.d: New test. * testsuite/gas/mips/cp0c.s: New test source. * testsuite/gas/mips/cp0m.s: New test source. * testsuite/gas/mips/cp2.s: New test source. * testsuite/gas/mips/cp2m.s: New test source. * testsuite/gas/mips/cp2d.s: New test source. * testsuite/gas/mips/cp2-64.s: New test source. * testsuite/gas/mips/cp3.s: New test source. * testsuite/gas/mips/cp3m.s: New test source. * testsuite/gas/mips/cp3d.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-4/+11
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki3-0/+49
The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
generated by cgit v1.1 at 2024-07-18 00:33:40 +0000