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* config/obj-elf.c (elf_file_symbol): When using ECOFF debugging,
pass on the new file hook.
* config/tc-alpha.c (alpha_fix_adjustable): Not quite the same as
!alpha_force_relocation, as local LITERALs can be adjusted to be
relative to the section.
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misaligned text label. Based on patch from Ronald F. Guilmette
<rfg@monkeys.com>.
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PCINDEX frag. From Ronald F. Guilmette <rfg@monkeys.com>.
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immediate value.
(md_assemble): If the size is 'B', set fx_signed.
(md_apply_fix_2): Use fx_signed when checking for overflow.
* write.h (struct fix): Add fx_signed field.
* write.c (fix_new_internal): Initialize fx_no_overflow and
fx_signed fields.
(fixup_segment): Use fx_signed when checking for overflow.
* config/obj-coff.c (fixup_segment): Check fx_no_overflow and
fx_signed when checking for overflow.
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updated, and all the useful information is in doc/internals.texi.
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* read.c (read_a_source_file): Check for conditional operators
before doing an MRI pending alignment.
* config/tc-m68k.h (m68k_conditional_pseudoop): Declare.
(tc_conditional_pseudop): Define.
* config/tc-m68k.c (m68k_conditional_pseudop): New function.
* doc/internals.texi (CPU backend): Describe
tc_conditional_pseudoop.
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* config/tc-m68k.c (m68k_rel32_from_cmdline): New static
variable.
(md_begin): Check m68k_rel32_from_cmdline before setting
m68k_rel32.
(m68k_mri_mode_change): Likewise.
(md_longopts): Add --disp-size-default-16 and
--disp-size-default-32.
(md_parse_option): Handle new options.
(md_show_usage): Mention new options.
* doc/c-m68k.texi (M68K-Opts): Document new options.
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* config/tc-m68k.c (m68k_index_width_default): New static
variable.
(m68k_ip): Use m68k_index_width_default to set the size of a base
register whose size was not given.
(md_longopts): Add --base-size-default-16 and
--base-size-default-32.
(md_parse_option): Handle new options.
(md_show_usage): Mention new options.
* doc/c-m68k.texi (M68K-Opts): Document new options.
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* configure: Rebuild.
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work if valueT is only 32 bits.
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* gas/mips/mips.exp: Run mips16 test.
* gas/mips/mips.exp: Run dli test unconditionally.
* gas/mips/dli.s: Add text symbol. Add nops to round to 16 byte
boundary.
* gas/mips/dli.d: Corresponding changes.
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than byte_order.
(byte_order): Remove.
(mips_init_after_args): Remove.
* config/tc-mips.h (LITTLE_ENDIAN, BIG_ENDIAN): Don't define.
(mips_init_after_args): Don't declare.
(tc_init_after_args): Don't define.
* config/tc-mips.h (tc_frob_after_relocs): Define if
OBJ_MAYBE_ELF.
(mips_elf_final_processing): Likewise.
(ELF_TC_SPECIAL_SECTIONS): Likewise.
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checking for a macro. From Ronald F. Guilmette
<rfg@monkeys.com>.
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* gas/sparc/synth64.d: Likewise.
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add segment argument. If OBJ_ELF, treat a relocation against a
symbol in a linkonce section like a relocation against an external
symbol.
* config/tc-sparc.h (MD_APPLY_FIX3): Define.
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includes config.h instead of host.h, tc.h instead of tp.h, and
targ-env.h instead of target-environment.h.
Also, obj-format.h includes targ-cpu.h instead of
target-processor.h.
start-sanitize-tic80
(Laying groundwork, that will be incrementally fleshed out,
for TIc80 support)
* configure.in (case ${generic_target}): Add tic80-*-coff entry.
* configure: Rebuild with autoconf.
* config/obj-coff.h (coff/tic80.h): Include if TC_TIC80 defined.
(TARGET_FORMAT): Define to "coff-tic80".
* config/tc-tic80.c: New file for TIc80 support.
* config/tc-tic80.h: New file for TIc80 support.
end-sanitize-tic80
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handling.
PR 11259.
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equated to an undefined symbol, convert the fixup to being against
the target symbol. Remove obsolete code handling a special case
for i386 PIC.
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* config/tc-d10v.c (do_assemble): Correct previous bug fix.
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* tc-d10v.c (md_assemble): Fix bug which caused
second instruction in a line to be case sensitize. PR11312
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* config/tc-d10v.c (md_assemble): Fix bug which caused
second instruction in a line to be case sensitize. PR11312
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range check operands with MN10200_OPERAND_NOCHECK set.
(check_operand): Likewise.
So the assembler won't check on "and -1,dn".
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(md_begin): Always align the text section to a four byte
boundary.
(append_insn): Remove call to record_align.
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(struct insn_label_list): Define.
(insn_labels, free_insn_labels): New static variables.
(mips_clear_insn_labels): New static function.
(append_insn): Mark all mips16 text labels, and make them odd.
Handle all labels after emitting a nop, not just one. Call
mips_clear_insn_labels rather than just clearing insn_label.
(mips_emit_delays): Add insns parameter, and use it to decide
whether to mark mips16 labels. Handle all labels, not just one.
Force mips16 labels to be odd. Change all callers.
(mips16_immed): Don't check for an odd branch target.
(md_apply_fix): Don't check mips16 mode for a branch reloc.
(mips16_extended_frag): Ignore the low bit in a branch target.
(md_convert_frag): Likewise.
(mips_no_prev_insn): Call mips_clear_insn_labels rather than just
clearing insn_label.
(mips_align, mips_flush_pending_output, s_cons): Likewise.
(s_float_cons, s_gpword): Likewise.
(s_align): Use insn_labels rather than insn_label.
(s_cons, s_float_cons, s_gpword): Likewise.
(mips_frob_file_after_relocs): New function.
(mips_define_label): Rewrite to add to insn_labels list.
* config/tc-mips.h (tc_frob_file_after_relocs): Define.
* ecoff.c (ecoff_build_symbols): If the size of a function comes
out odd, increment it.
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when using the register indirect addressing mode.
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check 24bit operands for overflow.
(check_operand): Likewise.
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pseudo-op for COFF and ELF.
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(RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and
store them. Adjust other RELAX_MIPS16 macros.
(RELAX_MIPS16_DSLOT): Define.
(RELAX_MIPS16_JAL_DSLOT): Define.
(append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct
handling of whether previous instruction has a fixup. Set
prev_insn_reloc_type.
(mips_no_prev_insn): Clear prev_insn_reloc_type.
(mips16_extended_frag): Use the right base address for a PC
relative add or load.
(md_convert_frag): Likewise. If a PC relative add or load is
used, record the alignment for the section.
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linkonce section into a reloc against the section symbol.
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branch instructions.
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.ifdef, to accomodate change to avoid default alignment on
embedded systems.
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system, don't set the section alignment to 2**4.
(s_change_sec): Likewise.
(append_insn): Call record_alignment for the section.
(md_section_align): Don't align the section size for an embedded
ELF system.
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resolved; expression symbols may have been skipped.
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resolved; expression symbols may have been skipped.
PR 11240.
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the assembler.
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issues correctly.
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