aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2024-10-29LoongArch: Corrected to GNU style codeLulu Cai1-10/+10
2024-10-29gas: make fix_new_exp()'s "exp" parameter constJan Beulich2-16/+4
This really should be only an input; in particular it looks bogus that O_add expressions are even altered. That altering and the recursion are even pointless: Once expanding what the inner call would do (with O_symbol) it becomes clear that this is no different than the default case. Simplify the code accordingly, retaining the comment.
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich78-237/+232
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-29RISC-V: Update the doc to match ISA manualKito Cheng1-36/+36
ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7), and I realized that may something I typo at beginning when I write the patch for `.insn` support...:P [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
2024-10-28RISC-V: Fix typo in gas/testsuite/gas/riscv/mapping.sJim Lin3-6/+6
gas/ * gas/riscv/mapping.s: Fix typo. * gas/riscv/mapping-dis.d: Fix typo. * gas/riscv/mapping-symbols.d. Fix typo.
2024-10-24Replace uses of asprintf with xasprintfAlan Modra7-49/+11
xasprintf has a nicer interface and behaves like xmalloc as far as memory is concerned, ie. no need to check a return status and the program exits with an error on OOM. binutils/ * dwarf.c (load_debug_sup_file): Replace asprintf with xasprintf. * nm.c (get_elf_symbol_type, get_coff_symbol_type): Likewise. * objdump.c (dump_ctf_indent_lines): Likewise. * readelf.c (display_lto_symtab, dump_ctf_indent_lines): Likewise. * windres.c (main): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. gas/ * config/tc-kvx.c (kvx_emit_single_noop): Simplify. * config/tc-riscv.c (md_assemblef): Replace asprintf with xasprintf. * read.c (s_nop, do_s_func): Likewise. * stabs.c (stabs_generate_asm_func): Likewise. (stabs_generate_asm_endfunc): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. ld/ * ldlang.c (lang_leave_overlay_section): Replace xmalloc+sprintf with xasprintf. Localise vars. * lexsup.c (parse_args): Replace asprintf with xasprintf. * pe-dll.c (make_head, make_tail, make_one): Likewise. (make_singleton_name_thunk, make_import_fixup_entry): Likewise. (make_runtime_pseudo_reloc): Likewise. (pe_create_runtime_relocator_reference): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate.
2024-10-22LoongArch: Force relocation for every reference to the global offset tableLulu Cai4-0/+75
Local absolute symbols are resolved at assembly stage and the symbol value is placed in the relocation addend. But non-zero addend will cause an assertion failure during linking. Forces emission of relocations to defer resolution of local abs symbols until link time. bfd/ * elfnn-loongarch.c (loongarch_elf_relax_section): Determine absolute symbols in advance to avoid ld crash. gas/ * config/tc-loongarch.c (loongarch_force_relocation): New function to force relocation. * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros to force relocation. (loongarch_force_relocation): Function declaration. * testsuite/gas/loongarch/localpic.d: New test. * testsuite/gas/loongarch/localpic.s: New test.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc6-2/+28
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-16Support Intel AVX10.2 convert instructionsLiwei Xu14-0/+1292
In this patch, we will support AVX10.2 convert instructions. All of them are new instruction forms. Among all the instructions, vcvtbiasph2[b,h]f8[,s] needs extra care. Since Operand 2 could indicate memory size, we do not need suffix under ATTmode. However, we could not fold all three templates but only XMM/YMM since the dst operand size are the same for them. Also, a new iterator <cvt8> is added to reduce redundancy. gas/ * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: New. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F3874, PREFIX_EVEX_MAP5_18, PREFIX_EVEX_MAP5_1B, PREFIX_EVEX_MAP5_1E and PREFIX_EVEX_MAP5_74. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c (MOD_EVEX_0F38B1): New. (PREFIX_EVEX_0F3874): Ditto. (PREFIX_EVEX_MAP5_18): Ditto. (PREFIX_EVEX_MAP5_1B): Ditto. (PREFIX_EVEX_MAP5_1E): Ditto. (PREFIX_EVEX_MAP5_74): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-10-15x86: Refine instruction check in x86_check_tls_relocationCui, Lili1-10/+11
gas/ChangeLog: * config/tc-i386.c (x86_check_tls_relocation): Refine instruction check.
2024-10-15x86/testsuite: Rename AVX10.2 media testcasesHaochen Jiang14-12/+12
Change these testcase name to make them clearer. gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media.d: ...this. * testsuite/gas/i386/avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/avx10_2-256-media.s: ...this. * testsuite/gas/i386/avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media.d: ...this. * testsuite/gas/i386/avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/avx10_2-512-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.s: ...this. * testsuite/gas/i386/i386.exp: Change testcase name. * testsuite/gas/i386/x86-64.exp: Ditto.
2024-10-14ia64/ELF: fix HPUX testsuite falloutJan Beulich3-13/+13
... from 1f1b5e506bf0 ("bfd/ELF: restrict file alignment for object files"), as noticed / reported by Alan.
2024-10-14gas: drop SKIP_WHITESPACE_AFTER_NAME()Jan Beulich21-98/+85
Exclusively all users should use restore_line_pointer() instead, at which point SKIP_WHITESPACE() suffices as a check afterwards.
2024-10-14LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai3-1/+20
The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead of the relocation in fixp. This can cause the second relocation of a pair to be deleted when -mthin-add-sub is enabled. Apply the correct macro to fix this. Also sets the initial value of -mthin-add-sub.
2024-10-11x86: bring 64-bit-only cmdline option handling in syncJan Beulich1-2/+8
--64 and --x32 are already suppressed in --help output when BFD64 is not defined. Also avoid recognizing these options in such configurations.
2024-10-11bfd/ELF: restrict file alignment for object filesJan Beulich5-18/+18
While for executables properly aligning sections within the file can be quite relevant, the same is of pretty little importance for relocatable object files. Avoid passing "true" into _bfd_elf_assign_file_position_for_section() when dealing with object files, but compensate minimally by applying log_file_align in such cases as a cap to the alignment put in place.
2024-10-11Support Intel AVX10.2 media instructionsHaochen Jiang18-0/+1604
In disassembler part, for vnni instructions, we extended previous VEX part using %XE in disassembler to promote them to EVEX by reusing the original VEX table. For vmpsadbw, we will also use %XE. However, it is hard to reuse the VEX table, so we are using new ones. In assmbler part, we put the vnni table entries with previous vnni instructions since they are just promotion from AVX-VNNI-INT{8,16}. Since we will prefer VEX encoding, we need to use the different table order in template <vnni>, which prefers EVEX due to earlier introduction for AVX512_VNNI than AVX_VNNI. This means a new <vnni>. For vdpphps and vmpsadbw, we put them at the end of the table, with future AVX10.2 instructions. Nit: I will remove the arch requirement for avx_vnni_int{8,16} in evex-promote testcases after AVX10.2 implies AVX-VNNI-INT{8,16}. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-1-intel.d: New. * testsuite/gas/i386/avx10_2-256-1.d: Ditto. * testsuite/gas/i386/avx10_2-256-1.s: Ditto. * testsuite/gas/i386/avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.s: Ditto. * testsuite/gas/i386/avx10_2-promote.d: Ditto. * testsuite/gas/i386/avx10_2-promote.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.s: Ditto. opcodes/Changelog: * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F3852. Add PREFIX_EVEX_0F3A42_W_0. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c: Adjust PREFIX_VEX_0F3850_W_0, PREFIX_VEX_0F3851_W_0, PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Lili Cui <lili.cui@intel.com>
2024-10-10s390: Add arch15 instructionsAndreas Krebbel6-4/+206
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-10-08RISC-V: Fix implicit dependency of Zabha and ZacasXiao Zeng1-2/+2
1 Zabha depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc> 2 Zacas depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc> bfd/ChangeLog: * elfxx-riscv.c: Zabha and Zacas implicitly depend on Zaamo. gas/ChangeLog: * testsuite/gas/riscv/imply.d: Updated. Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
2024-10-04gas: hide emulation struct format_ops instances when not neededJan Beulich7-114/+131
Most targets don't even support emulations, so this data (and certain functions) are entirely dead code for them.
2024-10-04x86: prune OBJ_MAYBE_... usesJan Beulich3-169/+113
With the removal of emulations, OBJ_MAYBE_... can no longer be defined. Tidy code wherever they're used, which also includes the dropping of most IS_ELF and uses and checks of OUTPUT_FLAVOR. Where touching such constructs anyway, also drop TE_PEP checks when used together with TE_PE ones (the former implies the latter).
2024-10-04x86: drop largely defunct gas emulationsJan Beulich10-185/+2
Both ELF and COFF have various sub-flavors, each of which would then require its own emulation: Right now when configuring a COFF/PE secondary target (with perhaps an ELF primary one), one gets plain COFF emulation rather than COFF/PE one. As such a multitude of emulations would be unwieldy (and likely fragile) drop gas emulations altogether instead.
2024-10-04include: de-duplicate i386.h and x86_64.hJan Beulich1-6/+1
Move common definitions to a new x86.h, thus allowing gas'es obj-coff.h to include just that, getting rid of a TE_PEP compile-time dependency.
2024-10-04gas: drop generate_asm_lineno emulation hookJan Beulich5-14/+0
It's not wired up, so can't be used.
2024-10-04gas: don't use COFF-specific SF_SET_LOCAL() directly from read.cJan Beulich8-3/+23
Make this a proper obj-format hook instead.
2024-10-04gas/dw2gencfi: correct .sframe section conditionalJan Beulich1-6/+5
While originally this was in preparation of a subsequent change making SUPPORT_FRAME_LINKONCE potentially dependent on a global variable, the construct appears unlikely to have been correct in the first place: The variable would have been passed reliably uninitialized when SUPPORT_FRAME_LINKONCE is build-time true. While there correct indentation of the parameters passed to get_cfi_seg().
2024-10-04gas: put emul decls in emul.hJan Beulich3-5/+5
The individual struct emulation instances shouldn't be declared in a .c file; it and the producers of the symbols want to both see the declarations, so declarations and definitions don't go out of sync. Move these declarations to emul.h. While there also adjust the conditional around this_format: That symbol is never #define-d anywhere, and it's needed only when USE_EMULATIONS is defined. (Really, when obj-multi isn't in use, it also is effectively only ever written to.)
2024-10-04gas: drop unused fields from struct emulationJan Beulich9-76/+0
Neither .match not .bfd_name appear to ever have been used in the last about 25 years. Purge them.
2024-10-01segv in read_a_source_fileAlan Modra1-0/+1
On some paths through read_a_source file, "s" may not be set. * read.c (read_a_source_file): Correct code ignoring comment.
2024-09-28gas buffer overflow with --listing-rhs-widthAlan Modra1-5/+18
With listings enabled, gas keeps a small cache of source lines. They are stored in buffers of size LISTING_RHS_WIDTH, ie. 100. Given listing-rhs-width larger than 100 it is of course possible to overflow the buffer. Fix that by allocating as needed. We could allocate all buffers on the first call to print_source using listing_rhs_width, but I chose not to do that in case some future assembly directive allows changes to listing_rhs_width similarly to the way paper_width can change during assembly.
2024-09-27x86: fix Solaris gas testsuite runJan Beulich1-1/+9
Commits 8015b1b0c1a1 ("x86-64: Never make R_X86_64_GOT64 section relative"), d774bf9b3623 ("x86: Add tls check in gas"), and 1b714c14e40f ("x86: Turn PLT32 to PC32 only for PC-relative relocations") all should have adjusted the Solaris counterpart of the reloc64 test as well.
2024-09-27RISC-V: odd data padding vs mapping symbolsJan Beulich3-5/+30
Odd data padding has a $d label inserted at its beginning. When a $x... label is removed instead, a replacement is inserted after the padding. The same, however, needs to also happen when there's no $x to replace.
2024-09-27RISC-V: correct alignment directive handling for text sectionsJan Beulich6-17/+217
.insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits.
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich10-0/+202
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich9-0/+296
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich10-0/+114
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: correct {,V}PEXTR{D,Q} optimizationJan Beulich1-0/+1
A possible relocation associated with a memory operand also needs moving.
2024-09-26x86/testsuite: Refine AVX10.2 rounding testcasesHaochen Jiang2-2/+3
Using hard byte code is not a good idea in dump file. Add a label for intel syntax test check to avoid that. gas/ChangeLog: * testsuite/gas/i386/avx10_2-rounding-intel.d: Use label for test split. * testsuite/gas/i386/avx10_2-rounding.s: Add label to avoid hard coding in dump file.
2024-09-26x86 TLS relocation checksAlan Modra1-7/+8
Some configurations (eg. i386-bsd, i386-msdos) broke with the addition of the TLS relocation checking. The "x86_elf_abi undeclared" error has been fixed, but "gotrel defined but not used" remains. Fix that. Also invert the preprocessor test around lex_got to make it positive logic and remove the LEX_AT condition which is no longer necessary. (The only x86 config files defining LEX_AT also define TE_PE.)
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei10-2/+85
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-24x86: Enable TLS relocation check only for ELFH.J. Lu1-11/+11
Since TLS relocation check is ELF specific, enable it only for ELF. PR gas/32022 * config/tc-i386.c (x86_tls_error_type): Define only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (x86_check_tls_relocation): Likewise. (x86_report_tls_error): Likewise. (i386_assemble): Check TLS relocations only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (md_show_usage): Output -mtls-check= only if OBJ_MAYBE_ELF or OBJ_ELF is defined. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-23Fix compile time error introduced by ↵Nick Clifton1-2/+8
d774bf9b3623239a1cfa729afcf048a15da657d3 for non-ELF x86 targets
2024-09-23x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu5-1/+21
commit 292676c15a615b5a95bede9ee91004d3f7ee7dfd Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Feb 13 13:44:17 2020 -0800 x86: Resolve PLT32 reloc aganst local symbol to section resolved PLT32 relocation against local symbol to section and commit 2585b7a5ce5830e60a089aa2316a329558902f0c Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun Jul 19 06:51:19 2020 -0700 x86: Change PLT32 reloc against section to PC32 turned PLT32 relocation against section into PC32 relocation. But these transformations are valid only for PC-relative relocations. Add fx_pcrel check for PC-relative relocations when performing these transformations to keep PLT32 relocation in `movq $foo@PLT, %rax`. gas/ PR gas/32196 * config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel for PLT32 relocations. (i386_validate_fix): Turn PLT32 relocation into PC32 relocation only if fixp->fx_pcrel is set. * testsuite/gas/i386/reloc32.d: Updated. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/reloc32.s: Add PR gas/32196 test. * testsuite/gas/i386/reloc64.s: Likewise. ld/ PR gas/32196 * testsuite/ld-x86-64/plt3.s: New file. * testsuite/ld-x86-64/x86-64.exp: Run plt3. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-21x86: Add tls check in gasCui, Lili23-32/+866
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-20x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu3-0/+17
R_X86_64_GOT64 relocation should never be made section relative. Change tc_i386_fix_adjustable to return 0 for BFD_RELOC_X86_64_GOT64. gas/ PR gas/32189 * config/tc-i386.c (tc_i386_fix_adjustable): Return 0 for BFD_RELOC_X86_64_GOT64. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/reloc64.s: Add more tests for R_X86_64_GOT64 and R_X86_64_GOTOFF64. ld/ PR gas/32189 * testsuite/ld-x86-64/x86-64.exp: Run PR gas/32189 test. * testsuite/ld-x86-64/pr32189.s: New file. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu7-44/+18
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted to support EGPR in APX spec. Don't promote them out of APX spec. This commit effectively reverted: ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded gas/ PR gas/32171 * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Add V{BROADCAST,EXTRACT,INSERT}{F,I}128 tests with EGPR. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} tests with EGPR. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Updated. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. opcodes/ PR gas/32171 * i386-opc.tbl: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} entries with EGPR. * i386-tbl.h: Regenerated. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-15MIPS/GAS: Discard redundant instruction from DDIV/DREM macrosMaciej W. Rozycki12-29/+5
A sequence such as: li at,-1 bne xx,at,0f li at,1 dsll32 at,at,0x1f is produced in the expansion of the DDIV and DREM assembly macros, where a redundant `li at,1' instruction is used to load an intermediate value of 1 into $at, which is then left-shifted by 63 with `dsll32 at,at,0x1f' yielding 0x8000000000000000. However this value likewise results from left-shifting the value of -1, already present in $at at this point. Remove the extraneous instruction then, shortening the sequence emitted. Adjust dumps in the testsuite accordingly.
2024-09-15MIPS/GAS/testsuite: Print instructions in hex in division testsMaciej W. Rozycki21-241/+249
Add `--show-raw-insn' to division tests so as to verify branch offsets without the need to know actual offsets into the text section individual instructions have been assembled at. Add `-z' where applicable to make interlock NOP instructions appear in output so as to verify them without the need to know the offsets too. Replace individual offsets to match against with generic patterns so that a change in the expansion of an assembly macro does not affect code that follows.
2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus2-12/+12
This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <dost@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus1-7/+0
Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
generated by cgit v1.1 at 2025-01-25 06:39:17 +0000