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2017-05-03Prevent a seg-fault in the assembler when provided with a bogus input source ↵Nick Clifton2-3/+23
file. PR gas/20941 * symbols.c (snapshot_symbol): Handle the case where resolve_expression returns a local symbol.
2017-05-03MIPS16/GAS: Fix absolute references with PC-relative synthetic instructionsMaciej W. Rozycki18-1/+193
Complement commit 88a7ef168927 ("MIPS16/GAS: Restore unsupported relocation diagnostics") and also propagate constant expressions, either already reduced from absolute symbol references or created from literals in the first place, used as a PC-relative operand with the MIPS16 LA, LW, DLA and LD synthetic instructions to relaxation, matching the way forward absolute symbol references have been handled as from the commit referred and letting relaxation produce any necessary relocations, if possible, for the absolute value requested to be reproduced at the run time. Call `symbol_append' for any expression symbol created for the purpose of MIPS16 relaxation as with constant expressions now propagated from earlier on such symbols may make it through and have R_MIPS16_PC16_S1 relocations emitted against, and therefore need to appear in the symbol table produced. gas/ * config/tc-mips.c (append_insn): Call `symbol_append' for any expression symbol created for MIPS16 relaxation. (match_mips16_insn): Don't encode a constant value as an immediate with a PC-relative operand. * testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-1.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-2.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-absolute-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-1.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-04-27MIPS16/GAS: Factor out duplicate symbol value conversion codeMaciej W. Rozycki2-92/+94
Factor out and consolidate duplicate section-relative to PC-relative symbol value conversion in `mips16_extended_frag' and `md_convert_frag' used for MIPS16 relaxation, observing that the final calculation in the latter function implies `stretch == 0'. Sanitize the formatting of code moved. gas/ * config/tc-mips.c (mips16_pcrel_val): New function, factored out from... (mips16_extended_frag): ... here. (md_convert_frag): Use `mips16_pcrel_val' rather than repeated code in MIPS16 relaxation, with `stretch' hardcoded to 0.
2017-04-27MIPS16/GAS: Rename the LONG_BRANCH relaxation flagMaciej W. Rozycki2-6/+16
Following commit 177b4a6ad004 ("infinite loop in mips16 assembler relaxation"), <https://sourceware.org/ml/binutils/2002-03/msg00345.html> the LONG_BRANCH flag used in MIPS16 relaxation has lost its use for branches. Complement commit 88a7ef168927 ("MIPS16/GAS: Restore unsupported relocation diagnostics") then, which has removed the remains of code deactivated by the former commit, and rename the flag to ALWAYS_EXTENDED, more accurately reflecting its current use to select the extended form of PC-relative ADDIU, DADDIU, LD and LW instructions. gas/ * config/tc-mips.c (RELAX_MIPS16_LONG_BRANCH): Rename to... (RELAX_MIPS16_ALWAYS_EXTENDED): ... this. (RELAX_MIPS16_MARK_LONG_BRANCH): Rename to... (RELAX_MIPS16_MARK_ALWAYS_EXTENDED): ... this. (RELAX_MIPS16_CLEAR_LONG_BRANCH): Rename to... (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): ... this. (mips16_extended_frag): Adjust accordingly.
2017-04-27Tidy S_FORCE_RELOCAlan Modra2-6/+14
Separate out symbol flag reasons from section reasons to force a reloc. Yes, this adds another section test to the local symbol case too. * symbols.c (S_FORCE_RELOC): Separate section and symbol tests.
2017-04-27MIPS/GAS: Fix `.option picX' handling with relaxationMaciej W. Rozycki20-52/+375
Correct the handling of `.option pic0' and `.option pic2' GAS pseudo-ops in relaxation and use the setting of `mips_pic' (which these directives control) as at the time a relaxed frag has been created rather than the final `mips_pic' setting at the end of the source file processed. To do so record whether `mips_pic' is NO_PIC or not in the frag itself and use this information throughout relaxation instead of `mips_pic' to decide which of NO_PIC or SVR4_PIC to produce machine code for, fixing code generation and removing a possible fatal failure reproducible with: $ as -32 --relax-branch -o option-pic-relax-3.o option-pic-relax-3.s option-pic-relax-3.s: Assembler messages: option-pic-relax-3.s:7: Warning: relaxed out-of-range branch into a jump option-pic-relax-3.s: Internal error in cvt_frag_to_fill at .../gas/write.c:490. Please report this bug. $ using the test source included, due to a buffer overrun in filling the variable part of a frag. Likewise use the `fx_tcbit2' flag of a BFD_RELOC_16_PCREL_S2 fixup to handle the simple case of substituting an out of range unconditional branch with an equivalent absolute jump in NO_PIC code. Retain the current way of VXWORKS_PIC use, which commit 41a1578ed17c ("MIPS/GAS: Sanitize `.option picX' pseudo-op") has forbidden the use of `.option picX' with. gas/ * config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag. (RELAX_PIC): New macro. (RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO) (RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT) (RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND): Shift bits. (RELAX_BRANCH_ENCODE): Add `pic' flag. (RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK) (RELAX_BRANCH_TOOFAR): Shift bits. (RELAX_BRANCH_PIC): New macro. (RELAX_MICROMIPS_ENCODE): Add `pic' flag. (RELAX_MICROMIPS_PIC): New macro. (RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT) (RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS) (RELAX_MICROMIPS_RELAX32): Shift bits. (relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE. (append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the first fixup created. (md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the fixup processed rather than `mips_pic' in choosing to relax an out of range branch to a jump. (relaxed_branch_length): Use the `pic' flag of the relaxed frag rather than `mips_pic'. (relaxed_micromips_32bit_branch_length): Likewise. (md_estimate_size_before_relax): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/option-pic-relax-0.d: New test. * testsuite/gas/mips/option-pic-relax-1.d: New test. * testsuite/gas/mips/option-pic-relax-2.d: New test. * testsuite/gas/mips/option-pic-relax-3.d: New test. * testsuite/gas/mips/option-pic-relax-3a.d: New test. * testsuite/gas/mips/option-pic-relax-4.d: New test. * testsuite/gas/mips/option-pic-relax-5.d: New test. * testsuite/gas/mips/option-pic-relax-2.l: New stderr output. * testsuite/gas/mips/option-pic-relax-3.l: New stderr output. * testsuite/gas/mips/option-pic-relax-4.l: New stderr output. * testsuite/gas/mips/option-pic-relax-5.l: New stderr output. * testsuite/gas/mips/option-pic-relax-0.s: New test source. * testsuite/gas/mips/option-pic-relax-1.s: New test source. * testsuite/gas/mips/option-pic-relax-2.s: New test source. * testsuite/gas/mips/option-pic-relax-3.s: New test source. * testsuite/gas/mips/option-pic-relax-4.s: New test source. * testsuite/gas/mips/option-pic-relax-5.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu3-16/+41
enter/leave mnemonics are enhanced to not only accept register ranges but also single register (i.e., r13) or even no GPR register at all. gas/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/leave_enter.d: Update test. * testsuite/gas/arc/leave_enter.s: Likewise. opcodes/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. * arc-opc.c (insert_r13el): New function. (R13_EL): Define. * arc-tbl.h: Add new enter/leave variants.
2017-04-25[ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu3-5/+10
NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is located before NOP in the instruction table, the disassembler prints MOV 0,0 for NOP. Reorder the instructions such that NOP is first. gas/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/b.d: Update test. * testsuite/gas/arc/noargs_hs.d: Likewise. opcode/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
2017-04-25MIPS/GAS: Correct BFD_RELOC_MIPS16_16_PCREL_S1 fixup sizeMaciej W. Rozycki8-5/+108
Correct the size of a BFD_RELOC_MIPS16_16_PCREL_S1 fixup made in `md_convert_frag', fixing a bug introduced with commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support)". Add test cases to verify that the overflow of this fixup's in-place addend is still correctly detected. gas/ * config/tc-mips.c (md_convert_frag): Correct BFD_RELOC_MIPS16_16_PCREL_S1 fixup size. * testsuite/gas/mips/mips16-branch-addend-4.d: New test. * testsuite/gas/mips/mips16-branch-addend-5.d: New test. * testsuite/gas/mips/mips16-branch-addend-5.l: New stderr output. * testsuite/gas/mips/mips16-branch-addend-4.s: New test source. * testsuite/gas/mips/mips16-branch-addend-5.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-04-25gas: sparc: fix relaxation of CALL instruction into branches in a.out targetsJose E. Marchesi6-2/+69
This patch avoids CALL instructions to be optimized into branches if the symbols referred to in the CALL instruction are not fully resolved at the time the assembler writes its output. Tested in sparc64-linux-gnu and sparc-sun-sunos4.1.3 targets. No regressions. gas/ChangeLog: 2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com> PR gas/21407 * config/tc-sparc.c (md_apply_fix): Do not transform `call' instructions into branch instructions in fixups generating additional relocations. * testsuite/gas/sparc/call-relax.s: New file. * testsuite/gas/sparc/call-relax.d: Likewise. * testsuite/gas/sparc/call-relax-aout.d: Likewise. * testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
2017-04-24[GAS/ARM] Fix expansion of ldr pseudo instructionThomas Preud'homme4-24/+40
The LDR rX, =cst pseudo-instruction suffers from two issues for loading integer constants in Thumb mode: - movs is used if the constant and register can be encoded using that instruction which leads to unexpected behavior due to its flag-setting behavior - mov.w, movw and mvn are used for r13 (sp) and r15 (pc) but these encoding are marked as UNPREDICTABLE This patch fixes those issues and update testing accordingly. 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS. Forbid MOV.W and MOVW if destination is SP or PC. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain expectation of LDR not generating a MOVS for low registers and small constants. Add tests of MOVW generation. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update expected disassembly.
2017-04-22PowerPC VLE insn set additionsAlan Modra3-127/+140
opcodes/ * ppc-opc.c (ELEV): Define. (vle_opcodes): Add se_rfgi and e_sc. (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx for E200Z4. gas/ * testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc. * testsuite/gas/ppc/vle.d: Update.
2017-04-21Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and ↵Nick Clifton3-0/+29
LD4R. PR binutils/21380 opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, LD3R and LD4R. gas * testsuite/gas/aarch64/illegal-3.s: New file. * testsuite/gas/aarch64/illegal-3.d: New file.
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra3-3/+7
The -mhtm option is fairly useless too. include/ * opcode/ppc.h (PPC_OPCODE_HTM): Delete. gas/ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm. * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm". * ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.
2017-04-10gas: xtensa: fix incorrect code generated with auto litpoolsMax Filippov8-32/+95
* config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag): Initialize lps->frag_count with auto_litpool_limit. (xg_promote_candidate_litpool): New function. (xtensa_move_literals): Extract candidate litpool promotion code into separate function. Call it for all possible found candidates. (xtensa_switch_to_literal_fragment): Drop 'recursive' flag and call to xtensa_mark_literal_pool_location that it guards. Replace it with call to xtensa_maybe_create_literal_pool_frag. Initialize pool_location with created literal pool candidate. * testsuite/gas/xtensa/all.exp: Add new tests. * testsuite/gas/xtensa/auto-litpools-first1.d: New test results. * testsuite/gas/xtensa/auto-litpools-first1.s: New test. * testsuite/gas/xtensa/auto-litpools-first2.d: New test results. * testsuite/gas/xtensa/auto-litpools-first2.s: New test. * testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due to additional jump instruction.
2017-04-07Remove E6500 insns from PPC_OPCODE_ALTIVEC2Alan Modra3-163/+72
This isn't losing anything from the testsuite. All of these insns appear in testsuite/gas/ppc/e6500.s opcodes/ * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only vector instructions with E6500 not PPCVEC2. gas/ * testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns. * testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07MBIND gas test tweakAlan Modra2-2/+7
score-elf aligns text sections. * testsuite/gas/elf/section12a.d: Don't expect alignment of 1 for .mbind.text.
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet9-38/+78
include * dis-asm.h: Add prototypes for wasm32 disassembler. opcodes * Makefile.am: Add wasm32-dis.c. * configure.ac: Add wasm32-dis.c to wasm32 target. * disassemble.c: Add wasm32 disassembler code. * wasm32-dis.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. * po/opcodes.pot: Regenerate. gas * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler changes. * testsuite/gas/wasm32/disass.d: New test. * testsuite/gas/wasm32/disass.s: New test. * testsuite/gas/wasm32/disass-2.d: New test. * testsuite/gas/wasm32/disass-2.s: New test. * testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc names. * testsuite/gas/wasm32/reloc.s: Update test for changed assembler syntax. * testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn test to succeed.
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu21-25/+222
Mark an ALLOC section, which should be placed in special memory area, with SHF_GNU_MBIND. Its sh_info field indicates the special memory type. GNU_MBIND section names start with ".mbind" so that they are placed as orphan sections by linker. All input GNU_MBIND sections with the same sh_type, sh_flags and sh_info are placed in one output GNU_MBIND section. In executable and shared object, create a GNU_MBIND segment for each GNU_MBIND section and its segment type is PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is aligned at page boundary. The assembler syntax: .section .mbind.foo,"adx",%progbits ^ 0: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.foo,"adx",%progbits,0x1 ^ 1: Special memory type. | 'd' for SHF_GNU_MBIND. .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2 ^ 2: Special memory type. | 'd' for SHF_GNU_MBIND. bfd/ * elf.c (get_program_header_size): Add a GNU_MBIND segment for each GNU_MBIND section and align GNU_MBIND section to page size. (_bfd_elf_map_sections_to_segments): Create a GNU_MBIND segment for each GNU_MBIND section. (_bfd_elf_init_private_section_data): Copy sh_info from input for GNU_MBIND section. binutils/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX. (get_elf_section_flags): Handle SHF_GNU_MBIND. (process_section_headers): Likewise. * testsuite/binutils-all/mbind1.s: New file. * testsuite/binutils-all/objcopy.exp: Run readelf test on mbind1.s. gas/ * NEWS: Mention support for ELF SHF_GNU_MBIND. * config/obj-elf.c (section_match): New. (get_section): Match both sh_info and group name. (obj_elf_change_section): Add argument for sh_info. Pass both sh_info and group name to get_section. Issue an error for SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info. (obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'. (obj_elf_section): Support SHF_GNU_MBIND section info. * config/obj-elf.h (obj_elf_change_section): Add argument for sh_info. * config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texinfo: Document 'd' for SHF_GNU_MBIND. * testsuite/gas/elf/elf.exp: Run section12a, section12b and section13. * testsuite/gas/elf/section10.d: Updated. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section12.s: New file. * testsuite/gas/elf/section12a.d: Likewise. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.l: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.s: Likewise. include/ * elf/common.h (PT_GNU_MBIND_NUM): New. (PT_GNU_MBIND_LO): Likewise. (PT_GNU_MBIND_HI): Likewise. (SHF_GNU_MBIND): Likewise. ld/ * NEWS: Mention support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX. * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place input GNU_MBIND sections with the same type, attributes and sh_info field into a single output GNU_MBIND section. * testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b. * testsuite/ld-elf/mbind1.s: New file. * testsuite/ld-elf/mbind1a.d: Likewise. * testsuite/ld-elf/mbind1b.d: Likewise. * testsuite/ld-elf/mbind1c.d: Likewise. * testsuite/ld-elf/mbind2a.s: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-03RISC-V: Avoid a const warningPalmer Dabbelt2-1/+6
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to avoid const warnings.
2017-04-03 IA16 supportAndrew Jenner1-0/+3
* config.sub: Handle ia16 in $basic_machine. bfd/ * config.bfd: Handle ia16. gas/ * configure.tgt: Handle ia16. ld/ * configure.tgt: Handle ia16.
2017-03-31RISC-V: Allow ISA subsets to be disabledPalmer Dabbelt2-0/+21
Without this patch, passing "-march=rv64ic -march=rv64i" results in you getting a "RV64IC" toolchain, which isn't expected. gas/ChangeLog: 2017-03-30 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_clear_subsets): New function. (riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to clear RVC when it's been previously set.
2017-03-31Reduce the size of s390 symbol tables by allowing relocations in mergeable ↵Nick Clifton2-2/+10
string sections (eg .debug_str) to be made section relative rather than symbol relative. PR gas/21333 * config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative fixups in mergeable sections to be adjusted.
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ↵Pip Cet64-1662/+3502
gas and the binutils. binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate.
2017-03-29PowerPC -Mraw disassemblyAlan Modra2-1/+6
This adds -Mraw for PowerPC objdump, a disassembler option to display the underlying machine instruction rather than aliases. For example, "rlwinm" always rather than "rotlwi" when the instruction is performing a simple rotate. binutils/ * doc/binutils.texi (objdump): Document PowerPC -M options. gas/ * config/tc-ppc.c (md_parse_option): Reject -mraw. include/ * opcode/ppc.h (PPC_OPCODE_RAW): Define. (PPC_OPCODE_*): Make them all unsigned long long constants. opcodes/ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add "raw" option. (lookup_powerpc): Don't special case -1 dialect. Handle PPC_OPCODE_RAW. (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first lookup_powerpc call, pass it on second.
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra4-0/+25
PR 21303 opcodes/ * ppc-dis.c (struct ppc_mopt): Comment. (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. gas/ * testsuite/gas/ppc/pr21303.d, * testsuite/gas/ppc/pr21303.s: New test * testsuite/gas/ppc/ppc.exp: Run it.
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig3-0/+135
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL. (insert_nps_misc_imm_offset): New function. (extract_nps_misc imm_offset): New function. (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class. gas * testsuite/gas/arc/nps400-12.s: New file. * testsuite/gas/arc/nps400-12.d: New file.
2017-03-24[GAS/ARM] Fix selected_cpu with default CPU and -mcpuThomas Preud'homme2-2/+7
When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or -march option, selected_cpu will be set to the default CPU. This means the -mcpu is ignored which is surprising behavior. This commit instead sets selected_cpu from the value passed to -mcpu/-march. 2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when CPU_DEFAULT is defined.
2017-03-22Sanitize RISC-V GAS help text, documentationPalmer Dabbelt3-7/+17
It looks like I missed the GAS help text when going through all the documentation last time, so it printed some of the old-format (never upstream) arguments. I fixed this, and when I went to check doc/ I noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-22gas: xtensa: make trampolines relaxation work with jumps in slots other than 0Max Filippov2-4/+25
add_jump_to_trampoline assumes that jump instruction is in slot 0, when it's in other slot that results in fixup that references NULL symbol, which results in segfault later in xtensa_make_cached_fixup. Search for the non-NULL symbol in the tc_frag_data.slot_symbols and check that there's exactly one such slot. xtensa_relax_frag for RELAX_TRAMPOLINE reassigns fixup from the original instruction with jump to generated jump in the trampoline frag, but does not fix its fx_r_type or fx_size. That results in "undecodable fix" or "fixup not contained within frag" error messages during relaxation. Fix both these fields. gas/ 2017-03-22 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the reassigned fixup to size of jump instruction (3) and fx_r_type to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot. (add_jump_to_trampoline): Search origfrag->tc_frag_data.slot_symbols for the slot with non-NULL symbol and use that slot instead of slot 0.
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel2-4/+7
This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags.
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig3-0/+616
Instructions for loading or storing 16/32B data from one address type to another. gas/ChangeLog * testsuite/gas/arc/nps400-11.s: New file. * testsuite/gas/arc/nps400-11.d: New file. include/ChangeLog * opcode/arc.h (insn_class_t): Add DMA class. opcodes/ChangeLog * arc-nps400-tbl.h: Add cp32/cp16 instructions format. * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. (insert_nps_imm_offset): New function. (extract_nps_imm_offset): New function. (insert_nps_imm_entry): New function. (extract_nps_imm_entry): New function.
2017-03-20Update descriptions of the .2byte, .4byte and .8byte directives.Nick Clifton2-14/+28
* doc/as.texinfo (2byte): Note that if no expressions are present the directive does nothing. Emphasize that the output is unaligned, and that this can have an effect on the relocations generated. (4byte): Simplify description. Refer back to the 2byte description. (8byte): Likewise.
2017-03-20[arm] Document missing -mfpu entries.Richard Earnshaw3-4/+13
Nick pointed out that I hadn't documented the new -mfpu option neon-vfpv3 and mentioned that some others were missing. Having looked through the list only one (neon-fp16) really should be documented; the other two entries in the real table should not be documented as they are aliases kept for legacy compatibility reasons. This patch adds the missing entries and notes in the main table that the other two entries should not be documented. I've also fixed a small spelling error in the accompanying text. * config/tc-arm.c (arm_fpus): Note entires that should not be documented. * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and neon-fp16. Fix spelling error.
2017-03-20[arm] Add neon-vfp3 as an alias for neon to -mfpu.Richard Earnshaw2-0/+5
GCC recently added neon-vfpv3 as an alias for neon in -mfpu. This patch adds a similar alias in GAS. * config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-03-16gas/arc: Limit special handling of t/nt flag to ARCv2Rinat Zelig2-5/+18
In a later commit I'll be adding a new version of the ".nt" flag for an ARC700 extension (NPS400) which does not require this same special handling. In this commit I have restricted the special flag handling to only apply if we are assembling for ARCv2. This is a restructuring commit, and there should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt" specially for ARCv2.
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2-0/+14
- They can accept 0 in imm field 2017-03-14 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. <c.andi>: Likewise. <c.addiw> Likewise.
2017-03-15Fix building riscv targets with gcc v6.3.1Nick Clifton2-1/+6
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time warning about discarding a const qualifier.
2017-03-14RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.Kuan-Lin Chen2-0/+7
gas/ChangeLog 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-14RISC-V: Fix DW_CFA_advance_loc relocation.Kuan-Lin Chen2-0/+7
gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Set fx_frag and fx_next->fx_frag for CFA_advance_loc relocations.
2017-03-14RISC-V: Fix the offset of CFA relocation.Kuan-Lin Chen2-10/+15
gas/ChangeLog: 2017-03-02 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix): Compute the correct offsets for CFA relocations.
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and ↵Nick Clifton3-8/+20
R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12. PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-10Document that the .2byte and .4byte directives warn about overlarge values.Nick Clifton2-10/+22
* doc/as.texinfo (2byte): Tidy up wording. Add note that overlarge values will produce a warning message and be trunacted. (4byte): Likewise.
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu8-48/+418
Many x86 instructions have more than one encodings. Assembler picks the default one, usually the shortest one. Although the ".s", ".d8" and ".d32" suffixes can be used to swap register operands or specify displacement size, they aren't very flexible. This patch adds pseudo prefixes, {xxx}, to control instruction encoding. The available pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and ".d32" suffixes, which are deprecated. gas/ * config/tc-i386.c (_i386_insn): Add dir_encoding and vec_encoding. Remove swap_operand and need_vrex. (extra_symbol_chars): Add '}'. (md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in mnemonic. (build_vex_prefix): Don't use 2-byte VEX encoding with {vex3}. Check dir_encoding and load. (parse_insn): Check pseudo prefixes. Set dir_encoding. (VEX_check_operands): Likewise. (match_template): Check dir_encoding and load. (parse_real_register): Set vec_encoding instead of need_vrex. (parse_register): Likewise. * doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32" * testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos. * testsuite/gas/i386/pseudos.d: New file. * testsuite/gas/i386/pseudos.s: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace S with Load. * i386-opc.h (S): Removed. (Load): New. (i386_opcode_modifier): Replace s with load. * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} and {evex}. Replace S with Load. * i386-tbl.h: Regenerated.
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner2-2/+7
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec and vsx instructions respecitively that have ever been added. This is in constract to GCC's -maltivec and -mvsx options, which only enable the oldest (ie, first) set of altivec and vsx instructions. This patch changes GAS to mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a problem with trying to assemble the lxvx instruction which is different between POWER8 and POWER9. opcodes/ * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; <vsx>: Do not use PPC_OPCODE_VSX3; gas/ * testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option. (objdump): Use the -Mpower8 option.
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner3-2/+9
opcodes/ * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. gas/ * testsuite/gas/ppc/power9.d <lnia> New test. * testsuite/gas/ppc/power9.s: Likewise.
2017-03-07Correct @section placement for makeinfo 4.13Alan Modra2-3/+7
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
2017-03-07Document .Nbyte assembler directivesAlan Modra3-0/+46
* doc/as.texinfo (2byte, 4byte, 8byte): Document. * doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
2017-03-06Add support for Intel CET instructionsH.J. Lu10-0/+213
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-03-06Update x86-64-mpx-inval-2 test for COFFH.J. Lu3-4/+12
Assembler displays upper case hex numbers and we need to force a good alignment to avoid matching NOPs at the end. * testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment. * testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
generated by cgit v1.1 at 2024-11-19 20:39:16 +0000