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2021-09-06Fix potential use on an uninitialised vairable in the MCore assembler.Nick Clifton1-3/+6
2021-09-06Fix potential uninitialised variable in microblaze assembler code.Nick Clifton1-1/+1
2021-09-02Add support for the haiku operating system. These are the os support ↵Alexander von Gluck IV4-1/+40
patches we have been grooming and maintaining for quite a few years over on git.haiku-os.org. All of these architectures are working and most have been stable for quite some time.
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton4-24/+34
PR 28292 gas * config/tc-v850.c (handle_lo16): Also accept BFD_RELOC_V850_LO16_SPLIT_OFFSET. * testsuite/gas/v850/split-lo16.s: Add extra line. * testsuite/gas/v850/split-lo16.d: Update expected disassembly. opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place of BFD_RELOC_16.
2021-08-31RISC-V: Extend .insn directive to support hardcode encoding.Nelson Chu7-5/+96
The .insn directive can let users use their own instructions, or some new instruction, which haven't supported in the old binutils. For example, if users want to use sifive cache instruction, they cannot just write "cflush.d1.l1" in the assembly code, they should use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive may not easy to use for some cases, and not so friendly to users. Therefore, I believe most of the users will use ".word 0xfc050073", to encode the instructions directly, rather than use .insn. But once we have supported the mapping symbols, the .word directives are marked as data, so disassembler won't dump them as instructions as usual. I have discussed this with Kito many times, we all think extend the .insn direcitve to support the hardcode encoding, is the easiest way to resolve the problem. Therefore, there are two more .insn formats are proposed as follows, (original) .insn <type>, <operand1>, <operand2>, ... .insn <insn-length>, <value> .insn <value> The <type> is string, and the <insn-length> and <value> are constants. gas/ * config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip, but assembles an instruction according to the hardcode values of .insn directive. * doc/c-riscv.texi: Document two new .insn formats. * testsuite/gas/riscv/insn-fail.d: New testcases. * testsuite/gas/riscv/insn-fail.l: Likewise. * testsuite/gas/riscv/insn-fail.s: Likewise. * testsuite/gas/riscv/insn.d: Updated. * testsuite/gas/riscv/insn.s: Likewise.
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu19-2/+516
Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-0/+1
Put back 3 aborts where invalid lengths should have been filtered out. gas/ PR binutils/28247 * testsuite/gas/i386/bad-bcast.s: Add a comment. opcodes/ PR binutils/28247 * * i386-dis.c (OP_E_memory): Put back 3 aborts.
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu3-0/+17
Print "{bad}" on invalid broadcast instead of abort. gas/ PR binutils/28247 * testsuite/gas/i386/bad-bcast.d: New file. * testsuite/gas/i386/bad-bcast.s: Likewise. * testsuite/gas/i386/i386.exp: Run bad-bcast. opcodes/ PR binutils/28247 * i386-dis.c (OP_E_memory): Print "{bad}" on invalid broadcast instead of abort.
2021-08-18Re: as: Replace the removed symbol with the versioned symbolAlan Modra1-2/+2
Some targets, typically embedded without shared libraries, replace the relocation symbol with a section symbol (see tc_fix_adjustable). Allow the test to pass for such targets. Fixes the following. avr-elf +FAIL: symver symver16 d10v-elf +FAIL: symver symver16 dlx-elf +FAIL: symver symver16 ip2k-elf +FAIL: symver symver16 m68k-elf +FAIL: symver symver16 mcore-elf +FAIL: symver symver16 pj-elf +FAIL: symver symver16 s12z-elf +FAIL: symver symver16 visium-elf +FAIL: symver symver16 z80-elf +FAIL: symver symver16 PR gas/28157 * testsuite/gas/symver/symver16.d: Relax reloc match.
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PACRET_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PACRET_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PACRET_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PAC_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PAC_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PAC_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PAC_extension'.
2021-08-17x86: Always run fp testsH.J. Lu4-208/+1
Always run fp tests since the size of .tfloat, .ds.x, .dc.x and .dcb.x directive outputs is always 10 bytes. There is no need for fp-elf32 nor fp-elf64. PR gas/28230 * testsuite/gas/i386/fp-elf32.d: Removed. * testsuite/gas/i386/fp-elf64.d: Likewise. * testsuite/gas/i386/fp.s: Remove NO_TFLOAT_PADDING codes. * testsuite/gas/i386/i386.exp: Don't run fp-elf32 nor fp-elf64. Always run fp.
2021-08-16x86: Don't pad .tfloat directive outputH.J. Lu5-15/+127
.tfloat output should always be 10 bytes without padding, independent of psABIs. In glibc, x86 assembly codes expect 10-byte .tfloat output. This also reduces .ds.x output and .tfloat output with hex input from 12 bytes to 10 bytes to match .tfloat output. PR gas/28230 * NEWS: Mention changes of .ds.x output and .tfloat output with hex input. * config/tc-i386.c (x86_tfloat_pad): Removed. * config/tc-i386.h (X_PRECISION_PAD): Changed to 0. (x86_tfloat_pad): Removed. * testsuite/gas/i386/fp.s: If NO_TFLOAT_PADDING isn't defined, add explicit paddings after .tfloat, .ds.x, .dc.x and .dcb.x directives. * testsuite/gas/i386/i386.exp (ASFLAGS): Append "--defsym NO_TFLOAT_PADDING=1" when running the fp test.
2021-08-16as: Replace the removed symbol with the versioned symbolH.J. Lu8-10/+103
When a symbol removed by .symver is used in relocation and there is one and only one versioned symbol, don't remove the symbol. Instead, mark it to be removed and replace the removed symbol used in relocation with the versioned symbol before generating relocation. PR gas/28157 * symbols.c (symbol_flags): Add removed. (symbol_entry_find): Updated. (symbol_mark_removed): New function. (symbol_removed_p): Likewise. * symbols.h (symbol_mark_removed): New prototype. (symbol_removed_p): Likewise. * write.c (write_relocs): Call obj_fixup_removed_symbol on removed fixp->fx_addsy and fixp->fx_subsy if defined. (set_symtab): Don't add a symbol if symbol_removed_p returns true. * config/obj-elf.c (elf_frob_symbol): Don't remove the symbol if it is used on relocation. Instead, mark it as to be removed and issue an error if the symbol has more than one versioned name. (elf_fixup_removed_symbol): New function. * config/obj-elf.h (elf_fixup_removed_symbol): New prototype. (obj_fixup_removed_symbol): New. * testsuite/gas/symver/symver11.d: Updated expected error message. * testsuite/gas/symver/symver16.d: New file. * testsuite/gas/symver/symver16.s: Likewise.
2021-08-13PR28168: [CSKY] Fix stack overflow in disassemblerLifang Xia3-8/+21
PR 28168: Stack overflow with a large float. %f is not a goot choice for this. %f should be replaced with %.7g. gas/ * testsuite/gas/csky/pr28168.d: New testcase for PR 28168. * testsuite/gas/csky/pr28168.s: Likewise. * testsuite/gas/csky/v2_float_part2.d: Following the new format. * opcodes/csky-dis.c (csky_output_operand): %.7g replaces %f.
2021-08-12Re: gas: support NaN flavorsAlan Modra2-1/+10
Fixes tic4x-coff FAIL: simple FP constants * testsuite/gas/all/float.s: Make NaN tests conditional on hasnan. * testsuite/gas/all/gas.exp: Define hasnan.
2021-08-11Fix a typo in the RX asse,bler. The Double-precision floating-point ↵Darius Galis5-4/+11
exception handling control register name is DECNT not DCENT. * config/rx-parse.y (DECNT): Fixed typo. * testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo. * testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo. * testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
2021-08-11Fix an internal error in the CSKY assembler when asked to resolve an ↵Nick Clifton2-1/+8
overlarge constant. PR 28215 * config/tc-csky.c (md_apply_fix): Correctly handle a fixup that involves an overlarge constant.
2021-08-11Deprecate a.out support for NetBSD targets.John Ericson5-1704/+1694
As discussed previously, a.out support is now quite deprecated, and in some cases removed, in both Binutils itself and NetBSD, so this legacy default makes little sense. `netbsdelf*` and `netbsdaout*` still work allowing the user to be explicit about there choice. Additionally, the configure script warns about the change as Nick Clifton requested. One possible concern was the status of NetBSD on NS32K, where only a.out was supported. But per [1] NetBSD has removed support, and if it were to come back, it would be with ELF. The binutils implementation is therefore marked obsolete, per the instructions in the last message. With that patch and this one applied, I have confirmed the following: --target=i686-unknown-netbsd --target=i686-unknown-netbsdelf builds completely --target=i686-unknown-netbsdaout properly fails because target is deprecated. --target=vax-unknown-netbsdaout builds completely except for gas, where the target is deprecated. [1]: https://mail-index.netbsd.org/tech-toolchain/2021/07/19/msg004025.html --- bfd/config.bfd | 43 +++++++++++++-------- bfd/configure.ac | 5 +-- binutils/testsuite/binutils-all/nm.exp | 2 +- binutils/testsuite/lib/binutils-common.exp | 7 +--- config/picflag.m4 | 4 +- gas/configure.tgt | 9 +++-- gas/testsuite/gas/arm/blx-bl-convert.d | 2 +- gas/testsuite/gas/arm/blx-local-thumb.d | 2 +- gas/testsuite/gas/sh/basic.exp | 2 +- gdb/configure.host | 34 +++++++---------- gdb/configure.tgt | 2 +- gdb/testsuite/gdb.asm/asm-source.exp | 6 +-- intl/configure | 2 +- ld/configure.tgt | 44 +++++++++++----------- ld/testsuite/ld-arm/arm-elf.exp | 4 +- ld/testsuite/ld-elf/elf.exp | 2 +- ld/testsuite/ld-elf/shared.exp | 4 +- libiberty/configure | 4 +-
2021-08-11Add a -mno-dollar-line-separator command line option to the AVR assembler.Matt Jacobson4-4/+33
Some frontends, like the gcc Objective-C frontend, emit symbols with $ characters in them. The AVR target code in gas treats $ as a line separator, so the code doesn?t assemble correctly. Provide a machine-specific option to disable treating $ as a line separator. * config/tc-avr.c (enum options): Add option flag. (struct option): Add option -mno-dollar-line-separator. (md_parse_option): Adjust treatment of $ when option is present. * config/tc-avr.h: Use avr_line_separator_chars.
2021-08-11Fix typo in previous deltaNick Clifton2-2/+6
2021-08-11gas: fold IEEE encoding of -Inf with that of +InfJan Beulich1-42/+3
The respective results differ only by the sign bits - there's no need to have basically identical (partially even arch-specific) logic twice. Simply set the sign bit at the end of encoding the various formats.
2021-08-11gas: support NaN flavorsJan Beulich9-18/+221
Like for infinity, there isn't just a single NaN. The sign bit may be of interest and, going beyond infinity, whether the value is quiet or signalling may be even more relevant to be able to encode. Note that an anomaly with x86'es double extended precision NaN values gets taken care of at the same time: For all other formats a positive value with all mantissa bits set was used, while here a negative value with all non-significant mantissa bits clear was chose for an unknown reason. For m68k, since I don't know their X_PRECISION floating point value layout, a warning gets issued if any of the new flavors was attempted to be encoded that way. However likely it may be that, given that the code lives in a source file supposedly implementing IEEE-compliant formats, the bit patterns of the individual words match x86'es, I didn't want to guess so. And my very, very old paper doc doesn't even mention floating point formats other than single and double.
2021-08-11Arm64: leave .bfloat16 processing to common codeJan Beulich1-49/+1
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11Arm32: leave more .bfloat16 processing to common codeJan Beulich1-46/+3
With x86 support having been implemented by extending atof-ieee.c, avoid unnecessary code duplication in md_atof(). This will then also allow to take advantage of adjustments made there without needing to mirror them here.
2021-08-11gas: make 2nd argument of .dcb.* consistently optionalJan Beulich2-55/+78
Unlike the forms consuming/producing integer data, the floating point ones so far required the 2nd argument to be present, contrary to documentation. To avoid code duplication, split float_length() out of hex_float() (taking the opportunity to adjust error message wording).
2021-08-11x86: introduce .bfloat16 directiveJan Beulich8-14/+32
This is to be able to generate data acted upon by AVX512-BF16 and AMX-BF16 insns. While not part of the IEEE standard, the format is sufficiently standardized to warrant handling in config/atof-ieee.c. Arm, where custom handling was implemented, may want to leverage this as well. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86: introduce .hfloat directiveJan Beulich7-6/+21
This is to be able to generate data passed to {,V}CVTPH2PS and acted upon by AVX512-FP16 insns. To be able to also use the hex forms supported for other floating point formats, a small addition to the generic hex_float() is needed. Extend existing x86 testcases.
2021-08-11x86/ELF: fix .tfloat output with hex inputJan Beulich5-4/+29
The ELF psABI-s are quite clear here: On 32-bit the data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make hex_float() capable of handling such padding. Note that this brings the emitted data size of .dc.x / .dcb.x in line also for non-ELF targets; so far they were different depending on input format (dec vs hex). Extend the existing x86 testcases.
2021-08-11x86/ELF: fix .ds.x outputJan Beulich7-7/+38
The ELF psABI-s are quite clear here: On 32-bit the underlying data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make s_space() capable of handling 'x' (and 'p') type floating point being other than 12 bytes wide (also adjusting documentation). This requires duplicating the definition of X_PRECISION in the target speciifc header; the compiler would complain if this was out of sync with config/atof-ieee.c. Note that for now padding space doesn't get separated from actual storage, which means that things will work correctly only for little- endian cases, and which also means that by specifying large enough numbers padding space can be set to non-zero. Since the logic is needed for a single little-endian architecture only for now, I'm hoping that this might be acceptable for the time being; otherwise the change will become more intrusive. Note also that this brings the emitted data size of .ds.x vs .tfloat in line for non-ELF targets as well; the issue will be even more obvious when further taking into account a subsequent patch fixing .dc.x/.dcb.x (where output sizes currently differ depending on input format). Extend existing x86 testcases.
2021-08-11x86/ELF: fix .tfloat outputJan Beulich7-6/+60
The ELF psABI-s are quite clear here: On 32-bit the data type is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16 bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of handling such padding, and specify the needed padding for x86 (leaving non-ELF targets alone for now). Split the existing x86 testcase.
2021-08-10Updated Serbian and Russian translations for various sub-directoriesNick Clifton2-4241/+4330
2021-08-09GAS: DWARF-5: Ensure that the 0'th entry in the directory table contains the ↵Nick Clifton8-18/+91
current working directory. * dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0] contains current working directory. (out_dir_and_file_list): Likewise. * testsuite/gas/elf/dwarf-5-dir0.s: New test source file. * testsuite/gas/elf/dwarf-5-dir0.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output. * testsuite/gas/i386/dwarf5-line-1.d: Likewise. * testsuite/gas/i386/dwarf5-line-2.d: Likewise.
2021-08-06Re: Add tests for Intel AVX512_FP16 instructionsAlan Modra1-0/+1
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Pass with mingw section padding.
2021-08-05[PATCH 2/2] Add tests for Intel AVX512_FP16 instructionsCui,Lili30-0/+26033
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * testsuite/gas/i386/i386.exp: Run FP16 tests. * testsuite/gas/i386/avx512_fp16-intel.d: New test. * testsuite/gas/i386/avx512_fp16-inval-bcast.l: Ditto. * testsuite/gas/i386/avx512_fp16-inval-bcast.s: Ditto. * testsuite/gas/i386/avx512_fp16.d: Ditto. * testsuite/gas/i386/avx512_fp16.s: Ditto. * testsuite/gas/i386/avx512_fp16_pseudo_ops.d: Ditto. * testsuite/gas/i386/avx512_fp16_pseudo_ops.s: Ditto. * testsuite/gas/i386/avx512_fp16_vl-intel.d: Ditto. * testsuite/gas/i386/avx512_fp16_vl.d: Ditto. * testsuite/gas/i386/avx512_fp16_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.l: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-register.l: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-inval-register.s: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-bad.d: Ditto. * testsuite/gas/i386/x86-64-avx512_fp16-bad.s: Ditto. * testsuite/gas/i386/x86-64-default-suffix-avx.d: Add new testcase. * testsuite/gas/i386/x86-64-default-suffix.d: Ditto. * testsuite/gas/i386/x86-64-default-suffix.s: Ditto. * testsuite/gas/i386/xmmword.l: Ditto. * testsuite/gas/i386/xmmword.s: Ditto.
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili3-4/+47
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-2/+2
opcodes/ * s390-opc.c (INSTR_SIY_RD): New instruction format. (MASK_SIY_RD): New instruction mask. * s390-opc.txt: Change instruction format of lpswey to SIY_RD. gas/ * testsuite/gas/s390/zarch-arch14.d: Remove last operand of lpswey. * testsuite/gas/s390/zarch-arch14.s: Likewise.
2021-08-04gas: correctly output XCOFF tbss symbols with XTY_CM type.Clément Chigot1-1/+2
Global tbss symbols weren't correctly handled and were generating a symbol with XTY_SD instead of XTY_CM as expected. gas/ * config/tc-ppc.c (ppc_frog_symbol): Generate a XTY_CM when a symbol has a storage class of XMC_UL.
2021-08-04gas: always add dummy symbols when creating XCOFF sections.Clément Chigot1-17/+11
Most of the algorithms for XCOFF in tc-ppc.c assume that the csects field of a ppc_xcoff_section isn't NULL. This was already made for most of the sections with the creation of a dummy symbol. This patch simply mades it default when creating a xcoff_section. gas/ * config/tc-ppc.c (ppc_init_xcoff_section): Always create the dummy symbol. (md_begin): Adjust ppc_init_xcoff_section call. (ppc_comm): Likewise. (ppc_change_csect): Likewise.
2021-07-30gas: ensure XCOFF DWARF subsection are initialized to 0Clément Chigot1-1/+1
debug_abbrev doesn't use end_exp to compute its size. However, it must be NULL. Otherwise, ppc_xcoff_end might try to access uninitialized memory. gas/ * config/tc-ppc.c (ppc_dwsect): Use XCNEW instead of XNEW when creating a new subsection.
2021-07-29gas: improve C_BSTAT and C_STSYM symbols handling on XCOFFClément Chigot7-3/+81
A C_BSTAT debug symbol specifies the beginning of a static block. Its n_value is the index of the csect containing static symbols. A C_STSYM debug symbol represents the stabstring of a statically allocated symbol. Its n_value is the offset in the csect pointed by the containing C_BSTAT. These two special n_value were not correctly handled both when generating object files with gas or when reading them with objdump. This patch tries to improve that and, above all, to allow gas-generated object files with such symbols to be accepted by AIX ld. bfd/ * coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols having fix_value = 1 in order to be an index and not a memory offset. * coffgen.c (coff_get_symbol_info): Likewize. (coff_print_symbol): Likewize. gas/ * config/tc-ppc.c (ppc_frob_label): Don't change within if already set. (ppc_stabx): Remove workaround changing exp.X_add_symbol's within. * config/tc-ppc.h (struct ppc_tc_sy): Update comments. * symbols.c (resolve_symbol_value): Remove symbol update when final_val is 0 and it's an AIX debug symbol. * testsuite/gas/ppc/aix.exp: Add new tests. * testsuite/gas/ppc/xcoff-stsym-32.d: New test. * testsuite/gas/ppc/xcoff-stsym-64.d: New test. * testsuite/gas/ppc/xcoff-stsym.s: New test.
2021-07-28x86: Simplify check for distinct TMM register operandsH.J. Lu1-15/+10
If any pair of operands in AMX instructions with 3 TMM register operands are the same, the instruction will UD. Don't call register_number to check for distinct TMM register operands since all TMM register operands have the same size. * config/tc-i386.c (check_VecOperands): Remove register_number call when checking for distinct TMM register operands.
2021-07-28PowerPC: ignore sticky options for .machineAlan Modra1-4/+16
PowerPC gas and objdump for a long time have allowed certain -m/-M options that extend a base cpu with extra functional units to be specified before the base cpu. For example, "-maltivec -mpower4" is the same as "-mpower4 -maltivec". See https://sourceware.org/pipermail/binutils/2008-January/054935.html It doesn't make as much sense that .machine keep any of these "sticky" flags when handling a new base cpu. See gcc PR101393. I think that instead .machine ought to override the command line. That's what this patch does. It is still possible to extend cpu functionality with .machine. For example the following can be assembled when selecting a basic -mppc on the command line: .machine power5 .machine altivec frin 1,2 lvsr 3,4,5 Here, ".machine altivec" extends the ".machine power5" so that both the power5 "frin" instruction and the altivec "lvsr" instruction are enabled. Swapping the two ".machine" directives would result in failure to assemble "lvsr". This change will expose some assembly errors, such as the one in glibc/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c, a file compiled with -maltivec but containing asm volatile (".machine push;\n" ".machine \"power5\";\n" "vspltisb %0,0;\n" "vspltisb %1,-1;\n" "vpkuwus %0,%0,%1;\n" "mfvscr %0;\n" "stvx %0,0,%2;\n" ".machine pop;" : "=v" (v0), "=v" (v1) : "r" (vscr_ptr) : "memory"); It's just wrong to choose power5 for a bunch of altivec instructions and in fact all of those .machine directives are unnecessary. * config/tc-ppc.c (ppc_machine): Don't use command line sticky options.
2021-07-26PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.Andrea Corallo1-0/+3
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (reg_names): Alias 'ra_auth_code' to r12.
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+16
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pacg'. (do_t_pacbti_pacg): New function. (insns): Define 'pacg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacg'.
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-0/+4
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_autg'. (insns): Define 'autg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'autg'.
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo3-1/+17
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_bxaut'. (do_t_pacbti_nonop): New function. (insns): Define 'bxaut' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'bxaut'.
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+4
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (pacbti_ext): Define. (BAD_PACBTI): New macro. (armv8_1m_main_ext_table): Add 'pacbti' extension. include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New macro.
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