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2019-12-17Remove tic80 supportAlan Modra2-1/+5
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-12i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu5-3/+25
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX prefix for the low byte register when optimizing test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 PR gas/25274 * config/tc-i386.c (optimize_encoding): Also check R12-R15 registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8" optimization. * testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test with r12. * testsuite/gas/i386/x86-64-optimize-3.d: Updated. * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
2019-12-12i386: Add tests for -malign-branch-boundary and -malign-branchH.J. Lu55-0/+2616
Add tests for -malign-branch-boundary, -malign-branch and -mbranches-within-32B-boundaries. gas/ * testsuite/gas/i386/align-branch-1.s: New file. * testsuite/gas/i386/align-branch-1a.d: Likewise. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-2.s: Likewise. * testsuite/gas/i386/align-branch-2a.d: Likewise. * testsuite/gas/i386/align-branch-2b.d: Likewise. * testsuite/gas/i386/align-branch-2c.d: Likewise. * testsuite/gas/i386/align-branch-3.d: Likewise. * testsuite/gas/i386/align-branch-3.s: Likewise. * testsuite/gas/i386/align-branch-4.s: Likewise. * testsuite/gas/i386/align-branch-4a.d: Likewise. * testsuite/gas/i386/align-branch-4b.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/align-branch-5.s: Likewise. * testsuite/gas/i386/align-branch-6.d: Likewise. * testsuite/gas/i386/align-branch-6.s: Likewise. * testsuite/gas/i386/align-branch-7.d: Likewise. * testsuite/gas/i386/align-branch-7.s: Likewise. * testsuite/gas/i386/align-branch-8.d: Likewise. * testsuite/gas/i386/align-branch-8.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-1.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-2a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-3.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-3.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-4.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-4a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-4b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. ld/ * testsuite/ld-i386/align-branch-1.d: New file. * testsuite/ld-i386/align-branch-1.s: Likewise. * testsuite/ld-x86-64/align-branch-1.d: Likewise. * testsuite/ld-x86-64/align-branch-1.3: Likewise. * testsuite/ld-i386/i386.exp: Run the new test. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu3-0/+31
Add -mbranches-within-32B-boundaries to enable -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5 * config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New. (md_longopts): Add -mbranches-within-32B-boundaries. (md_parse_option): Handle -mbranches-within-32B-boundaries. (md_show_usage): Add -mbranches-within-32B-boundaries.
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu4-3/+1160
Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-12gas: Add md_generic_table_relax_fragH.J. Lu3-1/+18
Add md_generic_table_relax_frag for TC_GENERIC_RELAX_TABLE targets so that a backend can extend relax_frag beyond TC_GENERIC_RELAX_TABLE. * write.c (md_generic_table_relax_frag): New. Defined to relax_frag if not defined. (relax_segment): Call md_generic_table_relax_frag instead of relax_frag.
2019-12-12gas signed overflow fixesAlan Modra11-52/+68
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow. * config/tc-metag.c (parse_dalu): Likewise. * config/tc-tic4x.c (md_pcrel_from): Likewise. * config/tc-tic6x.c (tic6x_output_unwinding): Likewise. * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer. Don't use register keyword. Avoid signed overflow and remove now unneccesary char masks. Formatting. * config/tc-ia64.c (operand_match): Don't use shifts to sign extend. * config/tc-mep.c (mep_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (load_const): Likewise. * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16 calculation.
2019-12-12obj-evax.c tidyAlan Modra2-29/+35
This started out as fixing decode_16, which used a char to index a 256 byte decodings array. When char is signed that could result in an out of bounds array access. The rest of the patch is for consistency and just general cleanup. * config/obj-evax.c (crc32, encode_32, encode_16, decode_16): Remove unnecessary prototypes. (number_of_codings): Delete, use ARRAY_SIZE instead throughout. (codings, decodings): Make arrays of unsigned char. (crc32): Use unsigned variables. Delete unnecessary mask. (encode_32, encode_16): Return unsigned char*, and make static buffer an unsigned char array. (decode_16): Make arg an unsigned char*. Remove useless casts. (shorten_identifier): Use unsigned char crc_chars. (is_truncated_identifier): Make ptr an unsigned char*.
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira10-8/+29
Add a -m{no-}warn-restrict-it option to control IT related warnings in ARMv8-A and ARMv8-R. This is disabled by default. Committed on behalf of Wilco Dijkstra. gas/ChangeLog: 2019-12-11 Wilco Dijkstra <wdijkstr@arm.com> * config/tc-arm.c (warn_on_restrict_it): Add new variable. (it_fsm_post_encode): Check warn_on_restrict_it. (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise. * testsuite/gas/arm/armv8-a-bad.d: Likewise. * testsuite/gas/arm/armv8-a-it-bad.d: Likewise. * testsuite/gas/arm/armv8-r-bad.d: Likewise. * testsuite/gas/arm/armv8-r-it-bad.d: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise. * testsuite/gas/arm/udf.d: Likewise.
2019-12-11x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich7-25/+88
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went both a little too far and not quite far enough: - GFNI insns also have AVX512 variants, which also shouldn't get diagnosed, - SSE4a insns should get diagnosed just like SSE4.x ones, - SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira4-0/+20
This patch fixes .arch_extension behaviour. Currently, context table for '.arch_extension' is only set while "-march" processing, but it is not set while .arch processing, so following code is rejected .syntax unified .thumb .arch armv8.1-m.main .arch_extension mve.fp unless -march=armv8.1-m.main is given. Committing on behalf of Vladimir Murzin gas/ChangeLog: 2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com> * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table. * testsuite/gas/arm/mve-arch-ext.s: New. * testsuite/gas/arm/mve-arch-ext.d: New.
2019-12-09x86/Intel: fold "xmmword" with "oword"Jan Beulich2-11/+18
These are full aliases of one another, so there's no real need to use distinct O_md* values for them.
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich7-5/+23
This is an alias of "qword ptr", commonly used with MMX insns. At this occasion also test (alongside the newly supported "mmword") - "zmmword" used as expression, - PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich4-3/+24
Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") broke rejecting of these for floating point insns. Fix this by setting the "byte" operand attribute, which will now (again) cause an error. Furthermore the diagnostic for the "far ptr" case in general and for the "near ptr" case in the non-float cases became "invalid instruction suffix" instead of the intended "operand size mismatch". Fix this by also setting the "tbyte" operand attribute (no insn template accepts both byte and tbyte operands).
2019-12-09x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich2-10/+11
There are extremely few insns accepting "tbyte ptr" operand, so the "tbyte" operand flag checking done by match_operand_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Fold the code with that setting the "byte" operand flag to force an error (no insn at all accepts both "byte ptr" and tbyte ptr" operands, except for AnySize ones where the two (conflicting) recorded types don't matter (operand_size_match() doesn't call match_operand_size() in this case).
2019-12-09x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich2-2/+5
No floating point insn accepts an "fword ptr" operand, so the "fword" operand flag checking done by match_mem_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09x86/Intel: drop pointless special casing of LxSJan Beulich2-6/+6
LDS et al don't accept "word ptr" operands anyway, as per their insn templates. Hence there's no need to special case this here; the check has become dysfunctional anyway by dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-08aarch64*-*-*ilp32 gas testsAlan Modra14-36/+50
The new pac_negate_ra_state test adds yet another failure on aarch64 ipl32 targets. This patch fixes that particular problem and a few more that are trivial to fix. * testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output. * testsuite/gas/aarch64/dgh.d: Likewise. * testsuite/gas/aarch64/f32mm.d: Likewise. * testsuite/gas/aarch64/f64mm.d: Likewise. * testsuite/gas/aarch64/i8mm.d: Likewise. * testsuite/gas/aarch64/pac_ab_key.d: Likewise. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g1.d: Likewise. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise. * testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-12-06[gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov4-0/+53
This patch implements the .cfi_negate_ra_state to be consistent with LLVM (https://reviews.llvm.org/D50136). The relevant DWARF code DW_CFA_AARCH64_negate_ra_state is multiplexed on top of DW_CFA_GNU_window_save, as per https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00753.html I believe this is the simplest patch implementing this and is needed to allow users to build, for example, the Linux kernel with Armv8.3-A pointer authentication support with Clang while using gas as the assembler, which is a common usecase. gas/ 2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state. * testsuite/gas/aarch64/pac_negate_ra_state.s: New file. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-3/+6
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich7-45/+49
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the latter should not also disable the former. In the course of adding respective tests also do away with the duplication of crypto.d's contents in crypto-directive.d.
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich9-8/+90
Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich4-6/+31
While dc2be329b950 ("i386: Only check suffix in instruction mnemonic") has made the assembler accept these in the first place (they were wrongly rejected before), the generated code was still wrong in that it lacked an operand size override. (In 64-bit code, other than in 16- and 32-bit ones, CALL and JMP with memory operands are all entirely unambiguous: No operand size can have two meanings.)
2019-12-04x86: consolidate tracking of MMX register useJan Beulich2-9/+8
Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead include the two special insns (not having register operands) explicitly.
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich7-0/+23
Test also memory operands with operand size specifier, which was broken prior to dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), due to the template not permitting any suffixes. Note that this uncovered a disassembler issue, which is being fixed here as well.
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich4-8/+40
While segment registers are registers, their use doesn't allow sizing of insns without suffix / explicit operand size specifier. Prevent PUSH and POP of segment registers from entering that path, instead allowing them to observe the stackop_size setting just like other PUSH/POP and alike do.
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich4-9/+94
Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.)
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess6-4/+51
The flag controlling the default DWARF CIE version to produce now starts with the value -1. This can be modified with the command line flag as before, but after command line flag processing, in md_after_parse_args targets can, if the global still has the value -1, override this value. This gives a target specific default. If a CIE version is not select either by command line flag, or a target specific default, then some new code in dwarf2_init now select a global default. This remains as version 1 to match previous behaviour. This RISC-V has a target specific default of version provided, this make the return column uleb128, which means we can use all DWARF registers include CSRs. I chose to switch to version 3 rather than version 4 as this is most similar to the global default (version 1). Switching to version 4 adds additional columns to the CIE header. gas/ChangeLog: * as.c (flag_dwarf_cie_version): Change initial value to -1, and update comment. * config/tc-riscv.c (riscv_after_parse_args): Set flag_dwarf_cie_version if it has not already been set. * dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if needed. * testsuite/gas/riscv/default-cie-version.d: New file. * testsuite/gas/riscv/default-cie-version.s: New file. ld/ChangeLog: * testsuite/ld-elf/eh5.d: Accept version 3 DWARF CIE. Change-Id: Ibbfe8f0979fba480bf0a359978b09d2b3055555e
2019-11-28gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess5-1/+36
In version 1 of DWARF CIE format, the return register column is just a single byte. For targets with large numbers of DWARF registers, any use of a register with a high number for the return column will (currently) silently overflow giving incorrect DWARF. This commit adds an error when the overflow occurs. gas/ChangeLog: * dw2gencfi.c (output_cie): Error on return column overflow. * testsuite/gas/riscv/cie-rtn-col-1.d: New file. * testsuite/gas/riscv/cie-rtn-col-3.d: New file. * testsuite/gas/riscv/cie-rtn-col.s: New file. Change-Id: I1809f739ba7771737ec012807f0260e1a3ed5e64
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess4-0/+531
This commit gives DWARF register numbers to the RISC-V CSRs inline with the RISC-V ELF specification here: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md The CSRs are defined being numbered from 4096 to 8191. This adds support to the assembler, required in order to reference CSRs in, for example .cfi directives. I have then extended dwarf.c in order to support printing CSR names in the dumped DWARF output. As the CSR name space is quite large and only sparsely populated, I have provided a new function to perform RISC-V DWARF register name lookup which uses a switch statement rather than the table base approach that other architectures use. Any CSR that does not have a known name will return a name based on 'csr%d' with the %d being replaced by the offset of the CSR from 4096. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR names too. * testsuite/gas/riscv/csr-dw-regnums.d: New file. * testsuite/gas/riscv/csr-dw-regnums.s: New file. binutils/ChangeLog: * dwarf.c (regname_internal_riscv): New function. (init_dwarf_regnames_riscv): Use new function. Change-Id: I3f70bc24fa8b3c75744e6775eeeb87db70c7ecfb
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess2-7/+6
We build a hash table of all register classes and numbers. The hash key is the register name and the hash value is the class and number encoded into a single value, which is of type 'void *'. When we pull the values out of the hash we cast them to be a pointer to a structure, however, we never access the fields of that structure, we just decode the register class and number from the pointer value itself. This commit removes the structure and treats the encoded class and number as a 'void *' during hash lookup. gas/ChangeLog: * config/tc-riscv.c (struct regname): Delete. (hash_reg_names): Handle value as 'void *'. Change-Id: Ie7d8f46ca3798f56f4af94395279de684f87f9cc
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski7-3/+25
psb CYSNC was not finding that CSYNC was a correct spelling. The problem was upper case version was being put in the wrong hashtable. This fixes the problem by using the correct hashtable. Also adds testcases for the upper case versions. * config/tc-aarch64.c (md_begin): Use correct hash table for uppercase version of hint. * testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase. * testsuite/gas/aarch64/system-2.d: Update. Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers6-11/+52
All symbols, sizes and relocations in this section are octets instead of bytes. Required for DWARF debug sections as DWARF information is organized in octets, not bytes. bfd/ * section.c (struct bfd_section): New flag SEC_ELF_OCTETS. * archures.c (bfd_octets_per_byte): New parameter sec. If section is not NULL and SEC_ELF_OCTETS is set, one octet es returned [ELF targets only]. * bfd.c (bfd_get_section_limit): Provide section parameter to bfd_octets_per_byte. * bfd-in2.h: regenerate. * binary.c (binary_set_section_contents): Move call to bfd_octets_per_byte into section loop. Provide section parameter to bfd_octets_per_byte. * coff-arm.c (coff_arm_reloc): Provide section parameter to bfd_octets_per_byte. * coff-i386.c (coff_i386_reloc): likewise. * coff-mips.c (mips_reflo_reloc): likewise. * coff-x86_64.c (coff_amd64_reloc): likewise. * cofflink.c (_bfd_coff_link_input_bfd): likewise. (_bfd_coff_reloc_link_order): likewise. * elf.c (_bfd_elf_section_offset): likewise. (_bfd_elf_make_section_from_shdr): likewise. Set SEC_ELF_OCTETS for sections with names .gnu.build.attributes, .debug*, .zdebug* and .note.gnu*. * elf32-msp430.c (rl78_sym_diff_handler): Provide section parameter to bfd_octets_per_byte. * elf32-nds.c (nds32_elf_get_relocated_section_contents): likewise. * elf32-ppc.c (ppc_elf_addr16_ha_reloc): likewise. * elf32-pru.c (pru_elf32_do_ldi32_relocate): likewise. * elf32-s12z.c (opru18_reloc): likewise. * elf32-sh.c (sh_elf_reloc): likewise. * elf32-spu.c (spu_elf_rel9): likewise. * elf32-xtensa.c (bfd_elf_xtensa_reloc): likewise * elf64-ppc.c (ppc64_elf_brtaken_reloc): likewise. (ppc64_elf_addr16_ha_reloc): likewise. (ppc64_elf_toc64_reloc): likewise. * elflink.c (bfd_elf_final_link): likewise. (bfd_elf_perform_complex_relocation): likewise. (elf_fixup_link_order): likewise. (elf_link_input_bfd): likewise. (elf_link_sort_relocs): likewise. (elf_reloc_link_order): likewise. (resolve_section): likewise. * linker.c (_bfd_generic_reloc_link_order): likewise. (bfd_generic_define_common_symbol): likewise. (default_data_link_order): likewise. (default_indirect_link_order): likewise. * srec.c (srec_set_section_contents): likewise. (srec_write_section): likewise. * syms.c (_bfd_stab_section_find_nearest_line): likewise. * reloc.c (_bfd_final_link_relocate): likewise. (bfd_generic_get_relocated_section_contents): likewise. (bfd_install_relocation): likewise. For section which have SEC_ELF_OCTETS set, multiply output_base and output_offset with bfd_octets_per_byte. (bfd_perform_relocation): likewise. include/ * coff/ti.h (GET_SCNHDR_SIZE, PUT_SCNHDR_SIZE, GET_SCN_SCNLEN), (PUT_SCN_SCNLEN): Adjust bfd_octets_per_byte calls. binutils/ * objdump.c (disassemble_data): Provide section parameter to bfd_octets_per_byte. (dump_section): likewise (dump_section_header): likewise. Show SEC_ELF_OCTETS flag if set. gas/ * as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF. * dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for .debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_str and .debug_ranges sections. * write.c (maybe_generate_build_notes): Set section flag SEC_OCTETS for .gnu.build.attributes section. * frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE if SEC_OCTETS is set. * symbols.c (resolve_symbol_value): Likewise. ld/ * ldexp.c (fold_name): Provide section parameter to bfd_octets_per_byte. * ldlang (init_opb): New argument s. Set opb_shift to 0 if SEC_ELF_OCTETS for the current section is set. (print_input_section): Pass current section to init_opb. (print_data_statement,print_reloc_statement, print_padding_statement): Likewise. (lang_check_section_addresses): Call init_opb for each section. (lang_size_sections_1,lang_size_sections_1, lang_do_assignments_1): Likewise. (lang_process): Pass NULL to init_opb.
2019-11-25Reverts patches providing octet support in dwarfChristian Eggers4-63/+22
Reverts "dwarf2: Align relocation within .debug_line section" commit 204f543cae7a5dc908264b49d558191d0ceb989c, Reverts "dwarf2: Pad size of .debug_line section." commit 145c4477d239fef4e31a457ff8a1ba7153e9a448, Reverts "dwarf2: Use octets for .debug_line prologue" commit 38c24f42c97af59ad83505ed735e689c63d3ca45, Mostly reverts "dwarf2: Use octets for dwarf2 headers" commit 7235427998571b6d8267e7ac72a52d7b082f4c2b, Mostly reverts "Symbols with octets value" commit d18d199917337537713f9fc4b7ae4d6568f740cf. * dwarf2dbg.c (out_set_addr): Revert 2019-03-13 change. (out_debug_line, out_debug_aranges, out_debug_info): Likewise. * symbols.h (symbol_set_value_now_octets, symbol_octets_p): Remove. * symbols.c (struct symbol_flags): Remove member sy_octets. (symbol_temp_new_now_octets): Don't set symbol_flags::sy_octets. (resolve_symbol_value): Revert: Return octets instead of bytes if sy_octets is set. (symbol_set_value_now_octets): Remove. (symbol_octets_p): Remove.
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu4-16/+62
This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-20PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra4-8/+23
PR 24944 * atof-generic.c (atof_generic): Increase decimal guard digits. * testsuite/gas/i386/fp.s: Add more tests. * testsuite/gas/i386/fp.d: Update.
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess13-2/+125
Add a flag to control the version of CIE that is generated. By default gas produces CIE version 1, and this continues to be the default after this patch. However, a user can now provide --gdwarf-cie-version=NUMBER to switch to either version 3 or version 4 of CIE, version 2 was never released, and so causes an error as does any number less than 1 or greater than 4. Producing version 4 CIE requires two new fields to be added to the CIE, an address size field, and an segment selector field. For a flat address space the DWARF specification indicates that the segment selector should be 0, and the address size fields just contains the address size in bytes. For now we support 4 or 8 byte addresses, and the segment selector is always produced as 0. At some future time we might need to allow targets to override this. gas/ChangeLog: * as.c (parse_args): Parse --gdwarf-cie-version option. (flag_dwarf_cie_version): New variable. * as.h (flag_dwarf_cie_version): Declare. * dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to flag_dwarf_cie_version. * doc/as.texi (Overview): Document --gdwarf-cie-version. * NEWS: Likewise. * testsuite/gas/cfi/cfi.exp: Add new tests. * testsuite/gas/cfi/cie-version-0.d: New file. * testsuite/gas/cfi/cie-version-1.d: New file. * testsuite/gas/cfi/cie-version-2.d: New file. * testsuite/gas/cfi/cie-version-3.d: New file. * testsuite/gas/cfi/cie-version-4.d: New file. * testsuite/gas/cfi/cie-version.s: New file. include/ChangeLog: * dwarf2.h (DW_CIE_VERSION): Delete. Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich3-34/+41
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich3-21/+45
... instead of an operand one: There's only ever one operand here anyway.
2019-11-14x86: make AnySize an insn attributeJan Beulich2-1/+5
... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich3-39/+45
The CMPS test case derivation from their MOVS counterparts I did in d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling") ended up with misplaced closing parentheses in som regexps. Correct this.
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich10-0/+386
This is still in the context of PR/gas 25167.
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-1/+5
We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu4-44/+131
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM, VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M Floating-point Extension is enabled. According to the ARMv8.1-M ARM, section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point Extension and/or Armv8.1-M MVE". [1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm instruction for mve_ext. (do_vfp_nsyn_pop): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm instruction for mve_ext. (do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks. (insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop, vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead of fpu_vfp_ext_v1xd. * testsuite/gas/arm/v8_1m-mve.s: New. * testsuite/gas/arm/v8_1m-mve.d: New.
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu4-2/+94
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu5-2/+32
This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
2019-11-12x86: fold EsSeg into IsStringJan Beulich2-34/+31
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12x86: eliminate ImmExt abuseJan Beulich12-352/+343
Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12x86: introduce operand type "instance"Jan Beulich2-29/+55
Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich3-0/+10
This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
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