aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2021-06-07x86/Intel: drop unnecessary bracket matching from parse_operands()Jan Beulich2-13/+8
While subsequent processing in AT&T mode relies on this simplistic early checking, Intel mode hasn't been for quite a long time (or perhaps never really did).
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich3-6/+11
In the one case where non-NULL gets passed, passing NULL has the same effect. Hence the parameter is not needed at all.
2021-06-07x86: immediate operands don't allow for vector operationsJan Beulich2-10/+4
Neither masking nor broadcast are possible here, and RC/SAE get dealt with elsewhere. This also fixes gas crashes (i.e. "Fatal error: unable to continue with assembly"), since the return path being removed failed to restore input_line_pointer from save_input_line_pointer.
2021-06-07ix86: wrap constantsJan Beulich6-6/+165
Non-64-bit code should get handled the same with or without BFD64. This wasn't the case though in a number of situations (and quite likely there are more that I haven't spotted yet). It's not very nice to tie the check in md_apply_fix() to object_64bit, but afaict at that time we have no record anymore of the mode an insn was assembled in (it might also have been data). This doesn't look to be the first inconsistency of this kind, though. In x86_cons() it's even less clear what the right approach would be: flag_code shouldn't matter for data emission, but instead we'd need to know from which mode(s) the data actually gets accessed. On this basis, signed_cons() also gets adjusted.
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-1/+6
Fixes a 16 year old bug report, which even came with a patch. opcodes/ PR 1202 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. Use unsigned int for inst. gas/ PR 1202 * testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra4-0/+121
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki54-0/+7580
Add tests for the generic C0, C1, C2, C3 coprocessor instructions. gas/ * testsuite/gas/mips/c0.d: New test. * testsuite/gas/mips/mips1@c0.d: New test. * testsuite/gas/mips/mips2@c0.d: New test. * testsuite/gas/mips/mips3@c0.d: New test. * testsuite/gas/mips/mips4@c0.d: New test. * testsuite/gas/mips/mips5@c0.d: New test. * testsuite/gas/mips/mips32@c0.d: New test. * testsuite/gas/mips/mips64@c0.d: New test. * testsuite/gas/mips/r3000@c0.d: New test. * testsuite/gas/mips/r3900@c0.d: New test. * testsuite/gas/mips/r4000@c0.d: New test. * testsuite/gas/mips/vr5400@c0.d: New test. * testsuite/gas/mips/r5900@c0.d: New test. * testsuite/gas/mips/sb1@c0.d: New test. * testsuite/gas/mips/interaptiv-mr2@c0.d: New test. * testsuite/gas/mips/octeon@c0.d: New test. * testsuite/gas/mips/xlr@c0.d: New test. * testsuite/gas/mips/c1.d: New test. * testsuite/gas/mips/mips1@c1.d: New test. * testsuite/gas/mips/mips2@c1.d: New test. * testsuite/gas/mips/mips3@c1.d: New test. * testsuite/gas/mips/mips4@c1.d: New test. * testsuite/gas/mips/mips5@c1.d: New test. * testsuite/gas/mips/mips32@c1.d: New test. * testsuite/gas/mips/mips64@c1.d: New test. * testsuite/gas/mips/mipsr6@c1.d: New test. * testsuite/gas/mips/r3000@c1.d: New test. * testsuite/gas/mips/r3900@c1.d: New test. * testsuite/gas/mips/r4000@c1.d: New test. * testsuite/gas/mips/vr5400@c1.d: New test. * testsuite/gas/mips/r5900@c1.d: New test. * testsuite/gas/mips/sb1@c1.d: New test. * testsuite/gas/mips/interaptiv-mr2@c1.d: New test. * testsuite/gas/mips/octeon@c1.d: New test. * testsuite/gas/mips/xlr@c1.d: New test. * testsuite/gas/mips/c2.d: New test. * testsuite/gas/mips/vr5400@c2.d: New test. * testsuite/gas/mips/r5900@c2.d: New test. * testsuite/gas/mips/octeon@c2.d: New test. * testsuite/gas/mips/c3.d: New test. * testsuite/gas/mips/mips1@c3.d: New test. * testsuite/gas/mips/mips2@c3.d: New test. * testsuite/gas/mips/mips32@c3.d: New test. * testsuite/gas/mips/r3000@c3.d: New test. * testsuite/gas/mips/r3900@c3.d: New test. * testsuite/gas/mips/c0.l: New test stderr output. * testsuite/gas/mips/c2.l: New test stderr output. * testsuite/gas/mips/c3.l: New test stderr output. * testsuite/gas/mips/c0.s: New test source. * testsuite/gas/mips/c1.s: New test source. * testsuite/gas/mips/c2.s: New test source. * testsuite/gas/mips/c3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki8-7/+39
Verify that the RFE instruction is not only accepted where supported, but rejected where it is not as well. gas/ * testsuite/gas/mips/mips.exp: Run RFE test across all ISAs. * testsuite/gas/mips/rfe.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@rfe.d: New test. * testsuite/gas/mips/mips2@rfe.d: New test. * testsuite/gas/mips/r3000@rfe.d: New test. * testsuite/gas/mips/r3900@rfe.d: New test. * testsuite/gas/mips/rfe.l: New test stderr output.
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki96-467/+1646
Verify that individual coprocessor instructions are not only accepted where supported, but rejected where they are not as well. gas/ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all ISAs. * testsuite/gas/mips/cp0b.d: Update for ISA exclusions. * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp0c.d: Update for ISA exclusions. * testsuite/gas/mips/cp0m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3.d: Update for ISA exclusions. * testsuite/gas/mips/cp3b.d: Update for ISA exclusions. * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp3m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3d.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0b.d: New test. * testsuite/gas/mips/mips3@cp0b.d: New test. * testsuite/gas/mips/r3000@cp0b.d: New test. * testsuite/gas/mips/r3900@cp0b.d: New test. * testsuite/gas/mips/r4000@cp0b.d: New test. * testsuite/gas/mips/r5900@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0bl.d: New test. * testsuite/gas/mips/mips3@cp0bl.d: New test. * testsuite/gas/mips/r3900@cp0bl.d: New test. * testsuite/gas/mips/r4000@cp0bl.d: New test. * testsuite/gas/mips/r5900@cp0bl.d: New test. * testsuite/gas/mips/mips1@cp0c.d: New test. * testsuite/gas/mips/mips2@cp0c.d: New test. * testsuite/gas/mips/mips3@cp0c.d: New test. * testsuite/gas/mips/mips4@cp0c.d: New test. * testsuite/gas/mips/mips5@cp0c.d: New test. * testsuite/gas/mips/r3000@cp0c.d: New test. * testsuite/gas/mips/r3900@cp0c.d: New test. * testsuite/gas/mips/r4000@cp0c.d: New test. * testsuite/gas/mips/vr5400@cp0c.d: New test. * testsuite/gas/mips/r5900@cp0c.d: New test. * testsuite/gas/mips/mips1@cp0m.d: New test. * testsuite/gas/mips/r3000@cp0m.d: New test. * testsuite/gas/mips/octeon@cp2.d: New test. * testsuite/gas/mips/mipsr6@cp2b.d: New test. * testsuite/gas/mips/vr5400@cp2b.d: New test. * testsuite/gas/mips/octeon@cp2b.d: New test. * testsuite/gas/mips/mips1@cp2bl.d: New test. * testsuite/gas/mips/mipsr6@cp2bl.d: New test. * testsuite/gas/mips/r3000@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2bl.d: New test. * testsuite/gas/mips/octeon@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2m.d: New test. * testsuite/gas/mips/r5900@cp2m.d: New test. * testsuite/gas/mips/octeon@cp2m.d: New test. * testsuite/gas/mips/mips1@cp2d.d: New test. * testsuite/gas/mips/r3000@cp2d.d: New test. * testsuite/gas/mips/r3900@cp2d.d: New test. * testsuite/gas/mips/vr5400@cp2d.d: New test. * testsuite/gas/mips/r5900@cp2d.d: New test. * testsuite/gas/mips/octeon@cp2d.d: New test. * testsuite/gas/mips/mips1@cp2-64.d: New test. * testsuite/gas/mips/mips2@cp2-64.d: New test. * testsuite/gas/mips/mips32@cp2-64.d: New test. * testsuite/gas/mips/mips32r2@cp2-64.d: New test. * testsuite/gas/mips/mips32r3@cp2-64.d: New test. * testsuite/gas/mips/mips32r5@cp2-64.d: New test. * testsuite/gas/mips/mips32r6@cp2-64.d: New test. * testsuite/gas/mips/r3000@cp2-64.d: New test. * testsuite/gas/mips/r3900@cp2-64.d: New test. * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test. * testsuite/gas/mips/mips1@cp3.d: New test. * testsuite/gas/mips/mips2@cp3.d: New test. * testsuite/gas/mips/mips32@cp3.d: New test. * testsuite/gas/mips/r3000@cp3.d: New test. * testsuite/gas/mips/r3900@cp3.d: New test. * testsuite/gas/mips/mips1@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3b.d: New test. * testsuite/gas/mips/mips32@cp3b.d: New test. * testsuite/gas/mips/r3000@cp3b.d: New test. * testsuite/gas/mips/r3900@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3bl.d: New test. * testsuite/gas/mips/mips32@cp3bl.d: New test. * testsuite/gas/mips/r3900@cp3bl.d: New test. * testsuite/gas/mips/mips1@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3m.d: New test. * testsuite/gas/mips/r3000@cp3m.d: New test. * testsuite/gas/mips/r3900@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3d.d: New test. * testsuite/gas/mips/cp0b.l: New test stderr output. * testsuite/gas/mips/cp0bl.l: New test stderr output. * testsuite/gas/mips/cp0c.l: New test stderr output. * testsuite/gas/mips/cp0m.l: New test stderr output. * testsuite/gas/mips/cp2.l: New test stderr output. * testsuite/gas/mips/cp2-64.l: New test stderr output. * testsuite/gas/mips/cp2b.l: New test stderr output. * testsuite/gas/mips/cp2bl.l: New test stderr output. * testsuite/gas/mips/cp2m.l: New test stderr output. * testsuite/gas/mips/cp2d.l: New test stderr output. * testsuite/gas/mips/cp3.l: New test stderr output. * testsuite/gas/mips/cp3b.l: New test stderr output. * testsuite/gas/mips/cp3bl.l: New test stderr output. * testsuite/gas/mips/cp3m.l: New test stderr output. * testsuite/gas/mips/cp3d.l: New test stderr output.
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki3-2/+53
Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki16-0/+215
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across the relevant ISA levels. Omit CP1 branches, covered elsewhere. gas/ * testsuite/gas/mips/cp0b.d: New test. * testsuite/gas/mips/cp0bl.d: New test. * testsuite/gas/mips/cp2b.d: New test. * testsuite/gas/mips/micromips@cp2b.d: New test. * testsuite/gas/mips/cp2bl.d: New test. * testsuite/gas/mips/micromips@cp2bl.d: New test. * testsuite/gas/mips/cp3b.d: New test. * testsuite/gas/mips/cp3bl.d: New test. * testsuite/gas/mips/cp0b.s: New test source. * testsuite/gas/mips/cp0bl.s: New test source. * testsuite/gas/mips/cp2b.s: New test source. * testsuite/gas/mips/cp2bl.s: New test source. * testsuite/gas/mips/cp3b.s: New test source. * testsuite/gas/mips/cp3bl.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki4-0/+26
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki9-29/+47
The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki27-0/+2180
Cover basic CP0, CP2, CP3 move, load and store instructions across the relevant ISA levels. Omit CP0 move and CP1 instructions as they are covered elsewhere. gas/ * testsuite/gas/mips/cp0c.d: New test. * testsuite/gas/mips/cp0m.d: New test. * testsuite/gas/mips/r3900@cp0m.d: New test. * testsuite/gas/mips/cp2.d: New test. * testsuite/gas/mips/micromips@cp2.d: New test. * testsuite/gas/mips/cp2m.d: New test. * testsuite/gas/mips/mipsr6@cp2m.d: New test. * testsuite/gas/mips/micromips@cp2m.d: New test. * testsuite/gas/mips/cp2d.d: New test. * testsuite/gas/mips/mipsr6@cp2d.d: New test. * testsuite/gas/mips/micromips@cp2d.d: New test. * testsuite/gas/mips/cp2-64.d: New test. * testsuite/gas/mips/micromips@cp2-64.d: New test. * testsuite/gas/mips/cp3.d: New test. * testsuite/gas/mips/cp3m.d: New test. * testsuite/gas/mips/cp3d.d: New test. * testsuite/gas/mips/cp0c.s: New test source. * testsuite/gas/mips/cp0m.s: New test source. * testsuite/gas/mips/cp2.s: New test source. * testsuite/gas/mips/cp2m.s: New test source. * testsuite/gas/mips/cp2d.s: New test source. * testsuite/gas/mips/cp2-64.s: New test source. * testsuite/gas/mips/cp3.s: New test source. * testsuite/gas/mips/cp3m.s: New test source. * testsuite/gas/mips/cp3d.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-4/+11
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki3-0/+49
The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki7-321/+331
The DMTC1 instruction operates on a floating-point general register as its second operand, however in the disassembly of the microMIPS encoding a floating-point control register is shown instead. This is due to an incorrect ordering of the two "dmtc1" entries in the opcode table, which gives precedence to one using the `G' aka coprocessor format over one using the `S' or floating-point register format. The coprocessor format, or OP_REG_COPRO, is used so that GAS supports referring to FPRs by their numbers in assembly, such as $0, $1, etc. however in the case of CP1/FPU it is also used by the disassembler to decode those numbers to the names of corresponding control registers. This in turn causes nonsensical disassembly such as: dmtc1 a1,c1_fir in a reference to $f0. It has been like this ever since microMIPS ISA support has been added. Correct the ordering of the two entries then by swapping them with each other, making disassembly output consistent with the regular MIPS DMTC1 instruction as well all the remaining CP1 move instructions. Adjust all the test cases affected accordingly. opcodes/ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" entries with each other. gas/ * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
2021-05-29MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1Maciej W. Rozycki2-4/+11
Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"), <https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR. While the register referred by its number is $31 in both cases, these instructions operate on the floating-point control register file rather than general-purpose registers. gas/ * config/tc-mips.c (FCSR): New macro. (macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu4-47/+27
The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner3-0/+13
opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.
2021-05-27nds32: __builtin_strncpy bound equals destination sizeAlan Modra2-8/+14
* config/tc-nds32.c (do_pseudo_push_bhwd, do_pseudo_pop_bhwd), (do_pseudo_pusha, do_pseudo_pushi): Avoid fortify strncpy bound error.
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu6-18/+80
commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs caused linker failure when building 16-bit program in a 32-bit ELF container. Update GNU_PROPERTY_X86_FEATURE_2_USED with #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12) to indicate that 16-bit mode instructions are used in the input object: https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA to indicate that 16-bit mode instructions are used in the object to allow linker to properly perform relocation overflow check for 16-bit PC-relative relocations in 16-bit mode instructions. 1. Update x86 assembler to always generate the GNU property note with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. 2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. bfd/ PR ld/27905 * elf32-i386.c: Include "libiberty.h". (elf_howto_table): Add 16-bit R_386_PC16 entry. (elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit R_386_PC16 if input has 16-bit mode instructions. (elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto call. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit R_X86_64_PC16 entry. (elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input has 16-bit mode instructions. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set elf_x86_has_code16 if relocatable input is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. * elfxx-x86.h (elf_x86_obj_tdata): Add has_code16. (elf_x86_has_code16): New. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Support GNU_PROPERTY_X86_FEATURE_2_CODE16. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Update x86_feature_2_used with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Always generate the GNU property note if x86_feature_2_used isn't 0. * testsuite/gas/i386/code16-2.d: New file. * testsuite/gas/i386/code16-2.s: Likewise. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. * testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New. ld/ PR ld/27905 * testsuite/ld-i386/code16.d: New file. * testsuite/ld-i386/code16.t: Likewise. * testsuite/ld-x86-64/code16.d: Likewise. * testsuite/ld-x86-64/code16.t: Likewise. * testsuite/ld-i386/i386.exp: Run code16. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-26i386: Replace movsb with movsxbSebastien Villemot2-1/+7
PR gas/27906 * doc/c-i386.texi: Replace movsb with movsxb as an alias for movsbq.
2021-05-26RISC-V: Allow to link the objects with unknown prefixed extensions.Nelson Chu2-0/+6
Since the policies of GNU and llvm toolchain are different for now, current binutils mainline cannot accept any draft extensions, including rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline, but the GNU ld might be used with them, so this causes the link time problems. The patch allows ld to link the objects with unknown prefixed extensions, which are probably generated by LLVM or customized toolchains. bfd/ * elfxx-riscv.h (check_unknown_prefixed_ext): New bool. * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the prefixed extension name if check_unknown_prefixed_ext is false. * elfnn-riscv.c (riscv_merge_arch_attr_info): Set check_unknown_prefixed_ext to false for linker. gas/ * config/tc-riscv.c (riscv_set_arch): Set check_unknown_prefixed_ext to true for assembler.
2021-05-25Arm: Fix forward thumb references [PR gas/25235]Tamar Christina4-1/+72
When assembling a forward reference the symbol will be unknown and so during do_t_adr we cannot set the thumb bit. The bit it set so early to prevent relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the symbol is Thumb. But because it's done so early we miss the case for forward references. This patch changes it so that we additionally check the thumb bit during the internal relocation processing. In principle we should be able to only set the bit during reloc processing but that would require changes to the other relocations that the instruction could be relaxed to. This approach still allows early relaxations (which means that we have less iteration of internal reloc processing) while still fixing the forward reference case. gas/ChangeLog: 2021-05-24 Tamar Christina <tamar.christina@arm.com> PR gas/25235 * config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol. (relax_adr): Thumb symbols 4 bytes. * testsuite/gas/arm/pr25235.d: New test. * testsuite/gas/arm/pr25235.s: New test.
2021-05-24RISC-V: PR25212, Report errors for invalid march and mabi combinations.Nelson Chu27-16/+72
This patch clarify the following invalid combinations of march and mabi, * ilp32f/lp64f abi without f extension. * ilp32d/lp64d abi without d extension. * ilp32q/lp64q abi without q extension. * e extension with any abi except ilp32e GNU assembler reports errors when finding the above invalid combinations. But LLVM-MC reports warnings and ignores these invalid cases. It help to set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve. This looks good and convenient, so perhaps we can do the same things. However, if you don't set the mabi, GNU assembler also try to set the suitable ABI according to march/elf-attribute. Compared to LLVM-MC, we will choose double/quad abi if d/f extension is set. gas/ PR 25212 * config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we will choose ilp32e abi for rv32e. Besides, report errors for the invalid march and mabi combinations. * testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase. Only accept ilp32e abi for rve extension. * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise. Renamed all mabi testcases to their march-mabi settings.
2021-05-22Re: Fix offset for ia64 PCREL60B relocation on HP-UXAlan Modra3-3/+17
PR 25599 * config/tc-ia64.c (emit_one_bundle): Expand comment for HP-UX adjustment. Add assertion. * testsuite/gas/ia64/reloc-mlx.d: Pass when slot 2 specified for PCREL60B.
2021-05-20Fix overflow detection in the Z80 assembler.Sergey Belyashov5-200/+227
* config/tc-z80.c (emit_data_val): Warn on constant overflow. (signed_overflow): New function. (unsigned_overflow): New function. (is_overflow): Use new functions. (md_apply_fix): Use signed_overflow. * testsuite/gas/z80/ez80_adl_suf.d: Fix test. * testsuite/gas/z80/ez80_isuf.s: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise.
2021-05-20PR27888, fix link of gas with zlib by libtool 2.4.6Nicolas Boulenguez3-2/+11
PR 27888 * Makefile.am (ZLIB): Define. (as_new_LDADD): Add it. * Makefile.in: Regenerate.
2021-05-19Fix offset for ia64 PCREL60B relocation on HP-UXJohn David Anglin1-1/+10
gas/ChangeLog: 2021-05-19 John Buddery <jvb@cyberscience.com> PR 25599 * config/tc-ia64.c (emit_one_bundle): Increment fixup offset by one for PCREL60B relocation on HP-UX.
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan5-3/+340
The initial problem I wanted to fix here is that GAS was rejecting MVE instructions such as: vmov q3[2], q3[0], r2, r2 with: Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' which is incorrect; such instructions are valid. Note that for moves in the other direction, e.g.: vmov r2, r2, q3[2], q3[0] GAS is correct in rejecting this as it does not make sense to move both lanes into the same register (the Arm ARM says this is CONSTRAINED UNPREDICTABLE). After fixing this issue, I added assembly/disassembly tests for these vmovs. This revealed several disassembly issues, including incorrectly marking the moves into vector lanes as UNPREDICTABLE, and disassembling many of the vmovs as vector loads. These are now fixed. gas/ChangeLog: * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving into the same GPR twice. * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. * testsuite/gas/arm/mve-vmov-3.d: New test. * testsuite/gas/arm/mve-vmov-3.s: New test. opcodes/ChangeLog: * arm-dis.c (mve_opcodes): Fix disassembly of MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. (is_mve_encoding_conflict): MVE vector loads should not match when P = W = 0. (is_mve_unpredictable): It's not unpredictable to use the same source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-12SAFE_BYTE_GET64Alan Modra3-3/+8
Functions dealing with lack of a 64-bit integer type can disappear now that we require C99. Printing using dwarf_vmatoa is better too. binutils/ * dwarf.c (dwarf_vmatoa64, SAFE_BYTE_GET64, add64): Delete. (skip_attr_bytes): Replace use of SAFE_BYTE_GET64 with SAFE_BYTE_GET_AND_INC. (read_and_display_attr_value): Likewise. Print using dwarf_vmatoa. (process_debug_info, process_cu_tu_index): Likewise. * elfcomm.c (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Make size param unsigned. Remove code dealing with 4-byte elf_vma. (byte_get_64): Delete. * elfcomm.h (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Update prototypes. (byte_get_64): Delete. gas/ * testsuite/gas/elf/dwarf-5-file0.d: Update. * testsuite/gas/i386/dwarf5-line-1.d: Update.
2021-05-11Report illegal Z80 load instructions.Sergey Belyashov5-0/+95
PR 27823 * config/tc-z80.c (emit_ld_r_m): Report an illegal load instruction. * testsuite/gas/z80/ill_ops.s: New test source file. * testsuite/gas/z80/ill_ops.d: New test driver. * testsuite/gas/z80/ill_ops.l: New test error output.
2021-05-10Add support for 8-bit and 24-bit shifts in the z80 assembler.Sergey Belyashov4-2/+35
PR 27415 * config/tc-z80.c (emit_data_val): Add support for 8-bit and 24-bit shifts. * testsuite/gas/z80/z80_reloc.a: Update tests. * testsuite/gas/z80/z80_reloc.d: Update expected disassembly.
2021-05-08support generating multi-html pages in parallelMike Frysinger3-2/+17
Use the pattern from other projects where we generate the html pages in a dir named the same as the project. So now we have: gas/doc/gas.html - single html page gas/doc/gas/ - multiple html pages This works for projects that have a doc/ subdir already, but gprof & ld require a little tweaking since they generate their docs in their respective toplevels.
2021-05-08generate single html manual page by defaultMike Frysinger3-2/+9
This better matches other GNU projects like autoconf/automake where the html manual is the single page form. We'll support the multi-page form in a follow up change.
2021-05-07Add a generic .bss directive for ELF based targets.Nick Clifton4-14/+65
PR 3136 * config/obj-elf.c (elf_pseudo_table): Add entry for .bss. (obj_elf_bss): New function. Change to the .bss section. Support an optional subsection number. (obj_elf_change_section): Call obj_elf_section_change_hook. (obj_elf_section): Likewise. (obj_elf_data): Likewise. (obj_elf_text): Likewise. (obj_elf_struct): Likewise. (obj_elf_subsection): Likewise. (obj_elf_previous): Likewise. * config/obj-elf.h (obj_elf_bss): Prototype. * doc/as.texi (Bss): New node.
2021-05-07Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on ↵Cl?ment Chigot11-5/+217
XCOFF. gas * config/tc-ppc.c (ppc_function): Update comment for fifth argument. (ppc_frob_symbol): Remove ppc_last_function check. Make sure coff_last_function is reset. Correctly set fsize when not provided in .function. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-function-1-32.d: New test. * testsuite/gas/ppc/xcoff-function-1-64.d: New test. * testsuite/gas/ppc/xcoff-function-1.s: New test. bfd * coff-rs6000.c (xcoff_dwsect_names): Add new DWARF sections. * coffgen.c (coff_pointerize_aux): Handle C_DWARF. (coff_print_symbol): Likewise. * libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update. gas * config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF. (coff_adjust_section_syms): Use corrext auxent for C_DWARF. (coff_frob_section): Likewise. * config/obj-coff.h (SA_GET_SECT_SCNLEN, SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN, SA_SET_SECT_NRELOC) New defines. (SET_SECTION_RELOCS): Adjust for C_DWARF. * config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF. (ppc_adjust_symtab): Reorder C_DWARF symbols. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2.s: New test. include * coff/internal.h (C_DWARF): New define. * coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME, SSUBTYP_DWMAC): New defines.
2021-05-07x86-64/ELF: clear src_mask for all reloc typesJan Beulich4-0/+33
x86-64 uses rela relocations. The comment next to the field's declaration says "Non-zero values for ELF USE_RELA targets should be viewed with suspicion ..." And indeed the fields being non-zero causes section contents to be accumulated into the final relocated values in addition to the relocations' addends, which is contrary to the ELF spec.
2021-05-07x86: don't mix disp and imm processingJan Beulich2-1/+6
Surely disp processing should access the disp operand, not an imm one. This is not an active issue only because imms and disps are, at the moment, overlapping fields of the same union.
2021-05-07x86: move register check in immediate operand parsingJan Beulich2-7/+13
i386_finalize_immediate() is used for both AT&T and Intel immediate operand handling. Move an AT&T-only check to i386_immediate(), which at the same time allows it to cover other cases as well, giving an overall better / more consistent diagnostic.
2021-05-07x86: minor improvements to optimize_imm()Jan Beulich2-8/+11
- Drop a pointless & where just before it was checked that the respective bits are clear already anyway. - Avoid a not really necessary operand_type_set() and a redundant operand_type_or() / operand_type_and() pair.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne3-1/+14
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-03RISC-V: PR27764, Add tests for A extensionJim Wilson1-0/+8
ChangeLog entry for last patch.
2021-05-03RISC-V: PR27764, Add tests for A extensionChristoph Muellner4-0/+550
gas/ PR 27764 * testsuite/gas/riscv/a-ext-64.d: New testcase. * testsuite/gas/riscv/a-ext-64.s: Likewise. * testsuite/gas/riscv/a-ext.d: Likewise. * testsuite/gas/riscv/a-ext.s: Likewise. Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
2021-05-03x86: allow @secrel32 also in data definitionsJan Beulich4-7/+22
Now that lex_got() is uniform for all targets using it, permit COFF targets to also use @secrel32 with, in particular, .long. This is more natural than the custom .secrel32 directive, and also allows more flexibility (the "+six" form of the two added test lines doesn't work with a .secrel32 equivalent, in that it silently produces an unintended relocation type). As an extra benefit this also makes sure that data definitions in Intel syntax mode would get treated like they do for e.g. ELF targets.
2021-05-03x86: use UNIX EOL in secrel testcaseJan Beulich3-125/+130
For some reason these were using Windows EOL.
2021-05-03x86: fold both instances of lex_got()Jan Beulich2-106/+14
I see no reason at all for us to carry two copies of almost identical code. The differences, apart from the table entries, are benign. And the #ifdef-ary doesn't really get any worse.
2021-05-03testsuite: Don't start directives in first columnAlan Modra3-14/+20
Fixes fails on hppa64-hp-hpux11.23 * testsuite/gas/elf/section25.s: Don't start directives in first column. * testsuite/gas/elf/section26.s: Likewise.
2021-04-29x86-64: adjust recently added testsJan Beulich6-15/+26
Five of them fail for Cygwin and MingW. Adjust four and move one to the ELF-only section.
generated by cgit v1.1 at 2025-02-16 19:42:24 +0000