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2019-02-01S12Z: GAS: Allow #_symbol operands as mov sourceJohn Darrington5-35/+115
mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source operand should be accepted a relocatable expression. This change makes that possible. gas/ * config/tc-s12z.c (lex_imm): Add new argument exp_o. (emit_reloc): New function. (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it can be either 2 bytes or 3 bytes long. * testsuite/gas/s12z/mov-imm-reloc.d: New file. * testsuite/gas/s12z/mov-imm-reloc.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01S12Z: GAS: Fix incorrect range test for 16-bit PC relative offsets.John Darrington8-1/+63
The limits for PC relative offsets were incorrect. This change fixes them and adds some tests. gas/ * config/tc-s12z.c (md_apply_fix): Fix incorrect limits. * testsuite/gas/s12z/pc-rel-bad.d: New file. * testsuite/gas/s12z/pc-rel-bad.l: New file. * testsuite/gas/s12z/pc-rel-bad.s: New file. * testsuite/gas/s12z/pc-rel-good.d: New file. * testsuite/gas/s12z/pc-rel-good.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01S12Z: GAS: Issue warning if TFR/EXG have identical source and destination.John Darrington4-0/+11
It is permissible for the source and destination operands of TFR and EXG to be the same register. However it is a pointless instruction and anyone writing it has probably made a mistake. This change emits a warning if such an instruction is encountered. gas/ * config/tc-s12z.c (tfr): Emit warning if operands are the same. * testsuite/gas/s12z/exg.d: New test case. * testsuite/gas/s12z/exg.l: New file.
2019-02-01S12Z: GAS: Disallow immediate destination operandsJohn Darrington6-36/+107
The assembler permitted instructions which attempted to assign to an immediate operand. Bizarrely there is a valid machine code for such operations (although the documentation says it's "inappropriate"). This change causes such attempts to fail with an error message. gas/ * config/tc-s12z.c (lex_opr): Add a parameter to indicate whether immediate mode operands should be permitted. * testsuite/s12z/imm-dest.d: New file. * testsuite/s12z/imm-dest.l: New file. * testsuite/s12z/imm-dest.s: New file. * testsuite/s12z/s12z.exp: Add them.
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel7-7/+328
opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-31Assorted warning fixesAlan Modra4-8/+15
gcc-9 flagged warnings at the places I'm patching here, all real bugs. * config/tc-alpha.c (md_apply_fix): Correct range checks for BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR. * config/tc-arm.c (md_apply_fix): Use llabs rather than abs. * config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
2019-01-28xtensa: gas: don't keep relocations for constantsMax Filippov3-1/+13
xtensa gas chokes on 8/16 bit data entries representing constant symbols because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD cannot emit relocations. Resolve fixups for constant symbols in md_apply_fix. gas/ 2019-01-28 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark fixups for constant symbols as done in md_apply_fix. * testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
2019-01-28Updated Russian and French translations for the gas sub-directoryNick Clifton3-5489/+6351
2019-01-28Control gas enable-checking default by bfd/development.shAlan Modra3-8/+12
* configure.ac (ac_checking): Set from bfd/development.sh development variable. * configure: Regenerate.
2019-01-25AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and ↵Tamar Christina1-0/+10
st2zg
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das5-69/+102
This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions to use a previously reserved field for a new register operand. Thus the new versions of the instructions are as follows: - STG Xt, [<Xn|SP>, #<simm>] - STG Xt, [<Xn|SP>, #<simm>]! - STG Xt, [<Xn|SP>], #<simm> - STZG Xt, [<Xn|SP>, #<simm>] - STZG Xt, [<Xn|SP>, #<simm>]! - STZG Xt, [<Xn|SP>], #<simm> - ST2G Xt, [<Xn|SP>, #<simm>] - ST2G Xt, [<Xn|SP>, #<simm>]! - ST2G Xt, [<Xn|SP>], #<simm> - STZ2G Xt, [<Xn|SP>, #<simm>] - STZ2G Xt, [<Xn|SP>, #<simm>]! - STZ2G Xt, [<Xn|SP>], #<simm> Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (warn_unpredictable_ldst): Exempt stg, st2g, stzg and stz2g from Xt == Xn with writeback warning. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for stg, stzg, st2g and stz2g. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-tbl.h (QL_LDST_AT): Update macro. (aarch64_opcode): Change encoding for stg, stzg st2g and st2zg. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das5-0/+34
This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging ↵Sudi Das6-59/+16
Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25PR23940, check bounds before usingWu Heng2-2/+7
PR gas/23940 * macro.c (getstring): Check array bound before accessing.
2019-01-25PR24125, Assertion failure with embedded NULs in stringAlan Modra2-2/+6
An assertion that can be triggered by user input is wrong, so remove it. I believe the NUL would have been accepted before the PR20902 patch. PR 20902 PR 24125 * read.c (stringer): Delete assertion.
2019-01-21Updated translations for various binutils subdirectories.Nick Clifton2-2744/+3164
2019-01-19Change version to 2.32.51 and regenerate configure and pot files.Nick Clifton4-2710/+3122
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton2-0/+6
2019-01-17Arm: Clean up PE GAS testsuite correct THUMB tests.Tamar Christina9-1/+51
The PE targets don't support mapping symbols and so the disassembler is unable to correctly output thumb instructions when the input was thumb. So for testcases that only have thumb output, I have copied them and skipped the ones for which auto-detection is supposed to work on PE, and added a new one that will force thumb output. This so that the tests still check the mapping symbols. For the tests that switch between thumb and arm in one file I just skip them entirely on PE targets. This cleans up the PE GAS testsuite. gas/ * testsuite/gas/arm/archv6t2-1-pe.d: New test. * testsuite/gas/arm/archv6t2-1.d: Skip pe. * testsuite/gas/arm/csdb.d: Skip pe. * testsuite/gas/arm/sb-thumb1-pe.d: New test. * testsuite/gas/arm/sb-thumb1.d: Skip pe. * testsuite/gas/arm/sb-thumb2-pe.d: New test. * testsuite/gas/arm/sb-thumb2.d: Skip pe. * testsuite/gas/arm/udf.d: Skip pe.
2019-01-16Don't emit vendor attribute section if there is no attribute to emit.Jim Wilson2-0/+7
2019-01-16 Kito Cheng <kito@andestech.com> bfd/ * elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even for OBJ_ATTR_PROC. gas/ * testsuite/gas/riscv/attribute-empty.d: New.
2019-01-16RISC-V: Support ELF attribute for gas and readelf.Jim Wilson25-6/+390
2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-16S12Z: gas: Fix bug when a symbol name was the single letter 'c'.John Darrington5-4/+32
The assembler incorrectly recognised "c" as a register name, and refused to allow it where it expected a symbol/label. gas/ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings before the contents. * testsuite/gas/s12z/labels.d: New file. * testsuite/gas/s12z/labels.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-01-16S12Z: gas: Permit "extend" instructions which don't actually extend.John Darrington2-10/+7
Other assemblers permit "extending" a register into a register of a smaller size or the same size. It doesn't make much sense to do this but would appear to be a valid instruction. So change the error to a warning. gas/ * config/tc-s12z.c (tfr): Change as_bad to as_warn. Also fix message typo and semantics.
2019-01-16S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate.John Darrington3-7/+20
When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-14Implement the assembly instructions yield, wfe, wfi and sev for ARMv6T2 in ↵Srinath Parvathaneni5-2/+44
both ARM mode and Thumb mode. * config/tc-arm.c (arm_ext_v6k_v6t2): Define. (insns) [ARM_VARIANT]: Modified. (insns) [THUMB_VARIANT]: To implement few ARMv6K instructions in ARMv6T2 as well. * testsuite/gas/arm/archv6t2-1.d: New test. * testsuite/gas/arm/archv6t2-1.s: Likewise. * testsuite/gas/arm/archv6t2-2.d: Likewise.
2019-01-11More fallout from PR 23963 changeAlan Modra3-4/+10
PR 23963 * testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change. * testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
2019-01-10Correct changelog entry.Nick Clifton1-2/+3
2019-01-10Stop objdump from displaying control codes embedded in symbol names.Nick Clifton31-443/+479
PR 23963 binutils* objdump.c (sanitize_string): New function. Removes control characters from symbol names. (dump_section_header): Use new function. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (show_line): Likewise. (disassemble_bytes): Likewise. (disassemble_section): Likewise. (load_specific_debug_section): Likewise. (read_section_stabs): Likewise. (print_section_stabs): Likewise. (dump_section): Likewise. (dump_reloc_set): Likewise. (dump_relocs_in_section): Likewise. (dump_bfd): Likewise. (display_any_bfd): Likewise. gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that control characters are now displayed as escape sequences. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mipsel16-e.d: Likewise. * testsuite/gas/mips/mipsr6@msa.d: Likewise. * testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise. * testsuite/gas/mips/r6-64-n32.d: Likewise. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. * testsuite/gas/mips/tmips16-e.d: Likewise. * testsuite/gas/mips/tmipsel16-e.d: Likewise. * testsuite/gas/mn10300/relax.d: Likewise.
2019-01-09S12Z: Fix disassembly of indexed OPR operands with zero index.John Darrington3-1/+8
gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2019-01-09Adjust bfd/warning.m4 egrep patternsAndrew Paprocki2-5/+9
Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-08[AArch64][gas] Add -mcpu support for Arm AresKyrylo Tkachov3-0/+11
This adds support for the Arm Ares CPU for AArch64. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-aarch64.c (aarch64_cpus): Add ares. * doc/c-aarch64.texi (-mcpu): Document ares value.
2019-01-08run_dump_test source in build directoryAlan Modra137-2/+210
Some existing tests build .s and .d files for run_dump_test, using an absolute #source: line in the .d file. This patch changes that scheme a little to instead use "#source: ./..." in .d files rather than "#source: $objdir/...", which is more useful in cases where the .d file is not generated. This allows RX gas test files to be built in the build directory, rather than in a source directory (which might be read-only). binutils/ * testsuite/lib/binutils-common.exp (run_dump_test): Don't prepend $srcdir/$subdir to source file name if it starts with "./". gas/ * testsuite/gas/rx/rx.exp: Create generated test source in current directory. * testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d, * testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d, * testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d, * testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d, * testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d, * testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d, * testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d, * testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d, * testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d, * testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d, * testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d, * testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d, * testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d, * testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d, * testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d, * testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d, * testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d, * testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d, * testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d, * testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d, * testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d, * testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d, * testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d, * testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d, * testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d, * testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d, * testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d, * testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d, * testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d, * testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d, * testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d, * testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d, * testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d, * testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d, * testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d, * testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d, * testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d, * testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d, * testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d, * testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d, * testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d, * testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d, * testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d, * testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d, * testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d, * testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d, * testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d, * testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d, * testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d, * testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d, * testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d, * testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d, * testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d, * testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d, * testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d, * testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d, * testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d, * testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d, * testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d, * testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d, * testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d, * testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d, * testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d, * testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d, * testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d, * testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d, * testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d, * testsuite/gas/rx/xor.d: Add #source line. ld/ * testsuite/ld-elf/sec64k.exp: Use . rather than $objdir in generated source file names. * testsuite/ld-m68k/m68k-got.exp: Likewise.
2019-01-07[arm][gas] Add -mcpu support for Arm AresKyrylo Tkachov3-0/+9
This adds support for the Arm Ares CPU in the arm port. It implements the Armv8.2-A architecture with the relevant optional features of dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-arm.c (arm_cpus): Add ares. * doc/c-arm.texi (-mcpu): Document ares value.
2019-01-05RX: gas - Add RXv3 instruction support.Yoshinori Sato49-57/+903
Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU. (rx_bfield): Add prototype. (rx_post): Likewise. * config/rx-parse.y: Add v3 instructions and Double FPU registers. (DSIZE): Define. (POST): Define. (rx_check_v3): New. check v3 type. (rx_check_dfpu): New. check have double support. (double_condition_table): New. dcmp<cond> contiditon. (check_condition): Multiple condition support. (rx_lex): RXv3 instructions support. Add parse dcmp<cond> instruction and Double FPU registers. (immediate): Disable optimize in dmov #imm case. (displacement): Add double displacement in dmov instraction. * config/tc-rx.c (rx_use_conventional_section_names): Invert default value in rx-*-linux target. (cpu_type): Add additional ELF flags. (cpu_type_list): Add RXv3. (md_parse_option): Refer elf_flags from cpu_type_list. (md_show_usage): Add rxv3 and rxv3-dfpu. (rx_bytesT): Add post byte. (rx_bfield): New. generate bfmov / bfmovz "imm" field. (rx_post): New. Set instruction post byte. (md_assemble): Add post byte. doc/c-rx.texi: Add cpu types. * testsuite/gas/rx/Xtod.d: New. * testsuite/gas/rx/Xtod.sm: New. * testsuite/gas/rx/bfmov.d: New. * testsuite/gas/rx/bfmov.sm: New. * testsuite/gas/rx/dabs.d: New. * testsuite/gas/rx/dabs.sm: New. * testsuite/gas/rx/dadd.d: New. * testsuite/gas/rx/dadd.sm: New. * testsuite/gas/rx/dcmp.d: New. * testsuite/gas/rx/dcmp.sm: New. * testsuite/gas/rx/ddiv.d: New. * testsuite/gas/rx/ddiv.sm: New. * testsuite/gas/rx/dmov.d: New. * testsuite/gas/rx/dmov.sm: New. * testsuite/gas/rx/dmul.d: New. * testsuite/gas/rx/dmul.sm: New. * testsuite/gas/rx/dneg.d: New. * testsuite/gas/rx/dneg.sm: New. * testsuite/gas/rx/dpopm.d: New. * testsuite/gas/rx/dpopm.sm: New. * testsuite/gas/rx/dpushm.d: New. * testsuite/gas/rx/dpushm.sm: New. * testsuite/gas/rx/dround.d: New. * testsuite/gas/rx/dround.sm: New. * testsuite/gas/rx/dsqrt.d: New. * testsuite/gas/rx/dsqrt.sm: New. * testsuite/gas/rx/dsub.d: New. * testsuite/gas/rx/dsub.sm: New. * testsuite/gas/rx/dtoX.d: New. * testsuite/gas/rx/dtoX.sm: New. * testsuite/gas/rx/macros.inc: Add double FPU registers. * testsuite/gas/rx/mvfdc.d: New. * testsuite/gas/rx/mvfdc.sm: New. * testsuite/gas/rx/mvfdr.d: New. * testsuite/gas/rx/mvfdr.sm: New. * testsuite/gas/rx/mvtdc.d: New. * testsuite/gas/rx/mvtdc.sm: New. * testsuite/gas/rx/rstr.d: New. * testsuite/gas/rx/rstr.sm: New. * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option. * testsuite/gas/rx/save.d: New. * testsuite/gas/rx/save.sm: New. * testsuite/gas/rx/xor.d: New. * testsuite/gas/rx/xor.sm: Add pattern.
2019-01-04Fix potential buffer overrun whilst scanning macro strings.Wu Heng2-1/+7
PR 24010 * macro.c (get_any_string): Check for end of input whilst scanning for separators.
2019-01-04Fix bug parsing angle bracketed string sequences.Wu Heng2-2/+11
PR 24009 * read.c (stringer): Fix handling of missing '>' character at end of <...> sequence.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra561-563/+567
2019-01-01ChangeLog rotationAlan Modra2-5874/+5888
2018-12-19x86: Properly handle PLT expression in directiveH.J. Lu8-3/+34
For PLT expressions, we should subtract the PLT relocation size only for jump instructions. Since PLT relocations are PC relative, we only allow "symbol@PLT" in PLT expression. gas/ PR gas/23997 * config/tc-i386.c (x86_cons): Check for invalid PLT expression. (md_apply_fix): Subtract the PLT relocation size only for jump instructions. * testsuite/gas/i386/reloc32.s: Add test for invalid PLT expression. * testsuite/gas/i386/reloc64.s: Likewise. * testsuite/gas/i386/ilp32/reloc64.s: Likewise. * testsuite/gas/i386/reloc32.l: Updated. * testsuite/gas/i386/reloc64.l: Likewise. * testsuite/gas/i386/ilp32/reloc64.l: Likewise. ld/ PR gas/23997 * testsuite/ld-i386/i386.exp: Run PR gas/23997 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr23997a.s: New file. * testsuite/ld-x86-64/pr23997b.c: Likewise. * testsuite/ld-x86-64/pr23997c.c: Likewise.
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu3-3/+9
Linkers group input note sections with the same name into one output note section with the same name. One output note section is placed in one PT_NOTE segment. New linkers merge all input .note.gnu.property sections into one output .note.gnu.property section with a single NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older linkers treat input .note.gnu.property section as a generic note section and just concatenate all input .note.gnu.property sections into one output .note.gnu.property section without merging them, we may see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which are invalid. GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such that linker sets the bit for non-relocatable outputs. But it isn't sufficient: 1. It doesn't cover generic properties. 2. When -mx86-used-note=yes is passed to x86 assembler, the GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED property in object file and older linkers generate invalid NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit set. I am proposing the following changes: 1. Add PT_GNU_PROPERTY segment type: # define PT_GNU_PROPERTY (PT_LOOS + 0x474e553) which covers .note.gnu.property section. 2. Remove GNU_PROPERTY_X86_UINT32_VALID. bfd/ PR ld/23900 * elf.c (get_program_header_size): Add a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. (_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. * elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set GNU_PROPERTY_X86_UINT32_VALID. binutils/ PR ld/23900 * readelf.c (get_segment_type): Support PT_GNU_PROPERTY. (decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID. (decode_x86_feature_1): Likewise. (decode_x86_feature_2): Likewise. (print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID check. * testsuite/binutils-all/i386/empty.d: Updated. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/i386/pr21231b.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. gas/ PR ld/23900 * config/tc-i386.c (x86_cleanup): Don't set GNU_PROPERTY_X86_UINT32_VALID. * testsuite/gas/i386/property-1.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. include/ PR ld/23900 * elf/common.h (PT_GNU_PROPERTY): New. (GNU_PROPERTY_X86_UINT32_VALID): Removed. ld/ PR ld/23900 * testsuite/ld-elf/elf.exp: Run PR ld/23900 test. * testsuite/ld-elf/pr23900-1-32.rd: New file. * testsuite/ld-elf/pr23900-1-64.rd: Likewise. * testsuite/ld-elf/pr23900-1.d: Likewise. * testsuite/ld-elf/pr23900-1.s: Likewise. * testsuite/ld-elf/pr23900-2.s: Likewise. * testsuite/ld-elf/pr23900-2a.d: Likewise. * testsuite/ld-elf/pr23900-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-1.d: Adjusted. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372c.d: Expect <None> for GNU_PROPERTY_X86_ISA_1_USED. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23372d-x32.d: Likewise. * testsuite/ld-x86-64/pr23372d.d: Likewise. * testsuite/ld-x86-64/property-x86-5a.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. * testsuite/ld-x86-64/property-x86-5b.s: Likewise.
2018-12-13Fix typo/thinko in last change.Jeff Law2-1/+6
* dw2gencfi.c (output_cie): Add missing semicolon in last change.
2018-12-13Move aarch64 CIE code to aarch64 backendSam Tebbs4-13/+70
This commit moves all aarch64-specific code to deal with CIE structure introduced in 3a67e1a6b4430374f3073e51bb19347d4c421cfe from target-independent files to the aarch64 backend. 2018-12-13 Sam Tebbs <sam.tebbs@arm.com> binutils/ * dwarf.c (read_cie): Add check for 'B'. gas/ * config/tc-aarch64.h (enum pointer_auth_key, tc_fde_entry_extras, tc_cie_entry_extras, tc_fde_entry_init_extra, tc_output_cie_extra, tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define. * dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation. (alloc_fde_entry, select_cie_for_fde): Add tc_fde_entry_init_extra invocation. (output_cie): Add tc_output_cie_extra invocation. (select_cie_for_fde): Add tc_cie_fde_equivalent_extra invocation. * dw2gencfi.h (enum pointer_auth_key): Move to config/tc-aarch64.h. (struct fde_entry): Add tc_fde_entry_extras invocation
2018-12-12[GAS][Arm] Skip Local BLX Thumb tests for arm-netbsdelf and arm-ntoAndre Vieira2-1/+6
gas/ChangeLog 2018-12-12 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/blx-local-thumb.d: Skip arm-nto and arm-netbsdelf.
2018-12-10RISC-V: Don't segfault for two regs in auipc or lui.Jim Wilson5-1/+27
gas/ PR gas/23954 * config/tc-riscv.c (my_getSmallExpression): Expand comment for register support. Set expr_end if parse a register. (riscv_ip) <'u'>: Break if imm_expr is not a symbol or constant. * testsuite/gas/riscv/auipc-parsing.d: New. * testsuite/gas/riscv/auipc-parsing.l: New. * testsuite/gas/riscv/auipc-parsing.s: New.
2018-12-10Correct gas/ChangeLog entry for PR gas/23968H.J. Lu1-1/+1
2018-12-09x86: Put back BFD_RELOC_X86_64_GOTPCRELH.J. Lu6-0/+39
Put back BFD_RELOC_X86_64_GOTPCREL in TC_FORCE_RELOCATION_LOCAL, which was removed by commit 56ceb5b5405af23eddd12e12d8ba849010120324 Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Oct 22 04:49:20 2015 -0700 Add R_X86_64_[REX_]GOTPCRELX support to gas and ld by accident.
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson5-3/+43
PR gas/23956 gas/ * config/tc-riscv.c (validate_riscv_insn) <'1'>: New case. (percent_op_null): New. (riscv_ip) <'j'>: Set imm_reloc before p. <'1'>: New case. <'0'>: Use percent_op_null and don't set imm_reloc. <alu_op>: Handle *args == '1'. * testsuite/gas/riscv/tprel-add.d: New. * testsuite/gas/riscv/tprel-add.l: New. * testsuite/gas/riscv/tprel-add.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra2-33/+61
This patch started off just adding the warnings in tc-ppc.c about incorrect usage of @l, @h and @ha in instructions that don't have 16-bit D-form fields. That unfortunately showed up three warnings in ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like e_li r3, IV_table@l+0x00 which was being assembled to 8: 70 60 00 00 e_li r3,0 a: R_PPC_ADDR16_LO IV_table The ADDR16_LO reloc is of course completely bogus on e_li, which has a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800. Applying an ADDR16_LO reloc to the instruction potentially changes the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i, e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis, e_and2is, or some invalid encodings. Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was added 2017-09-05 but I can't see code in gas to generate the relocation. In any case, VLE_ADDR20 probably doesn't have the correct semantics for @l since ideally you'd want an @l to pair with @h or @ha to generate a 32-bit constant. Thus @l should only produce a 16-bit value, I think. So we need some more relocations to handle e_li it seems, or as I do in this patch, modify the behaviour of existing relocations when applied to e_li instructions. include/ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct mask and shift value. (ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li specially. gas/ * config/tc-ppc.c (md_assemble): Adjust relocs for VLE before TLS tweaks. Handle e_li. Warn on unexpected operand field for lo16/hi16/ha16 relocs.
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess2-2/+8
The RISC-V assembler generates fake labels with the name '.L0 ' as part of the debug information (see gas/config/tc-riscv.h:FAKE_LABEL_NAME). The problem is that currently, when disassembling an object file, the output looks like this (this is an example from the GDB testsuite, but is pretty representative of anything with debug information): 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 0000000000000026 <.L0 >: 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 0000000000000034 <.L0 >: 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L0 > 0000000000000046 <.L0 >: 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 0000000000000050 <.L0 >: 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <.L0 +0xe> 0000000000000066 <.L0 >: 66: 4785 li a5,1 68: a869 j 102 <.L0 > 000000000000006a <.L0 >: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L0 +0x8> The frequent repeated '.L0 ' labels are pointless, as they are non-unique there's no way to match a use of '.L0 ' to its appearence in the output, so we'd be better off just not printing it at all. That's what this patch does by defining a 'symbol_is_valid' method for RISC-V. With this commit, the same disassembly now looks like this: 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L4> 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <main+0x40> 66: 4785 li a5,1 68: a869 j 102 <.L5> 000000000000006a <.L4>: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L4+0x8> In order to share the fake label between the assembler and the libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have just moved FAKE_LABEL_NAME to the include file, however, I thnk this would be confusing, someone working on the assembler would likely not expect to find FAKE_LABEL_NAME defined outside of the assembler source tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the assembler standard FAKE_LABEL_ defines in the assembler source, but still share the RISCV_FAKE_LABEL_* with libopcodes. gas/ChangeLog: * config/tc-riscv.h (FAKE_LABEL_NAME): Define as RISCV_FAKE_LABEL_NAME. (FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR. include/ChangeLog: * dis-asm.h (riscv_symbol_is_valid): Declare. * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define. (RISCV_FAKE_LABEL_CHAR): Define. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Add RISC-V initialisation. * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-05[aarch64] Add support for pointer authentication B keySam Tebbs7-16/+150
Armv8.3-A has another key used in pointer authentication called the B-key (other than the A-key that is already supported). In order for stack unwinders to work it is necessary to be able to identify frames that have been signed with the B-key rather than the A-key and it was felt that keeping this as an augmentation character in the CIE was the best bet. The DWARF extensions for ARM therefore propose to add a new augmentation character 'B' to the CIE augmentation string and the corresponding cfi directive ".cfi_b_key_frame". I've made the relevant changes to GAS and LD to add support for B-key unwinding, which required modifying LD to check for 'B' in the augmentation string, adding the ".cfi_b_key_frame" directive to GAS and adding a "pauth_key" field to GAS's fde_entry and cie_entry structs. The pointer authentication instructions will behave as NOPs on architectures that don't support them, and so a check for the architecture being assembled for is not necessary since there will be no behavioural difference between augmentation strings with and without the 'B' character on such architectures. 2018-12-05 Sam Tebbs <sam.tebbs@arm.com> bfd/ * elf-eh-frame.c (_bfd_elf_parse_eh_frame): Add check for 'B'. gas/ * dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation. (alloc_fde_entry): Add tc_fde_entry_init_extra invocation. (output_cie): Add tc_output_cie_extra invocation. (select_cie_for_fde): Add tc_cie_fde_equivalent_extra and tc_cie_entry_init_extra invocation. (frch_cfi_data, cfa_save_data): Move to dwgencfi.h. * config/tc-aarch64.c (s_aarch64_cfi_b_key_frame): Declare. (md_pseudo_table): Add "cfi_b_key_frame". * config/tc-aarch64.h (tc_fde_entry_extras, tc_cie_entry_extras, tc_fde_entry_init_extra, tc_output_cie_extra, tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define. * dw2gencfi.h (struct fde_entry): Add tc_fde_entry_extras invocation. (pointer_auth_key): Define. (frch_cfi_data, cfa_save_data): Move from dwgencfi.c. * doc/c-aarch64.texi (.cfi_b_key_frame): Add documentation. * testsuite/gas/aarch64/(pac_ab_key.d, pac_ab_key.s): New file.
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