Age | Commit message (Collapse) | Author | Files | Lines |
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2011-02-28 Kai Tietz <kai.tietz@onevision.com>
* debug.c (debug_start_source): Use filename_(n)cmp.
* ieee.c (ieee_finish_compilation_unit): Likewise.
(ieee_lineno): Likewise.
* nlmconv.c (main): Likewise.
* objcopy.c (strip_main): Likewise.
(copy_main): Likewise.
* objdump.c (show_line): Likewise.
(dump_reloc_set): Likewise.
* srconv.c (main): Likewise.
* wrstabs.c (stab_lineno): Likewise.
ChangeLog gas/
2011-02-28 Kai Tietz <kai.tietz@onevision.com>
* depend.c (register_dependency): Use filename_(n)cmp.
* dwarf2dbg.c (get_filenum): Likewise.
* ecoff.c (add_file): Likewise.
(ecoff_generate_asm_lineno): Likewise.
* input-scrub.c (new_logical_line_flags): Likewise.
* listing.c (file_info): Likewise.
(listing_newline): Likewise.
* remap.c (remap_debug_filename): Likewise.
* stabs.c (generate_asm_file): Likewise.
(stabs_generate_asm_lineno): Likewise.
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* mips-opc.c (mips_builtin_opcodes): Correct register use
annotation of "alnv.ps".
gas/testsuite/
* gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction
branch swapping.
* gas/mips/alnv_ps-swap.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
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* config/tc-mips.c (append_insn): Disable branch relaxation for
DSP instructions.
gas/testsuite/
* gas/mips/relax-bposge.l: New test for DSP branch relaxation.
* gas/mips/relax-bposge.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
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* config/tc-mips.c (macro): Handle M_PREF_AB.
include/opcode/
* mips.h (M_PREF_AB): New enum value.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
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* config/tc-mips.c (RELAX_BRANCH_ENCODE): Encode the temporary
register to use.
(RELAX_BRANCH_UNCOND): Adjust accordingly.
(RELAX_BRANCH_LIKELY): Likewise.
(RELAX_BRANCH_LINK): Likewise.
(RELAX_BRANCH_TOOFAR): Likewise.
(RELAX_BRANCH_AT): New macro.
(append_insn): Encode the temporary register to use in standard
MIPS branch relaxation.
(relaxed_branch_length): Update according to changes to
RELAX_BRANCH_ENCODE.
(md_convert_frag): Use the encoded register as the temporary.
gas/testsuite/
* gas/mips/relax-at.d: New test for branch relaxation with .set
at.
* gas/mips/relax.s: Update to support the new test.
* gas/mips/relax.l: Update accordingly.
* gas/mips/relax.d: Update for multi-arch invocation.
* gas/mips/mips.exp: Run the new test. Adjust to run "relax"
across all applicable architectures.
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* config/tc-mips.c (mips_fix_adjustable): On REL targets also
reject PC-relative relocations.
gas/testsuite/
* gas/mips/branch-misc-2.d: Adjust for relocation change.
* gas/mips/branch-misc-2pic.d: Likewise.
* gas/mips/branch-misc-4.d: New test for PC-relative relocation
overflow.
* gas/mips/branch-misc-4-64.d: Likewise.
* gas/mips/branch-misc-4.s: Source for the new tests.
* testsuite/gas/mips/mips.exp: Run the new tests.
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* config/tc-mips.c (md_convert_frag): Correct message
capitalization.
gas/testsuite/
* gas/mips/relax-swap1.l: Adjust for message capitalization
correction.
* gas/mips/relax-swap2.l: Likewise.
* gas/mips/relax.l: Likewise.
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Add "op" parameter. Report operator and operand segments in error
message, not operand symbols.
(resolve_symbol_value): Always set segment for equated symbols, not
just when finalizing. Adjust report_op_error calls.
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gas/
2011-02-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (reloc): Don't sign-checking 4-byte
relocations if 64bit relocations aren't allowed.
gas/testsuite/
2011-02-25 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/ilp32.exp: Run reloc64.
* gas/i386/ilp32/reloc64.s: Allow TLS relocations with 32bit
register destinations.
* gas/i386/ilp32/reloc64.d: Updated.
* gas/i386/ilp32/reloc64.l: New.
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2011-02-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12519
* gas/elf/bad-size.d: New.
* gas/elf/bad-size.err: Likewise.
* gas/elf/bad-size.s: Likewise.
* gas/elf/elf.exp: Run bad-size.
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* config/obj-elf.c (elf_frob_symbol): Properly handle size expression.
* ld-mn10300/i135409-3.s: Correct .size label reference.
* ld-sh/sh64/stolib.s: Likewise.
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initialization of offset_reloc.
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(cfi_pseudo_table) [!TARGET_USE_CFIPOP]: New.
* read.c (pobegin): Unconditionally call cfi_pop_insert.
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/:
Import from Libtool and gnulib:
2011-01-27 Gerald Pfeifer <gerald@pfeifer.com>
Prepare for supporting FreeBSD 10.
* config.rpath: Remove handling of freebsd1* which soon would
match FreeBSD 10.0.
2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change)
Remove support for FreeBSD 1.x.
* libtool.m4 (_LT_LINKER_SHLIBS)
(_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which
soon would incorrectly match FreeBSD 10.0.
bfd/:
* configure: Regenerate.
gas/:
* configure: Regenerate.
ld/:
* configure: Regenerate.
opcodes/:
* configure: Regenerate.
binutils/:
* configure: Regenerate.
gprof/:
* configure: Regenerate.
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The single cycle dual mac ABS insn was incorrectly decoding the mac1
part of the insn.
Once we fix the decode, update the gas tests to have the correct output.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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When assigning to a register half, the mac0 part of the mult insn
was not decoding properly. It would always show a full dreg instead
of the dreg low half.
Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BYTEOP2M insn was part of the initial Blackfin designs, but never made
it into any actual silicon. So punt support for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The mmod field is decoded in a few places (gas/opcodes/sim), so move it to
a common place to avoid duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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A bunch of Blackfin-specific directives were lacking info on what they
actually do, so fill in the blanks. Further, the byte2/byte4 descriptions
were swapped.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The TESTSET insn does not work with the FP/SP Pregs, so reject them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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* gas/cfi/cfi-x86_64.d: Adjust for x64 PE+.
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and PowerPC options.
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* doc/as.texinfo: Refer to and include c-ppc.texi for PowerPC options.
(Overview <Target PowerPC options>): Add a number of missing options.
* doc/c-ppc.texi: Likewise. Add markup for use in manpage generation.
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* gas/m68k/mcf-coproc.d: Likewise.
* gas/m68k/mcf-wdebug.d: Likewise.
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gas/
2011-02-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/6957
* config/tc-i386.c (i386_align_code): Use f32_patt when tuning
for i686.
gas/testsuite/
2011-02-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/6957
* gas/i386/nops-1-i686.d: Updated.
* gas/i386/nops-3-i686.d: Likewise.
* gas/i386/nops-4-i686.d: Likewise.
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gas/
2011-02-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (set_cpu_arch): Also update cpu_arch_isa_flags
for ISA extensions.
(md_parse_option): Likewise.
gas/testsuite/
2011-02-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops-4a-i686 and nops-6.
* gas/i386/nops-4a-i686.d: New.
* gas/i386/nops-6.d: Likewise.
* gas/i386/nops-6.s: Likewise.
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* gas/m68k/p3041pcrel.s, * gas/m68k/p3041pcrel.d: New test.
* gas/m68k/all.exp: Add "p3041pcrel" and enable p3041 tests for
all m68k-aout targets.
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* doc/as.texinfo (Target TIC6X options): Don't mention "-matomic".
* doc/c-tic6x.texi (TIC6X Directives): Don't mention ".atomic".
(TIC6X Options): Don't mention "-matomic".
* config/tc-tic6x.c (OPTION_MATOMIC, OPTION_MNO_ATOMIC): Delete.
(md_longopts): Remove corresponding entries.
(md_parse_option): Don't handle them.
(md_show_usage): Don't document them.
(tic6x_atomic): Delete variable.
(tic6x_update_features): Always copy tic6x_arch_enable to
tic6x_features.
(tic6x_arch_enable): Remove references to TIC6X_INSN_ATOMIC.
(s_tic6x_atomic, s_tic6x_noatomic): Remove functions.
(md_pseudo_table): Remove ".atomic" and ".noatomic".
gas/testsuite/
* gas/tic6x/dir-junk.l: Remove tests for .atomic and .noatomic.
* gas/tic6x/dir-junk.s: Likewise.
* gas/tic6x/insns-c674x-bad.d: Remove test.
* gas/tic6x/insns-c674x-bad.l: Likewise.
* gas/tic6x/insns-atomic.d: Remove "-matomic" switch.
include/opcode/
* tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
* tic6x.h (TIC6X_INSN_ATOMIC): Remove.
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value when reporting the inability to write to the output file.
* config/tc-rx.c (rx_handle_align): Do not insert NOPs into align
frag that has a non-zero fill value.
* gas/all/align.d: Skip for the RX.
* gas/elf/group1a.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/elf.exp: Do not run section5 test for the RX port.
* gas/elf/section4.d: Likewise.
* gas/elf/section7.d: Likewise.
* gas/macros/semi.s: Fill with a non-zero pattern.
* gas/macros/semi.d: Expect non-zero fill value.
* gas/rx/bcnd.d: Update expected disassembly.
* gas/rx/bra.d: Likewise.
* gas/rx/macros.inc: Add reg1 macro.
* gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP
instruction.
* gas/rx/mov.sm: Likewise.
* gas/rx/max.d: Update expected disassembly.
* gas/rx/mov.d: Likewise.
* gas/rx/rx-asm-good.s: Use Renesas section names.
* gas/rx/rx-asm-good.d: Update expected disassembly.
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address, zero out the values stored in the object file to make
objdump's output consistent.
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* config/tc-i386.c (md_begin): Set for x64 windows COFF target
x86_dwarf2_return_column to 32.
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* config/tc-h8300.c (constant_fits_width_p): Use correct type for
comparison.
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2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* write.c (compress_debug): Return if section size is small than
32 byte.
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gas/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12409
* write.c (compress_debug): Return if section size is 0.
gas/testsuite/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12409
* gas/elf/dwarf2-4.d: New.
* gas/elf/dwarf2-4.s: Likewise.
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gas/testsuite/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.d: Updated.
* gas/i386/opcode-intel.d: Likewise.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
opcodes/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (sIbT): New.
(b_T_mode): Likewise.
(dis386): Replace sIb with sIbT on "pushT".
(x86_64_table): Replace sIb with Ib on "aam" and "aad".
(OP_sI): Handle b_T_mode. Properly sign-extend byte.
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2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/x86-64-arch-2.d: Add tbm flag and TBM instruction
pattern.
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cores: fa606te, fa616te, fmp626. Modify the VFP of fa626te.
* doc/c-arm.texi (ARM Options): Add -mcpu={fa606te, fa616te,
fmp626} options.
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* doc/all.texi: Add NS32K
* doc/as.texinfo: Remove target specific details of which
characters act as comment initiators and statement separators into
individual target specific files.
* doc/c-alpha.texi (Alpha-Chars): Document special behaviour of
the hash character at the start of a line.
* doc/c-arm.texi (ARM-Chars): Likewise.
* doc/c-avr.texi (AVR-Chars): Likewise.
* doc/c-d10v.texi (D10V-Chars): Likewise.
* doc/c-d30v.texi (D30V-Chars): Likewise.
* doc/c-mmix.texi (MMIX-Chars): Likewise.
* doc/c-s390.texi (s390 characters): Likewise.
* doc/c-sh.texi (SH-Chars): Likewise.
* doc/c-sh64.texi (SH64-Chars): Likewise.
* doc/c-sparc.texi (SPARC-Chars): Likewise.
* doc/c-tic6x.texi (TIC6X Syntax): Likewise.
* doc/c-xtensa.texi (Xtensa Syntax): Likewise.
* doc/c-z80.texi (Z80-Chars): Likewise.
* doc/c-z8k.texi (Z8000-Chars): Likewise.
* doc/c-pdp11.texi (PDP11-Syntax): Document line separator character.
* doc/c-arc.texi (ARC-Chars): Fill in this subsection.
* doc/c-bfin.texi (Blackfin Syntax): Document line comment and
line separator characters.
* doc/c-cr16.texi (CR16 Syntax): Likewise.
* doc/c-i386.texi (i386-Chars): Likewise.
* doc/c-i860.texi (i860-Chars): Likewise.
* doc/c-i960.texi (i960-Chars): Likewise.
* doc/c-ip2k.texi (IP2K-Chars): Likewise.
* doc/c-lm32.texi (LM32-Chars): likewise.
* doc/c-m32c.texi (M32C-Chars): Likewise.
* doc/c-m68hc11.texi (M68HC11-syntax): Likewise.
* doc/c-m68k.texi (M68K-Chars): Likewise.
* doc/c-microblaze.texi (MicroBlaze-Chars): Likewise.
* doc/c-msp430.texi (MSP430-Chars): Likewise.
* doc/c-mt.texi (MT-Chars): Likewise.
* doc/c-ns32k.texi (NS32K-Chars): Likewise.
* doc/c-pj.texi (PJ-Chars): Likewise.
* doc/c-ppc.texi (PowerPC-Chars): Likewise.
* doc/c-rx.texi (RX-Chars): Likewise.
* doc/c-score.texi (SCORE-Chars): Likewise.
* doc/c-tic54x.texi (TIC54X-Chars): Likewise.
* doc/c-v850.texi (V850-Chars): Likewise.
* doc/c-vax.texi (VAX-Chars): Likewise.
* doc/c-xc16x.texi (xc16x-Chars): Likewise.
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gas/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
* doc/c-i386.texi (i386-TBM): New section.
opcodes/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
gas/testsuite
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* gas/i386/tbm.s: New.
* gas/i386/tbm.d: New.
* gas/i386/tbm-intel.d: New.
* gas/i386/x86-64-tbm.s: New.
* gas/i386/x86-64-tbm.d: New.
* gas/i386/x86-64-tbm-intel.d: New.
* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
* gas/i386/arch-10.s: Add a TBM instruction.
* gas/i386/arch-10-1.l: Add TBM instruction pattern.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
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gas/
2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (disallow_64bit_disp): Renamed to ...
(disallow_64bit_reloc): This.
(md_assemble): Don't check movabs for x32 mode here.
(i386_target_format): Updated.
(tc_gen_reloc): Check if 64bit relocations are allowed.
gas/testsuite/
2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/immed64.s: New.
* gas/i386/ilp32/reloc64.s: Likewise.
* gas/i386/ilp32/x86-64-pcrel.s: Likewise.
* gas/i386/ilp32/inval.s: Add more tests.
* gas/i386/ilp32/immed64.d: Updated.
* gas/i386/ilp32/inval.l: Likewise.
* gas/i386/ilp32/reloc64.d: Likewise.
* gas/i386/ilp32/x86-64-pcrel.d: Likewise.
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gas/
2011-01-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (disallow_64bit_disp): New.
(x86_elf_abi): Replace X86_64_LP64_ABI/X86_64_ILP32_ABI with
X86_64_ABI/X86_64_X32_ABI.
(md_assemble): Don't allow movabs with relocation in x32 mode.
(i386_target_format): Updated.
gas/testsuite/
2011-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/ilp32.exp: Run inval.
* gas/i386/ilp32/inval.l: New.
* gas/i386/ilp32/inval.s: Likewise.
* gas/i386/ilp32/x86-64.s: Likewise.
* gas/i386/ilp32/x86-64.d: Don't use ../x86_64.s. Updated.
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gas/
2011-01-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (OPTION_N32): Renamed to ...
(OPTION_X32): This.
(md_longopts): Replace n32 with x32.
(md_parse_option): Updated.
(md_show_usage): Likewise.
* doc/c-i386.texi: Replace n32 with x32.
gas/testsuite/
2011-01-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/cfi/ilp32.exp: Replace --n32 with --x32.
* gas/i386/ilp32/elf/ilp32.exp: Likewise.
* gas/i386/ilp32/ilp32.exp: Likewise.
* gas/i386/ilp32/lns/ilp32.exp: Likewise.
ld/testsuite/
2011-01-14 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/ilp32-1.d: Replace --n32 with --x32.
* ld-x86-64/ilp32-2.d: Likewise.
* ld-x86-64/ilp32-3.d: Likewise.
* ld-x86-64/ilp32-4.d: Likewise.
* ld-x86-64/ilp32-5.d: Likewise.
* ld-x86-64/x86-64.exp: Likewise.
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