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2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme3-2/+8
Object files other than ELF do not have mapping symbols to indicate the type of data for objdump to work reliably. This is why the following tests FAIL on arm-wince-pe targets: ARMv6T2 Thumb CoProcessor Instructions (1) ARMv6T2 Thumb CoProcessor Instructions (2) This patch adds the force-thumb disassembler option to objdump for this test to PASS on these targets as well. 2017-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: Add --disassembler-options=force-thumb to objdump options. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: Likewise.
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which ↵James Bowman21-375/+2909
requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 2 adds a relaxation pass, which actually implements the code compression scheme. bfd * archures.c: Add bfd_mach_ft32b. * cpu-ft32.c: Add arch_info_struct. * elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1, DIFF32. (ft32_elf_relocate_section): Add clauses for R_FT32_SC0, SC1, DIFF32. (ft32_reloc_shortable, elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value, elf32_ft32_adjust_reloc_if_spans_insn, elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target, ft32_elf_relax_section): New function. * reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-ft32.c (md_assemble): add relaxation reloc BFD_RELOC_FT32_RELAX. (md_longopts): Add "norelax" and "no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32. (relaxable_section, ft32_validate_fix_sub, ft32_force_relocation, ft32_allow_local_subtract): New function. * config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION. * testsuite/gas/ft32/insnsc.s: New test exercising all FT32B shortcodes. include * elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme26-35/+328
A few coprocessor instructions introduced in ARMv2 are currently accepted by GAS when targeting ARMv1 due to a typo in the code. This patch fixes the issue and introduce a more fine grained testing for coprocessor instructions availability. Coprocessor instructions are grouped as follows: * ARM coprocessor instructions introduced in ARMv2 Includes: ldc, stc, mcr, mrc, cdp, ldcl, stcl Guarded by: ARM_EXT_V2 Tests: copro-arm_v2plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5 Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2 Guarded by: ARM_EXT_V5 Tests: copro-arm_v5plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5TE Includes: mcrr, mrrc Guarded by: ARM_EXT_V5E Tests: copro-arm_v5teplus-arm_v*.d * ARM coprocessor instructions introduced in ARMv6 Includes: mcrr2, mrrc2 Guarded by: ARM_EXT_V6 Tests: copro-arm_v6plus-arm_v*.d * Thumb coprocessor instructions introduced in ARMv6T2 Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc, cdp, ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2, mrrc2 Guarded by: ARM_EXT_V6T2 Tests: copro-thumb_v6t2plus-thumb_v*.d For each of these groups, at least 2 tests are performed: * instructions are not available in earlier architecture * instructions are available in architecture where they were introduced More tests need to be performed when instructions in a group span several assembly files. Note that an instruction in the original coprocessor testcase is changed to unified syntax to allow the testcase to be assembled for ARM and Thumb state. Correct processing of legacy syntax is covered in other testcases. 2017-11-01 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit. * testsuite/gas/arm/copro.s: Split into ... * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while changing it to unified syntax and ... * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ... * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ... * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This. * testsuite/gas/arm/copro.d: Split into ... * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2 and ... * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5 and ... * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target ARMv5TE and ... * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6. * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase. * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu14-1/+41
Extend invalid register check for AVX512 gathers to XMM register. PR gas/22352 * config/tc-i386.c (check_VecOperands): Also check XMM register for invalid register in AVX512 gathers. * testsuite/gas/i386/vgather-check.s: Add tests for AVX512 gathers with XMM register. * testsuite/gas/i386/x86-64-vgather-check.s: Likewise. * testsuite/gas/i386/vgather-check-error.l: Updated. * testsuite/gas/i386/vgather-check-none.d: Likewise. * testsuite/gas/i386/vgather-check-warn.d: Likewise. * testsuite/gas/i386/vgather-check-warn.e: Likewise. * testsuite/gas/i386/vgather-check.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-error.l: Likewise. * testsuite/gas/i386/x86-64-vgather-check-none.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-warn.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-warn.e: Likewise. * testsuite/gas/i386/x86-64-vgather-check.d: Likewise.
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2-2/+6
For some targets, like mmix-knuth-mmixware, .L2 (and .L1) are invalid symbols.
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra2-10/+18
include/ PR 22348 * opcode/cr16.h (instruction): Delete. (cr16_words, cr16_allWords, cr16_currInsn): Delete. * opcode/crx.h (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. (instruction): Delete. opcodes/ PR 22348 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. (cr16_words, cr16_allWords, processing_argument_number): Likewise. (imm4flag, size_changed): Likewise. * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. (words, allWords, processing_argument_number): Likewise. (cst4flag, size_changed): Likewise. * crx-opc.c (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. gas/ PR 22348 * config/tc-crx.c (instruction, output_opcode): Make static. (relocatable, ins_parse, cur_arg_num): Likewise. (parse_insn): Adjust for renamed opcodes globals. (check_range): Likewise
2017-10-25Yet another fill-1 test fixAlan Modra3-11/+17
tic4x fails due to being a 4 octets per byte target, while tic54x is 2 octets per byte. mmix still fails with fill-1.s:4: Error: unknown pseudo-op: `.l1:' fill-1.s:6: Error: unknown pseudo-op: `.l2:' fill-1.s:3: Error: .space specifies non-absolute value and if the labels are changed to L1 and L2 then mep-elf fails with fill-1.s:3: Error: .space specifies non-absolute value Since both of those look like they ought to be investigated by the target maintainers, I'm tweaking the test to fail on both targets. * testsuite/gas/all/fill-1.d: Exclude tic4x and tic54x. * testsuite/gas/all/fill-1.s: Use L1 rather than .L1.
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman8-0/+26
These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) <addi>: Use the above functions. <add>: Likewise. <c.addi4spn>: Likewise. <c.addi16sp>: Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests.
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman5-0/+15
This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-24Fix my previous gas/ChangeLog entryPalmer Dabbelt1-2/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu7-4/+54
Without 64-bit bfd, we can't properly support .code64 directive in 32-bit mode. * config/tc-i386.c (md_pseudo_table): Add .code64 directive only if BFD64 is defined. * testsuite/gas/i386/code64-inval.l: New file. * gas/testsuite/gas/i386/code64-inval.s: Likewise. * gas/testsuite/gas/i386/code64.d: Likewise. * gas/testsuite/gas/i386/code64.s: Likewise. * testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32, att-regs, intel-regs, intel-expr and string-ok tests only if assembler supports x86-64. Run code64 and code64-inval.
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2-1/+6
Systems without the C extension mandate 4-byte alignment for instructions, so there is no reason to allow for 2-byte alignment. This change avoids emitting lots of unimplemented instructions into object files on non-C targets, which users keep reporting as a bug. While this isn't actually a bug (as none of the offsets in object files are relevant until RISC-V), it is ugly. gas/ChangeLog 2017-10-23 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_frag_align_code): Align code by 4 bytes on non-RVC systems.
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+162
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2-3/+6
Fix a bug in MIPS n32 ELF object file generation and make such objects consistent with the n32 BFD requested, by presetting the EF_MIPS_ABI2 flag in the `e_flags' member of the newly created ELF file header, as it is this flag that tells n32 objects apart from o32 objects. This flag will then stay set through to output file generation for writers such as GAS or GDB's `generate-core-file' command. Readers will overwrite the whole of `e_flags' along with the rest of the ELF file header in `elf_swap_ehdr_in' and then verify in `mips_elf_n32_object_p' that the flag is still set before accepting an input file as an n32 object. The issue was discovered with GDB's `generate-core-file' command making o32 core files out of n32 debuggees. bfd/ * elfn32-mips.c (mips_elf_n32_mkobject): New prototype and function. (bfd_elf32_mkobject): Use `mips_elf_n32_mkobject' rather than `_bfd_mips_elf_mkobject'. gas/ * config/tc-mips.c (mips_elf_final_processing): Don't set EF_MIPS_ABI2 in `e_flags'.
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist15-0/+1046
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist15-1/+977
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist33-1/+738
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VPCLMULQDQ. * doc/c-i386.texi: Document VPCLMULQDQ. * testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests. * testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test. * testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/vpclmulqdq.d: Ditto. * testsuite/gas/i386/vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. (enum): Remove VEX_LEN_0F3A44_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F3A44_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. (CpuUnused): Comment out to avoid zero-width field problem. * i386-opc.tbl (vpclmulqdq): New instruction. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist33-0/+1349
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VAES. * doc/c-i386.texi: Document VAES. * testsuite/gas/i386/i386.exp: Run VAES tests. * testsuite/gas/i386/avx512f_vaes-intel.d: New test. * testsuite/gas/i386/avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vaes.d: Ditto. * testsuite/gas/i386/avx512f_vaes.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.s: Ditto. * testsuite/gas/i386/vaes-intel.d: Ditto. * testsuite/gas/i386/vaes.d: Ditto. * testsuite/gas/i386/vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto. * testsuite/gas/i386/x86-64-vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-vaes.d: Ditto. * testsuite/gas/i386/x86-64-vaes.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VAES. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist32-1/+1865
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist15-2/+3409
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-22Fix spurious left-over quotes from last edit.Hans-Peter Nilsson2-3/+8
With a 32-bit bfd (default on an ILP32 system) the previous markings on tests *were* correct. There, the results have been consistent since they were added. The tests would appear to "spuriously" xpass "only" on LP64 hosts, which were not the norm in 2000. (But, now CRIS requires a 64-bit BFD.)
2017-10-20Improve handling of REPT pseudo op with a negative count.Nick Clifton8-9/+46
PR 22324 * read.c (s_rept): Use size_t type for count parameter. (do_repeat): Change type of count parameter to size_t. Issue an error is the count parameter is negative. (do_repeat_with_expression): Likewise. * read.h: Update prototypes for do_repeat and do_repeat_with_expression. * doc/as.texinfo (Rept): Document that a zero count is allowed but negative counts are not. * config/tc-rx.c (rx_rept): Use size_t type for count parameter. * config/tc-tic54x.c (tic54x_loop): Cast count parameter to size_t type. * testsuite/gas/macros/end.s: Add a test using a negative repeat count. * testsuite/gas/macros/end.l: Add expected error message.
2017-10-19RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt2-1/+10
In the medany code model the compiler generates PCREL_HI20+PCREL_LO12 relocation pairs against local symbols because HI20+LO12 relocations can't reach high addresses. We relax HI20+LO12 pairs to GPREL relocations when possible, which is an important optimization for Dhrystone. Without this commit we are unable to relax PCREL_HI20+PCREL_LO12 pairs to GPREL when possible, causing a 10% permormance hit on Dhrystone on Rocket. Note that we'll now relax la gp, __global_pointer$ to mv gp, gp which probably isn't what you want in your entry code. Users who want gp-relative symbols to continue to resolve should add ".option norelax" accordingly. Due to this, the assembler now pairs PCREL relocations with RELAX relocations when they're expected to be relaxed just like every other relaxable relocation. bfd/ChangeLog 2017-10-19 Palmer Dabbelt <palmer@dabbelt.com> * elfnn-riscv.c (riscv_pcgp_hi_reloc): New structure. (riscv_pcgp_lo_reloc): Likewise. (riscv_pcgp_relocs): Likewise. (riscv_init_pcgp_relocs): New function. (riscv_free_pcgp_relocs): Likewise. (riscv_record_pcgp_hi_reloc): Likewise. (riscv_record_pcgp_lo_reloc): Likewise. (riscv_delete_pcgp_hi_reloc): Likewise. (riscv_use_pcgp_hi_reloc): Likewise. (riscv_record_pcgp_lo_reloc): Likewise. (riscv_find_pcgp_lo_reloc): Likewise. (riscv_delete_pcgp_lo_reloc): Likewise. (_bfd_riscv_relax_pc): Likewise. (_bfd_riscv_relax_section): Handle R_RISCV_PCREL_* relocations via the new functions above. gas/ChangeLog 2017-10-19 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (md_apply_fix): Mark BFD_RELOC_RISCV_PCREL_HI20 as relaxable when relaxations are enabled.
2017-10-19Fix the AVR assembler so that it will correctly issue warnings about skipped ↵Nick Clifton6-4/+49
instructions even if subsections are used. PR 21621 * config/tc-avr.h (struct avr_frag_data): Add prev_opcode field. (TC_FRAG_INIT): Define. (avr_frag_init): Add prototype. * config/tc-avr.c (avr_frag_init): New function. (avr_operands): Replace static local 'prev' variable with prev_opcode field in current frag. * testsuite/gas/avr/pr21621.s: New test source file. * testsuite/gas/avr/pr21621.d: New test driver file. * testsuite/gas/avr/pr21621.s: New test error output file.
2017-10-19Fix fill-1 testcaseAndreas Krebbel4-6/+23
This fixes various issues with the fill-1 testcase causing fails on a couple of targets. gas/ChangeLog: 2017-10-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/all/fill-1.s: Use normal labels. Change .text to .data. Pick different values. Use .dc.w instead of .word. * testsuite/gas/all/fill-1.d: New objdump output check. * testsuite/gas/all/gas.exp: Use run_dump_test to execute fill-1 testcase.
2017-10-18RISC-V: Mark unsupported gas testcasesPalmer Dabbelt9-1/+38
There are individual comments that explain why each test isn't supported, but the vast majority of them are due to RISC-V's aggressive linker relaxation. The SLEB test cases should eventually be supported, but the remaining ones probably won't ever be. 2017-10-18 Palmer Dabbelt <palmer@dabbelt.com> * testsuite/gas/all/align.d: Mark as unsupported on RISC-V. testsuite/gas/all/relax.d: Likewise. testsuite/gas/all/sleb128-2.d: Likewise. testsuite/gas/all/sleb128-4.d: Likewise. testsuite/gas/all/sleb128-5.d: Likewise. testsuite/gas/all/sleb128-7.d: Likewise. testsuite/gas/elf/section11.d: Likewise. testsuite/gas/all/gas.exp (diff1.s): Likewise.
2017-10-18Update Cris assembler tests for checks that now pass where they used to fail.Nick Clifton3-6/+9
PR gas/22304 * testsuite/gas/cris/range-err-1.s: Remove spurious xfails. * testsuite/gas/cris/cris.exp: Expect the shexpr-1 test to pass.
2017-10-18Update the Swedish translation in the GAS subdirectory.Nick Clifton2-4238/+6054
* po/sv.po: Updated Swedish translation.
2017-10-16Fix segfault processing nios2 pseudo-instructions with too few arguments.Sandra Loosemore5-30/+145
2017-10-16 Sandra Loosemore <sandra@codesourcery.com> Henry Wong <henry@stuffedcow.net> gas/ * config/tc-nios2.c (nios2_translate_pseudo_insn): Check for correct number of arguments. (md_assemble): Handle failure of nios2_translate_pseudo_insn. * testsuite/gas/nios2/illegal_pseudoinst.l: New file. * testsuite/gas/nios2/illegal_pseudoinst.s: New file. * testsuite/gas/nios2/nios2.exp: Add illegal_pseudoinst test.
2017-10-12FT32: support for FT32B processor - part 1James Bowman2-3/+20
FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
2017-10-11Disable the inclusion of logical input files in the assembler listing output ↵Nick Clifton4-13/+38
unless high level source listing has been enabled. PR 21977 * listing.c (listing_newline): Use the name of the current physical input file, rather than the current logical input file, unless including high level source in the listing. * input-scrub.c (as_where_physical): New function. Returns the name of the current physical input file. * as.h: Add prototype for as_where_physical.
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel4-1/+14
prno, tpei, and irbm are missing in the optable. gas/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-arch12.d (prno, tpei, irbm): New instructions added. * testsuite/gas/s390/zarch-arch12.s: Likewise. * testsuite/gas/s390/zarch-z13.d: Rename ppno to prno. opcodes/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt (prno, tpei, irbm): New instructions added.
2017-10-09Add missing changelog entriesAndreas Krebbel1-0/+11
2017-10-09Replace nop in fill-1.s testcase.Andreas Krebbel1-1/+1
gas/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/all/fill-1.s: Replace nop with .word 42
2017-10-09Enable .fill forward labelsAndreas Krebbel3-1/+8
gas/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * read.c (s_fill): Invoke expression instead of get_known_segmented_expression. * testsuite/gas/all/fill-1.s: New testcase. * testsuite/gas/all/gas.exp: Run fill-1 testcase
2017-10-05Fix the MSP430 assembler so that it detects and reports extraneous text at ↵Nick Clifton6-27/+114
the end of operands. PR 22133 * config/tc-msp430.c (parse_exp): Skip an 'h' suffix to constant expressions. (msp430_srcoperand): Check that the entire text was parsed by parse_exp. (msp430_operands): Likewise. * testsuite/gas/msp430/pr22133.s: New test file. * testsuite/gas/msp430/pr22133.d: New test driver. * testsuite/gas/msp430/pr22133.s: Expected error output. * testsuite/gas/msp430/msp430.exp: Run the new test.
2017-10-04Add an assembler test for PR gas/21167H.J. Lu4-0/+22
PR gas/21167 * testsuite/gas/elf/elf.exp: Run group3. * testsuite/gas/elf/group3.d: New file. * testsuite/gas/elf/group3.s: Likewise.
2017-10-05PR21167, relocation sections not included in groupsAlan Modra8-31/+62
This fixes a wart I've known about for years, but haven't done anything about because BFD treats relocation sections as an adjunct to the section they relocate. SHF_GROUP on the section thus implicitly applies to its relocation section(s), but it is an error that the reloc sections aren't part of the group. Like many patches to gas, this wasn't as straightforward as it could be due to a number of backends, i386, cr16 and others, removing relocs in tc_get_reloc rather than marking them as "done" earlier in md_apply_reloc. So it isn't possible for the group support to reliably detect the presence of relocs by looking at fixups earlier than write_relocs. However the group support needs to create signature symbols, and that must be done before the symbol table is frozen, before write_relocs. So split off the group sizing from elf_adjust_symtab and put it in elf_frob_file_after_relocs. bfd/ PR 21167 * elf.c (_bfd_elf_setup_sections): Don't trim reloc sections from groups. (_bfd_elf_init_reloc_shdr): Pass sec_hdr, use it to copy SHF_GROUP flag from section. (elf_fake_sections): Adjust calls. Exit immediately on failure. (bfd_elf_set_group_contents): Add associated reloc section indices to group contents gas/ PR 21167 * config/obj-elf.c (struct group_list): Delete elt_count. (groups): New static. (build_group_lists): Don't count elements. (elf_adjust_symtab): Use groups rather than auto list. Set up pointer from group member to SHT_GROUP section. Don't size SHT_GROUP section or clean up here.. (elf_frob_file_after_relocs): ..do so here instead. * testsuite/gas/arc/jli-1.d, * testsuite/gas/elf/groupautob.d, * testsuite/gas/mips/compact-eh-eb-2.d, * testsuite/gas/mips/compact-eh-eb-5.d, * testsuite/gas/mips/compact-eh-el-2.d, * testsuite/gas/mips/compact-eh-el-5.d: Adjust. ld/ PR 21167 * testsuite/ld-elf/group9b.d: Adjust for relocs included in group.
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov4-0/+71
opcodes/ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for VLE multimple load/store instructions. Old e_ldm* variants are kept as aliases. Add missing e_lmvmcsrrw and e_stmvmcsrrw. gas/ * testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the support for the VLE multiple load/store instructions. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test driver. * testsuite/gas/ppc/ppc.exp: Run it.
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x ↵Nick Clifton4-0/+25
instructions, vis: fmv.x.w and fmv.w.x. PR 22179 opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new names for the fmv.x.s and fmv.s.x instructions respectively. gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the renamed fmv.x.s and fmv.s.x instructions. * testsuite/gas/riscv/fmv.x.d: New file: Test driver.
2017-09-22readelf: Handle E_MIPS_MACH_5900Maciej W. Rozycki3-0/+28
Fix commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation 2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and add the handling of E_MIPS_MACH_5900, correctly showing `5900' among `Flags:' in the output of `-h' rather than `unknown CPU'. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_5900>: New case. gas/ * testsuite/gas/mips/elf_mach_5900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
2017-09-22PR gas/21762: MIPS: Fix .stabs directive marking labels as MIPS16James Cowgill7-0/+49
If a .stabs directive was used before another .set directive in a MIPS source file, s_mips_stab would call mips_mark_labels without having initialized the mips_opts structure yet. Fix this by calling file_mips_check_options which will initialize mips_opts if necessary. gas/ PR gas/21762 * config/tc-mips.c (s_mips_stab): Insert call to file_mips_check_options. * testsuite/gas/mips/micromips@stabs-symbol-type.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/mips16@stabs-symbol-type.d: New test. * testsuite/gas/mips/stabs-symbol-type.d: New test. * testsuite/gas/mips/stabs-symbol-type.s: New test source.
2017-09-21Reduce excessive .eh_frame alignment for powerpcAlan Modra2-0/+5
PowerPC64 .cfi directives use DW_EH_PE_sdata4 encoding for .eh_frame, so there is no real reason why .eh_frame should be 8 byte aligned. gas/ * config/tc-ppc.h (EH_FRAME_ALIGNMENT): Define. ld/ * testsuite/ld-powerpc/tlsopt5.wf: Update for reduced alignment.
2017-09-14PR22127, as segfaults assembling invalid .relocAlan Modra2-1/+7
"sec" gets set to NULL on errors in the offset expression. This patch disables part of the reloc expression processing that needs "sec" valid. I didn't disable the entire reloc expression handling so that errors in the reloc expression are reported even when the offset expression has an error. PR 22127 * write.c (resolve_reloc_expr_symbols): Don't segfault when sec has been set to NULL.
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu12-228/+266
Since the NOTRACK prefix is no longer required to be the last prefix before the REX prefix, restriction on the NOTRACK prefix position is removed from assembler as well as disassembler. Assembler encodes the NOTRACK prefix the same way as the DS segment register, which places it before other prefixes. Disassembler displays prefixes in the order they appear. gas/ * config/tc-i386.c (NOTRACK_PREFIX): Removed. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (parse_insn): Remove restriction on NOTRACK prefix position. * testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. opcodes/ * i386-dis.c (last_active_prefix): Removed. (ckprefix): Don't set last_active_prefix. (NOTRACK_Fixup): Don't check last_active_prefix.
2017-09-07RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC codePalmer Dabbelt2-17/+13
When linking the following code .global _prog_start _prog_start: mv x1, x1 mv x2, x2 .align 2 rvc_boundry: .option norvc .align 3 mv x3, x3 we currently emit an invalid two-byte 0 instruction. The actual output code looks like 0000000080000000 <_prog_start>: 80000000: 8086 mv ra,ra 80000002: 810a mv sp,sp 0000000080000004 <rvc_boundry>: 80000004: 0000 unimp 80000006: 0001 nop 80000008: 00018193 mv gp,gp This ends up manifesting due to the two-byte compressed NOP that's pessimisticly emitted by the ".align 2", which results in "rvc_boundry" being 2-byte aligned. frag_align_code() then goes and outputs a 2-byte NOP (which is invalid in no-RVC mode) to align the code back to a 4-byte boundry, which can't be relaxed away by the linker as it's not part of the R_RISCV_RELAX relocation. The fix is to just always emit the worst case possible alignment into the output as a single R_RISCV_RELAX, which the linker will then fix up. With this patch I get the expected code generation 0000000080000000 <_prog_start>: 80000000: 8086 mv ra,ra 80000002: 810a mv sp,sp 0000000080000004 <rvc_boundry>: 80000004: 00000013 nop 80000008: 00018193 mv gp,gp gas/ChangeLog 2017-09-07 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_frag_align_code): Emit the entire alignment sequence inside R_RISCV_ALIGN.
2017-09-05Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556134-2/+33
include/ * elf/ppc.h (R_PPC_VLE_ADDR20): New relocation. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20. (ppc_elf_check_relocs): Handle it. (ppc_elf_vle_split20): New function. (ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20. binutils/ * readelf.c (get_elf_section_flags): Add VLE. (process_section_headers): Add VLE key to details. gas/ * config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag. (ppc_elf_section_letter): New function. * config/tc-ppc.h (md_elf_section_letter): New. * testsuite/gas/elf/section10.d: Adjust for VLE.
2017-09-01Enable support for the AArch64 dot-prod instruction in the Cortex A55 and ↵Tamar Christina2-2/+7
A75 cpus. * config/tc-aarch64.c (aarch64_cpus): Enable DOTPROD for cortex-a55 and cortx-a75.
2017-08-30MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxationMaciej W. Rozycki6-0/+114
Fix a bug in commit a6ebf6169a1b ("MIPS: Convert cross-mode BAL to JALX") and in BFD linker relaxation correct the microMIPS interpretation of the branch offset, which is supposed to be shifted by 1 bit, rather than 2 as in the regular MIPS case. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS branch offset interpretation. gas/ * testsuite/gas/mips/branch-addend-micromips.d: New test. * testsuite/gas/mips/branch-addend-micromips-n32.d: New test. * testsuite/gas/mips/branch-addend-micromips-n64.d: New test. * testsuite/gas/mips/branch-addend-micromips.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-08-30MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 codeMaciej W. Rozycki23-1/+411
Fix a bug in commit 8b10b0b3e100 ("MIPS: Add options to control branch ISA checks") and with the `-mignore-branch-isa' command-line option also lift a GAS check for invalid MIPS16 branches between ISA modes, which is made separately from regular MIPS and microMIPS checks. gas/ * config/tc-mips.c (md_convert_frag): Respect `mips_ignore_branch_isa'. * testsuite/gas/mips/branch-local-5.d: New test. * testsuite/gas/mips/branch-local-n32-5.d: New test. * testsuite/gas/mips/branch-local-n64-5.d: New test. * testsuite/gas/mips/branch-local-6.d: New test. * testsuite/gas/mips/branch-local-n32-6.d: New test. * testsuite/gas/mips/branch-local-n64-6.d: New test. * testsuite/gas/mips/branch-local-7.d: New test. * testsuite/gas/mips/branch-local-n32-7.d: New test. * testsuite/gas/mips/branch-local-n64-7.d: New test. * testsuite/gas/mips/branch-local-ignore-5.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-5.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-5.d: New test. * testsuite/gas/mips/branch-local-ignore-6.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-6.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-6.d: New test. * testsuite/gas/mips/branch-local-5.l: New stderr output. * testsuite/gas/mips/branch-local-6.l: New stderr output. * testsuite/gas/mips/branch-local-5.s: New test source. * testsuite/gas/mips/branch-local-6.s: New test source. * testsuite/gas/mips/branch-local-7.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
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