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2020-12-01RISC-V: Support to add implicit extensions for G.Nelson Chu4-1/+20
G is a special case, consider the ISA spec github issue as follows, https://github.com/riscv/riscv-isa-manual/issues/575 My understand is that - i, m, a, f and d extensions are not g's implicit extensions, they are g's expansions. The zifencei is the implicit extension of g, and so is zicsr, since it is implicited by f (or i2p1). However, we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it will not output to the arch string, it is only used to check what implicit extensions are need to be added. bfd/ * elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with RISCV_UNKNOWN_VERSION versions. (riscv_parse_std_ext): Add g to the subset list, we only use it to add the implicit extensions, but won't output it to arch string. (riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei for g extension. (riscv_arch_str1): Do not output g to the arch string. * elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h. gas/ * testsuite/gas/riscv/attribute-10.d: Updated. * testsuite/gas/riscv/march-imply-g.d: New testcase for g. * testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei are not supported in the ISA spec v2.2, so don't add and output them. include/ * opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu12-12/+48
We have to parse and add all arch string extensions at first, and then start to add their implicit extensions. That means we can always add arch string extensions at the end of the subset list, but we need to search the right place to add their implicit extensions. For now we follow the following rules to add the implicit extensions, * Add zicsr and zifencei only when the i's version less than 2.1. * Add d, f and zicsr when q is found. * Add f and zicsr when d is found. * Add zicsr when f is found. Besides, we do not add the implicit extensions if they are already added in the subset list, or we cannot find their default versions according to the chosen ISA spec. bfd/ * elfnn-riscv.c (riscv_merge_std_ext): Updated since riscv_lookup_subset is changed. * elfxx-riscv.c (riscv_ext_order): New Array used to compare the extensions' order quickly. (riscv_init_ext_order): New function. Init the riscv_ext_order according to the riscv_supported_std_ext and parse_config[i].class automatically. (riscv_compare_subsets): New function. Similar to the strcmp, but compare the subsets with the specific order. (riscv_lookup_subset): Return TRUE and set `current` to the subset if it is found. Otherwise, return FALSE and set `current` to the place where we should insert the subset. (riscv_add_implicit_subset): New function. Search the list first, and then find the right place to add the implicit_subset. (riscv_parse_add_subset): Since We have to add all arch string extensions first, and then start to add their implicit extensions. We can add arch string extensions in order by the original riscv_add_subset, and then add the implicit subsets by the riscv_add_implicit_subset. Besides, do not add the implicit extensions if we failed to find their default versions. (riscv_parse_std_ext): Updated. (riscv_parse_add_implicit_subsets): New function. Add all implicit extensions according to the arch string extensions. (riscv_parse_subset): Call riscv_init_ext_order and riscv_parse_add_implicit_subsets, before and after parsing the arch string. Remove parts of the ISA conflict checking since the implicit extensions are added. * elfxx-riscv.h (riscv_lookup_subset): Updated. gas/ * config/tc-riscv.c (riscv_subset_supports): Updated. * testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to add the implicit zicsr and zifencei when i's version less than 2.1. * testsuite/gas/riscv/march-imply-i2p1.d: New testcase. * testsuite/gas/riscv/march-imply-d.d: Likewise. * testsuite/gas/riscv/march-imply-f.d: Likewise. * testsuite/gas/riscv/march-imply-q.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iq.l: Updated. * testsuite/gas/riscv/march-fail-rv32id.d: Removed. * testsuite/gas/riscv/march-fail-rv32id.l: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.d: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu23-35/+72
Keep the riscv_add_subset to do the same thing, and use a new function, riscv_parse_add_subset, to cover most of the things when parsing, including find the default versions for extensions, and check whether the versions are valid. The version 0p0 should be an invalid version, that is the mistake I made before. This patch clarify the version rules as follows, * We accept any version of extensions set by users, except 0p0. * The non-standard x extensions must be set with versions in arch string. * If user don't set the versions, or set 0p0 for the extensions, then try to find the supported versions according to the chosen ISA spec. Otherwise, report errors rather than output 0p0 for them. Besides, we use as_bad rather than as_fatal to report more errors for assembler. bfd/ * elfxx-riscv.c (riscv_lookup_subset): Moved to front. (riscv_add_subset): Likewise. (riscv_release_subset_list): Likewise. (riscv_parse_add_subset): New function. Find and check the versions before adding them by riscv_add_subset. (riscv_parsing_subset_version): Remove use_default_version and change the version type from unsigned to int. Set the versions to RISCV_UNKNOWN_VERSION if we can not find them in the arch string. (riscv_parse_std_ext): Updated. (riscv_parse_prefixed_ext): Updated. Since we use as_bad rather than as_fatal to report more errors, return NULL string if the parsed end_of_version is NULL, too. (riscv_parse_subset): Use a new boolean, no_conflict, to report more errors when we have more than one ISA conflicts. * elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to RISCV_UNKNOWN_VERSION. (riscv_lookup_subset_version): Removed. (riscv_parse_subset_t): Updated. gas/ * config/tc-riscv.c (riscv_get_default_ext_version): Change the version type from unsigned to int. (riscv_set_arch): Use as_bad rather than as_fatal to report more errors. * testsuite/gas/riscv/attribute-02.d: Updated since x must be set with versions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. * testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported in the spec 2.2, so choose the newer spec. * testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad. * testsuite/gas/riscv/march-fail-base-02.l: Likewise. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-porder.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise. * testsuite/gas/riscv/march-fail-rv32id.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise. * testsuite/gas/riscv/march-fail-single-char.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown.l: Likewise. * testsuite/gas/riscv/march-fail-uppercase.l: Likewise. * testsuite/gas/riscv/march-fail-version.l: Likewise. * testsuite/gas/riscv/march-fail-isa-spec.d: Likewise. * testsuite/gas/riscv/march-fail-isa-spec.l: Likewise. include/ * opcode/riscv.h (riscv_ext_version): Change the version type from unsigned to int.
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu7-2/+23
bfd/ * elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard extensions when parsed h keyword. (riscv_get_prefix_class): Support prefixed h class. (riscv_std_h_ext_strtab): Likewise. (riscv_ext_h_valid_p): Likewise. (parse_config): Likewise. (riscv_std_z_ext_strtab): Add zifencei. * elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H. gas/ * testsuite/gas/riscv/march-fail-order-z.d: New testcase, check orders of prefixed z extensions. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-char-h.d: New testcase. * testsuite/gas/riscv/march-fail-single-char.l: Updated. * testsuite/gas/riscv/march-fail-unknown-h.d: New testcase. * testsuite/gas/riscv/march-fail-unknown.l: Updated. opcodes/ * riscv-opc.c (riscv_ext_version_table): Add zifencei.
2020-12-01RISC-V: Don't allow any uppercase letter in the arch string.Nelson Chu4-2/+11
Although I cannot find any RISC-V specs said that uppercases are not allowed in the arhc string, but seems like it is an established fact both for GNU and LLVM. Therefore, we shouldn't allow the uppercases for the non-standard x extensions, too. bfd/ * elfxx-riscv.c (riscv_parse_subset): ISA string cannot contain any uppercase letter. gas/ * testsuite/gas/riscv/march-fail-uppercase-base.d: Updated. * testsuite/gas/riscv/march-fail-uppercase.l: Updated. * testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase.
2020-12-01RISC-V: Minor cleanup and testcases improvement for arch string parser.Nelson Chu55-59/+156
Re-indent the related codes, unify and improve the related error messages and comments. Besies, also re-write the testcases to cover more cases. bfd/ * elfxx-riscv.c: Re-indent codes, unify and improve the error messages and comments. (riscv_parse_prefixed_ext): Stop parsing the prefixed class extensions if the class is RV_ISA_CLASS_UNKNOWN, I get internal errors before adding this check for march-fail-porder* testcases. (riscv_parse_subset): Move the rv32 with q checking in front. * elfxx-riscv.h: Likewise. gas/ (These are new testcases that cover more cases) * testsuite/gas/riscv/march-fail-base-01.d: The first extension must be e, i or g. * testsuite/gas/riscv/march-fail-base-01.l: Likewise. * testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA. * testsuite/gas/riscv/march-fail-base-02.l: Likewise. * testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard extensions. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed x extensions. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when standard and prefixed extensions are set at the same time. * testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise. * testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise. * testsuite/gas/riscv/march-fail-porder.l: Likewise. * testsuite/gas/riscv/march-fail-single-char-s.d: Only standard extensions can use single char. * testsuite/gas/riscv/march-fail-single-char-x.d: Likewise. * testsuite/gas/riscv/march-fail-single-char-z.d: Likewise. * testsuite/gas/riscv/march-fail-single-char.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-s.d: All extensions should be known, except the non-standard x extensions. * testsuite/gas/riscv/march-fail-unknown-std.d: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-z.d: Likewise. * testsuite/gas/riscv/march-fail-unknown.l: Likewise. * testsuite/gas/riscv/march-fail-uppercase-base.d: Do not allow any uppercase in the arch string. * testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise. * testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise. * testsuite/gas/riscv/march-fail-uppercase.l: Likewise. * testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions. * testsuite/gas/riscv/march-fail-version-z.d: Likewise. * testsuite/gas/riscv/march-fail-version.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ef.l: Updated. * testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext. * testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64. * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. * testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext. * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise. (The following testcases are removed and covered by new testcases) * testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base. * testsuite/gas/riscv/march-fail-rv32i.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std. * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std. * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x. * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std. * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise. * testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std. * testsuite/gas/riscv/march-fail-rv64I.l: Likewise. * testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02. * testsuite/gas/riscv/march-fail-rv64e.l: Likewise. * testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s. * testsuite/gas/riscv/march-fail-s-with-version.l: Likewise. * testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s. * testsuite/gas/riscv/march-fail-s.l: Likewise. * testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s. * testsuite/gas/riscv/march-fail-sx.l: Likewise.
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov7-0/+34
The previous change "x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode" to ignore segment override prefixes in 64-bit mode lead to dumping branch hints as excessive prefixes: ffffffff8109d5a0 <vmx_get_rflags>: ... ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e> ^^^^^ In this particular case, those prefixes are not excessive but are used to provide branch hints - taken/not-taken - to the CPU. Assign active_seg_prefix in that particular case to consume them. gas/ 2002-11-29 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/branch.d: Add new branch insns test. * testsuite/gas/i386/branch.s: Likewise. * testsuite/gas/i386/i386.exp: Insert the new branch test. * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns. * testsuite/gas/i386/x86-64-branch.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2020-11-28 Borislav Petkov <bp@suse.de> * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
2020-11-27ELF: Support .noinit and .persistent sectionsJozef Lawrynowicz6-0/+50
The ".persistent" section is for data that should be initialized during load, but not during application reset. The ".noinit" section is for data that should not be initialized during load or application reset. Targets utilizing the elf.sc linker script template can define HAVE_{NOINIT,PERSISTENT}=yes to include the .noinit or .persistent output sections in the generated linker script. Targets with existing support for .noinit did not handle unique .noinit.* and .gnu.linkonce.n.* sections the .noinit output section, this patch also fixes that. bfd/ChangeLog: * elf.c (special_sections_g): Add .gnu.linkonce.n and .gnu.linkonce.p. (special_sections_n): Add .noinit. (special_sections_p): Add .persistent. binutils/ChangeLog: * testsuite/lib/binutils-common.exp (supports_noinit_section): New. (supports_persistent_section): New. gas/ChangeLog: * testsuite/gas/elf/elf.exp: Run new tests. * testsuite/gas/elf/section25.d: New test. * testsuite/gas/elf/section25.s: New test. * testsuite/gas/elf/section26.d: New test. * testsuite/gas/elf/section26.s: New test. ld/ChangeLog: * emulparams/armelf.sh (OTHER_SECTIONS): Remove .noinit section definition. Define HAVE_{NOINIT,PERSISTENT}=yes. * scripttempl/avr.sc (.noinit): Add .noinit.* and .gnu.linkonce.n.* input section wildcard patterns. * scripttempl/elf.sc: Define .noinit and .persistent sections when HAVE_NOINIT or HAVE_PERSISTENT are defined to "yes". * scripttempl/elf32msp430.sc (.noinit): Add .noinit.* and .gnu.linkonce.n.*. input section wildcard patterns. (.persistent): Add .persistent.* and .gnu.linkonce.p.*. input section wildcard patterns. * scripttempl/elfarcv2.sc (.noinit): Add .noinit.* and .gnu.linkonce.n.*. input section wildcard patterns. * scripttempl/pru.sc: Likewise. * testsuite/ld-elf/noinit-sections-1.d: New test. * testsuite/ld-elf/noinit-sections-2.d: New test. * testsuite/ld-elf/noinit-sections-2.l: New test. * testsuite/ld-elf/noinit-sections.s: New test. * testsuite/ld-elf/persistent-sections-1.d: New test. * testsuite/ld-elf/persistent-sections-2.d: New test. * testsuite/ld-elf/persistent-sections-2.l: New test. * testsuite/ld-elf/persistent-sections.s: New test.
2020-11-25gas output_file_close error messageAlan Modra3-3/+8
Seen on arm-elf, where ELFOSABI_ARM is set too late to get a warning when processing ifunc related directives on their source line. ../gas/as-new ifunc.s -o tmpdir/ifunc.o ../gas/as-new: symbol type STT_GNU_IFUNC is supported only by GNU and FreeBSD targets ifunc.s: Assembler messages: ifunc.s: Fatal error: can't close tmpdir/ifunc.o: sorry, cannot handle this file This patch doesn't fix the real underlying problem, just the late error message where "can't close" is a misdirection in this case. * output-file.c (output_file_close): Remove "can't close" from error message. * testsuite/gas/mips/reginfo-2.l: Update expected output.
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus4-1/+18
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-11-19gas/testsuite: Fix SHF_GNU_RETAIN tests for FreeBSD OSABIsJozef Lawrynowicz4-3/+10
gas/ChangeLog: * testsuite/gas/elf/section22.d: Allow FreeBSD OSABI in readelf output. * testsuite/gas/elf/section23a.d: Likewise. * testsuite/gas/elf/section24a.d: Likewise.
2020-11-18Re: Stop Gas from generating line info or address rangesAlan Modra9-32/+122
* doc/as.texi (.nop): Document optional size arg. * dwarf2dbg.c (dwarf2_gen_line_info_1): Only check SEC_ALLOC when ELF. Warn whenever dwarf line number information is ignored. * frags.c (frag_offset_ignore_align_p): New function. * frags.h (frag_offset_ignore_align_p): Declare. * read.c (s_nop): Extend to support optional size arg. * testsuite/gas/elf/dwarf2-20.d: Expect warnings, and exact range. * testsuite/gas/elf/dwarf2-20.s: Emit 16 bytes worth of nops. * testsuite/gas/m68hc11/indexed12.d: Expect warnings.
2020-11-18Support SHF_GNU_RETAIN ELF section flagJozef Lawrynowicz16-22/+250
The SHF_GNU_RETAIN section flag is an extension to the GNU ELF OSABI. It is defined as follows: ========================================================= Section Attribute Flags +-------------------------------------+ | Name | Value | +-------------------------------------+ | SHF_GNU_RETAIN | 0x200000 (1 << 21) | +-------------------------------------+ SHF_GNU_RETAIN The link editor should not garbage collect the section. ========================================================= The .section directive accepts the "R" flag, which indicates SHF_GNU_RETAIN should be applied to the section. There is not a direct mapping of SHF_GNU_RETAIN to the BFD section flag SEC_KEEP. Keeping these flags distinct allows SHF_GNU_RETAIN sections to be explicitly removed by placing them in /DISCARD/. bfd/ChangeLog: * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_retain. (struct elf_obj_tdata): Increase has_gnu_osabi to 4 bits. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_retain for SHF_GNU_RETAIN. (_bfd_elf_final_write_processing): Report if SHF_GNU_RETAIN is not supported by the OSABI. Adjust error messages. * elflink.c (elf_link_input_bfd): Copy enabled has_gnu_osabi bits from input BFD to output BFD. (bfd_elf_gc_sections): gc_mark the section if SHF_GNU_RETAIN is set. binutils/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * readelf.c (get_elf_section_flags): Handle SHF_GNU_RETAIN. Recognize SHF_GNU_RETAIN and SHF_GNU_MBIND only for supported OSABIs. * testsuite/binutils-all/readelf.exp: Run new tests. Don't run run_dump_test when there isn't an assembler available. * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Adjust comment. * testsuite/binutils-all/readelf-maskos-1a.d: New test. * testsuite/binutils-all/readelf-maskos-1b.d: New test. * testsuite/binutils-all/readelf-maskos.s: New test. * testsuite/binutils-all/retain1.s: New test. * testsuite/binutils-all/retain1a.d: New test. * testsuite/binutils-all/retain1b.d: New test. gas/ChangeLog: * NEWS: Announce SHF_GNU_RETAIN support. * config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit between section declarations. (obj_elf_parse_section_letters): Handle 'R' flag. Handle numeric flag values within the SHF_MASKOS range. (obj_elf_section): Validate SHF_GNU_RETAIN usage. * doc/as.texi: Document 'R' flag to .section directive. * testsuite/gas/elf/elf.exp: Run new tests. * testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit. * testsuite/gas/elf/section10.s: Likewise. * testsuite/gas/elf/section22.d: New test. * testsuite/gas/elf/section22.s: New test. * testsuite/gas/elf/section23.s: New test. * testsuite/gas/elf/section23a.d: New test. * testsuite/gas/elf/section23b.d: New test. * testsuite/gas/elf/section23b.err: New test. * testsuite/gas/elf/section24.l: New test. * testsuite/gas/elf/section24.s: New test. * testsuite/gas/elf/section24a.d: New test. * testsuite/gas/elf/section24b.d: New test. include/ChangeLog: * elf/common.h (SHF_GNU_RETAIN): Define. ld/ChangeLog: * NEWS: Announce support for SHF_GNU_RETAIN. * ld.texi (garbage collection): Document SHF_GNU_RETAIN. (Output Section Discarding): Likewise. * testsuite/ld-elf/elf.exp: Run new tests. * testsuite/ld-elf/retain1.s: New test. * testsuite/ld-elf/retain1a.d: New test. * testsuite/ld-elf/retain1b.d: New test. * testsuite/ld-elf/retain2.d: New test. * testsuite/ld-elf/retain2.ld: New test. * testsuite/ld-elf/retain2.map: New test. * testsuite/ld-elf/retain3.d: New test. * testsuite/ld-elf/retain3.s: New test. * testsuite/ld-elf/retain4.d: New test. * testsuite/ld-elf/retain4.s: New test. * testsuite/ld-elf/retain5.d: New test. * testsuite/ld-elf/retain5.map: New test. * testsuite/ld-elf/retain5lib.s: New test. * testsuite/ld-elf/retain5main.s: New test. * testsuite/ld-elf/retain6a.d: New test. * testsuite/ld-elf/retain6b.d: New test. * testsuite/ld-elf/retain6lib.s: New test. * testsuite/ld-elf/retain6main.s: New test.
2020-11-17When reading string arguments for the assembler's string directives treat ↵Nick Clifton5-1/+21
space separated strings as a single entity. * read.c (stringer): Treat space separated, quote enclosed strings as a single string. * doc/as.texi (asciz): Mention this behaviour in the description of the asciz directive. * testsuite/gas/all/asciz.s: New test. * testsuite/gas/all/asciz.d: New test driver. * testsuite/gas/all/gas.exp: Run the new test.
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus6-1/+169
New -march option +pauth enables PAuth vel PAC (Pointer Authentication) feature.
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus6-1/+51
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
2020-11-16arm: Add support for Cortex-A78CPrzemyslaw Wirkus4-0/+16
This patch adds support for -mcpu=cortex-a78c command line option. For more information about this processor, see [0]: [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov36-392/+430
"In 64-bit mode, the CS, DS, ES, and SS segment-override prefixes have no effect. These four prefixes are not treated as segment-override prefixes for the purposes of multiple-prefix rules. Instead, they are treated as null prefixes." (AMD APM v2). However, objdump disassembles instructions containing those ignored prefixes by still generating that segment override: 66 66 2e 0f 1f 84 00 data16 nopw %cs:0x0(%rax,%rax,1) 00 00 00 00 Print those segment override prefixes as excessive ones: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1) 00 00 00 00 which is what they actually are - they have no effect and the decoding hardware ignores them. gas/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/x86-64-segovr.d: Adjust regexes. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-7.d: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise. ld/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/ld-x86-64/pe-x86-64-4.od: Adjust regexes. * testsuite/ld-x86-64/tlsld3.dd: Likewise. * testsuite/ld-x86-64/tlsld4.dd: Likewise. opcodes/ 2020-11-14 Borislav Petkov <bp@suse.de> * i386-dis.c (ckprefix): Do not assign active_seg_prefix in 64-bit addressing mode. (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of active_seg_prefix.
2020-11-13gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm modeAndre Vieira3-2/+16
This patch fixes a mistake when enabling MVE instructions that disabled support for single precision vmla and vmul for arm mode. gas/ChangeLog: 2020-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 26858 * config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT. * testsuite/gas/arm/pr26858.s: New test. * testsuite/gas/arm/pr26858.d: New test.
2020-11-12MSP430: gas: Ignore -md option required for GCC backward compatibilityJozef Lawrynowicz5-0/+30
The redundant -md option was removed in e4ae357fe8, but it is required for backwards compatibility with GCC 10, which passes it to the assembler implicitly in certain situations. It is now silently ignored. gas/ChangeLog: * config/tc-msp430.c (OPTION_MOVE_DATA): Define. (md_parse_option): Ignore OPTION_MOVE_DATA. (md_longopts): Handle -md option. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/empty.s: New test. * testsuite/gas/msp430/ignore-md.d: New test.
2020-11-12Fix up changelog entry of previous deltaNick Clifton1-2/+4
2020-11-12Stop Gas from generating line info or address ranges for sections that do ↵Nick Clifton6-17/+54
not contain code or are not loaded. PR 26850 * dwarf2dbg.c (dwarf2_gen_line_info_1): Do not record lines in sections that are not executable or not loadable. (out_debug_line): Move warning message into dwarf2_gen_line_info_1. * testsuite/gas/elf/dwarf2-20.s: New test. * testsuite/gas/elf/dwarf2-20.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/warn-2.s: Use the .nop directive.
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus2-1/+5
Allow users to use LS64 extension with Armv8.6 architecture.
2020-11-09Revert delta accidentally applied with commit ↵Nick Clifton1-24/+0
9372689d72f902c8bae90536acc4747fb0a4b1e1
2020-11-09gas: improve reproducibility for stabs debugging data formatDenys Zagorui2-1/+7
* config/obj-elf (obj_elf_init_stab_section): Improve reproducibility for stabs debugging data format
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU ↵Spencer E. Olson4-0/+36
assembler. include * opcode/pru.h: Add LMBD (left-most bit detect) opcode index opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect) gas * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect) * testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus4-1/+71
This patch: + Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0]. + Adds LS64 instruction tests. + Update LS64 feature test with new register. + Fix comment for AARCH64_OPND_Rt_LS64. [0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1 Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default).
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus5-34/+271
Atomic 64-byte load/store instructions limit Rt register number to values matching below condition (register <Xt> number must be even and <= 22): if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; This patch adds check if Rt fulfills above requirement. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
2020-11-09Fix regexp for development.expAndreas Schwab3-2/+7
binutils/: * Makefile.am (development.exp): Fix regexp. * Makefile.in: Regenerate. gas/: * Makefile.am (development.exp): Fix regexp. * Makefile.in: Regenerate. ld/: * Makefile.am (development.exp): Fix regexp. * Makefile.in: Regenerate.
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu18-47/+211
Originally, if the -mabi option isn't set, then assembler will set the abi according to the architecture string in the riscv_after_parse_args. But we should also check and reset the abi later since the architecture string may be reset by the elf attributes. Therefore, set the abi to the elf_flags in the riscv_after_parse_args seems too early. Besides, we have to set the abi_xlen before assembling any instruction, so it should be safe to call riscv_set_abi_by_arch at the place that we set start_assemble to TRUE. However, one minor case is that we won't call the md_assemble when we are assembling an file without any instruction. It seems that we still need to set the abi in riscv_elf_final_processing, to make sure that abi can be updated according to the elf arch attributes. For the rv32i and most elf toolchains, this patch can fix the mis-matched ABI errors for Run pr26391-5 and Run pr26391-6 testcases. Besides, it also correct the elf header flags of the output objects. Consider the new testcases, mabi-fail-02 and mabi-noabi-attr-[01|02|03], they are failed before applying this patch. But I still get the mis-matched ABI errors for the following toolchains when runnung the riscv-gnu-toolchain regressions, newlib-rv32imafc-ilp32f-[medlow|medany] linux-rv32imac-ilp32-[medlow|medany] linux-rv32imafdc-ilp32-[medlow|medany} linux-rv64imac-lp64-[medlow|medany] linux-rv64imafdc-lp64-[medlow|medany} For the newlib-rv32imafc-ilp32f, although we try to choose the abi according to the elf attributes, we will use FLOAT_ABI_SOFT rather than the FLOAT_ABI_SINGLE for the assmebly file wihtout setting the -mabi, but compiler will set the abi to FLOAT_ABI_SINGLE for the C files. As for the linux toolchains, we also get fails for Run pr26391-5 and Run pr26391-6 testcases. Since the linux toolchain won't generate elf attributes to correct the ISA, and the --with-arch configure option isn't set, assembler will try to set the default arch to rv[32|64]g, which means the FLOAT_ABI_DOUBLE will be choosed, and may be conflict with the abi set by the toolchain. Therefore, I would suggest that it's is more safe to set the --with-arch when building binutils, but it may break some testcases. For example, ld-scripts/fill and ld-scripts/empty-address-2 may be broken when c-ext is set. We might insert R_RISCV_ALIGN to make sure the 4-byte alignment, but the dump result will be a bit different from what the testcase expected. However, this patch only fix the problem - the abi, elf_flags and the instruction, which is generated according to the abi_xlen, are all fixed once the elf attributes are set for most elf toolchains. Other mis-matched ABI problems should be fixed when we always build the binutils with the --with-arch= configure option. gas/ * config/tc-riscv.c (explicit_mabi): New boolean to indicate if the -mabi= option is explictly set. (md_parse_option): Set explicit_mabi to TRUE if -mabi is set. (riscv_set_abi_by_arch): New function. If the -mabi option isn't set, then we set the abi according to the architecture string. Otherwise, check if there are conflicts between architecture and abi setting. (riscv_after_parse_args): Move the abi setting to md_assemble nad riscv_elf_final_processing. (md_assemble): Call the riscv_set_abi_by_arch when we set the start_assemble to TRUE. (riscv_elf_final_processing): Likewise, in case the file without any instruction. * testsuite/gas/riscv/mabi-attr-01.s: New testcase. * testsuite/gas/riscv/mabi-attr-02.s: Likewise. * testsuite/gas/riscv/mabi-attr-03.s: Likewise. * testsuite/gas/riscv/mabi-fail-01.d: Likewise. * testsuite/gas/riscv/mabi-fail-01.l: Likewise. * testsuite/gas/riscv/mabi-fail-02.d: Likewise. * testsuite/gas/riscv/mabi-fail-02.l: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-01a.d: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-01b.d: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-02a.d: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-02b.d: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-03a.d: Likewise. * testsuite/gas/riscv/mabi-noabi-attr-03b.d: Likewise. * testsuite/gas/riscv/mabi-noabi-march-01.d: Likewise. * testsuite/gas/riscv/mabi-noabi-march-02.d: Likewise. * testsuite/gas/riscv/mabi-noabi-march-03.d: Likewise.
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus11-141/+85
This patch: + updates RAS feature system registers with new RAS 1.1 regs. + extends RAS/RAS 1.1 support for all architecture levels of Armv8-A. Please note that early Armv8-A architectures do not officially support RAS extension. Rationale of the patch: To ease development so that user-friendly RAS system registers operands can be used. Certain use cases require developers to enable only more generic architecture (e.g. -march=armv8-a) during system development. Users must use RAS extension registers bearing in mind that system they use must support it. The RAS (Reliability, Availability, Serviceability) extension is a system-level extension that defines a number of system registers. RAS 1.1 (FEAT_RASv1p1) introduces five new system registers: ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1. For details see [0]. [0] https://developer.arm.com/docs/ddi0595/i/
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus7-0/+76
Armv8.7 architecture introduces the "accelerator extension", aka load/store of 64 bytes. New atomic load/store instructions are: LD64B, ST64B, ST64BV and ST64BV0. This patch adds: + New feature +ls64 to -march command line. + New atomic load/store instructions associated with above feature. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+90
Patch with missing ChangeLog entries for GAS AArch64 files.
2020-11-03gas: fix symbol value calculation for versioned symbol aliasesChristian Eggers2-1/+7
Symbol value is in bytes while fragS::fr_address is in octets. Fixes GAS symver12 and symver13 tests on ELF targets with with OCTETS_PER_BYTE>1. * config/obj-elf (elf_frob_symbol): Fix symbol value calculation for versioned symbol aliases. Signed-off-by: Christian Eggers <ceggers@gmx.de>
2020-10-30x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE markerH.J. Lu16-56/+86
GCC 11 supports -march=x86-64-v[234] to enable x86 micro-architecture ISA levels: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97250 X86 ISA markers are updated: https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/13 GNU_PROPERTY_X86_ISA_1_BASELINE is added and GNU_PROPERTY_X86_ISA_1_V[234] are updated: #define GNU_PROPERTY_X86_ISA_1_BASELINE (1U << 0) #define GNU_PROPERTY_X86_ISA_1_V2 (1U << 1) #define GNU_PROPERTY_X86_ISA_1_V3 (1U << 2) #define GNU_PROPERTY_X86_ISA_1_V4 (1U << 3) Add -z x86-64-baseline linker command line option to mark x86-64-baseline ISA level as needed. bfd/ PR gas/26703 * elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Generate GNU_PROPERTY_X86_ISA_1_BASELINE for -z x86-64-baseline. binutils/ PR gas/26703 * readelf.c (decode_x86_isa): Handle * GNU_PROPERTY_X86_ISA_1_BASELINE. * testsuite/binutils-all/i386/empty.d: Updated. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. gas/ PR gas/26703 * config/tc-i386.c (output_insn): Update for GNU_PROPERTY_X86_ISA_1_BASELINE. * testsuite/gas/i386/property-1.d: Updated. * testsuite/gas/i386/property-2.d: Likewise. * testsuite/gas/i386/property-3.d: Likewise. * testsuite/gas/i386/property-4.d: Likewise. * testsuite/gas/i386/property-5.d: Likewise. * testsuite/gas/i386/property-6.d: Likewise. * testsuite/gas/i386/property-11.d: Likewise. * testsuite/gas/i386/property-12.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise. * testsuite/gas/i386/x86-64-property-3.d: Likewise. * testsuite/gas/i386/x86-64-property-4.d: Likewise. * testsuite/gas/i386/x86-64-property-5.d: Likewise. * testsuite/gas/i386/x86-64-property-6.d: Likewise. * testsuite/gas/i386/x86-64-property-11.d: Likewise. * testsuite/gas/i386/x86-64-property-12.d: Likewise. include/ PR gas/26703 * elf/common.h (GNU_PROPERTY_X86_ISA_1_BASELINE): New. (GNU_PROPERTY_X86_ISA_1_V2): Uppdated. (GNU_PROPERTY_X86_ISA_1_V3): Likewise. (GNU_PROPERTY_X86_ISA_1_V4): Likewise. ld/ PR gas/26703 * NEWS: Mention -z x86-64-baseline. * ld.texi: Document -z x86-64-baseline. * emulparams/x86-64-level.sh: Handle -z x86-64-baseline. * testsuite/ld-elf/x86-feature-1a.rd: Update. * testsuite/ld-elf/x86-feature-1b.rd: Likewise. * testsuite/ld-elf/x86-feature-1c.rd: Likewise. * testsuite/ld-elf/x86-feature-1d.rd: Likewise. * testsuite/ld-elf/x86-feature-1e.rd: Likewise. * testsuite/ld-i386/pr23372c.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-i386/pr24322a.d: Likewise. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-i386/property-1a.r: Likewise. * testsuite/ld-i386/property-2a.r: Likewise. * testsuite/ld-i386/property-3.r: Likewise. * testsuite/ld-i386/property-3a.r: Likewise. * testsuite/ld-i386/property-4.r: Likewise. * testsuite/ld-i386/property-4a.r: Likewise. * testsuite/ld-i386/property-5.r: Likewise. * testsuite/ld-i386/property-5a.r: Likewise. * testsuite/ld-i386/property-7a.r: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-5.d: Likewise. * testsuite/ld-i386/property-x86-cet1.d: Likewise. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-isa1.d: Likewise. * testsuite/ld-i386/property-x86-isa2.d: Likewise. * testsuite/ld-i386/property-x86-isa3.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa1.d: Likewise. * testsuite/ld-x86-64/property-x86-isa2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa2.d: Likewise. * testsuite/ld-x86-64/property-x86-isa3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa3.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. * testsuite/ld-i386/i386.exp: Run property-x86-isa4. * testsuite/ld-i386/property-x86-isa4.d: New file. * testsuite/ld-x86-64/property-x86-isa4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa4.d: Likewise. * ld/testsuite/ld-x86-64/x86-64.exp: Run property-x86-isa4 and property-x86-isa4-x32.
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus3-2/+67
This patch adds new to Armv8.7 WFIT instruction which take one operand: WFIT <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 570 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn. * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn. opcodes/ChangeLog: 2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-29aarch64: Fix DSB instruction 'missing immediate expression' errorsPrzemyslaw Wirkus3-1/+34
This patch fixes errors with DSB instruction after introduction of DSB nXS variant. That change would cause GAS to reject valid DSB immediate string operands. gas/ChangeLog: 2020-10-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB immediate string operand. * testsuite/gas/aarch64/system-4.d: Update test. * testsuite/gas/aarch64/system-4.s: Update test.
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus7-0/+57
This patch adds: + New feature +csre to -march command line. + New instruction CSR PDEC associated with CSRE feature. Please note that CSRE system registers were already upstreamed. This patch should finalize CSRE feature implementation. CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. Although this instruction has operand (PDEC) it's instruction's only operand. PDEC forces instruction field Rt to be set to 0b1111. This results in fixed opcode of the instruction. gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * config/tc-aarch64.c (parse_csr_operand): New operand parser. (parse_operands): Call to CSR operand parser. * testsuite/gas/aarch64/csre_csr-invalid.d: New test. * testsuite/gas/aarch64/csre_csr-invalid.l: New test. * testsuite/gas/aarch64/csre_csr-invalid.s: New test. * testsuite/gas/aarch64/csre_csr.d: New test. * testsuite/gas/aarch64/csre_csr.s: New test. include/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature. (enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. * aarch64-tbl.h (CSRE): New CSRE feature handler. (_CSRE_INSN): New CSRE instruction type. (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus3-1/+75
This patch adds new to Armv8.7 WFET instruction which take one operand: WFET <Xt> Where: <Xt> is 64-bit name of the general-purpose source register, encoded in the "Rd" field. For more details regarding WFET (Wait For Event with Timeout) instruction for Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 565 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update docs. * testsuite/gas/aarch64/system-5.d: New test. * testsuite/gas/aarch64/system-5.s: New test. opcodes/ChangeLog: 2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding and operand description. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus7-0/+107
This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus3-2/+3
This patch adds support for AArch64 -march=armv8.7-a command line option in GAS. Please note that this change ONLY extends -march= command line interface with a new "armv8.7-a" option. Architectural changes like new instructions will be added in following patches. gas/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (armv8.7-a): New arch. * doc/c-aarch64.texi (-march=armv8.7-a): Update docs. include/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask. (AARCH64_ARCH_V8_7): New arch feature set. opcodes/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-tbl.h (ARMV8_7): New macro.
2020-10-26gas: Clear all auto-assigned file slotsH.J. Lu5-11/+89
Since a file slot is auto-assigned for the #APP marker appeared before the first .file <NUMBER> directive has been seen, clear all auto-assigned file slots when seeing the first .file <NUMBER> directive. PR gas/26778 * * dwarf2dbg.c (num_of_auto_assigned): New. (allocate_filenum): Increment num_of_auto_assigned. (dwarf2_directive_filename): Clear the slots auto-assigned before the first .file <NUMBER> directive was seen. * testsuite/gas/i386/dwarf4-line-1.d: New file. * testsuite/gas/i386/dwarf4-line-1.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf4-line-1.
2020-10-26Update gas/ChangeLog of last commitLifang Xia1-0/+5
gas/ * ChangeLog: Update ChangLog of 2e58f3923ef
2020-10-26C-SKY: Fix the literal dump of big vector constant.Cooper Qu1-1/+2
gas/ * config/tc-csky.c (dump_literals): Fix the literal dump of big vector constant.
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu3-2/+7
gas/ * testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16. * testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16. opcodes/ * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16. Change-Id: Ifb43573192e215527355f6541365b9f6a8ec80a4
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu2-2/+5
gas/ * config/tc-csky.c (md_begin): Add version flag in eflag. include/ * opcode/csky.h (CSKY_VERSION_V1): Define, currently used. (CSKY_VERSION_V2): Define. (CSKY_VERSION_V3): Define. Change-Id: Iafe3a9ce6fe544880a225b9fae439275a828bb34
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu3-27/+47
gas/ * config/tc-csky.c (get_operand_value): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for vector register. opcodes/ * csky-dis.c (csky_output_operand): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add some instructions for VDSPV1. Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili3-32/+38
gas/ * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from {vex3} to {vex} * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. opcodes/ * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus6-2/+425
This patch introduces BRBE (Branch Record Buffer Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/brbe-invalid.d: New test. * testsuite/gas/aarch64/brbe-invalid.l: New test. * testsuite/gas/aarch64/brbe-invalid.s: New test. * testsuite/gas/aarch64/brbe.d: New test. * testsuite/gas/aarch64/brbe.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add BRBE system registers.
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus6-1/+70
This patch introduces CSRE (Call Stack Recorder Extension) system registers. Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default). CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of a Call stack record) instruction. This instruction will be added in a following, separate patch. This change only adds CSRE system registers. gas/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * testsuite/gas/aarch64/csre-invalid.d: New test. * testsuite/gas/aarch64/csre-invalid.l: New test. * testsuite/gas/aarch64/csre-invalid.s: New test. * testsuite/gas/aarch64/csre.d: New test. * testsuite/gas/aarch64/csre.s: New test. opcodes/ChangeLog: 2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: New CSRE system registers defined.
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