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2023-10-24as: fixed internal error when immediate value of relocation overflow.Lulu Cai7-1/+21
The as and ld use _bfd_error_handler to output error messages when checking relocation alignment and relocation overflow. However, the abfd value passed by as to the function is NULL, resulting in an internal error. The ld passes a non-null value to the function, so it can output an error message normally.
2023-10-23gas: make .nops output visible in listingJan Beulich5-2/+71
Due to using a different frag type (in turn due to storing data differently), making the resulting code appear in listings requires special handling.
2023-10-23x86: fold NOP testcase expectations where possibleJan Beulich14-2340/+14
Like done earlier for files needing adjustment anyway, also do this for the remaining set.
2023-10-23x86: fold a few of the "alternative" NOP patternsJan Beulich1-6/+3
Since named objects may not overlap, the compiler is not permitted to do this for us, to avoid wasting space and cache bandwidth/capacity.
2023-10-23x86: add a few more NOP patternsJan Beulich32-2270/+465
First of all add f32_5[], allowing to eliminate the extra slot-is-NULL code from i386_output_nops(). Plus then introduce f32_8[] and f16_5[] following the same concept of adding a %cs segment override prefix. Also re-use patterns when possible and correct comments as applicable. Similarly re-use testcase expectations as much as possible, where they need touching anyway.
2023-10-23x86: don't record full i386_cpu_flags in struct i386_tc_frag_dataJan Beulich2-4/+4
We only use a single bit of this ever growing structure.
2023-10-23x86: i686 != PentiumProJan Beulich2-3/+6
The two are distinct in opcodes/, distinguished precisely by CpuNOP that's relevant in i386_generate_nops(), yet the function has the PPro case label in the other group. Simply removing it revealed that cpu_arch[] had a wrong entry for i686. While there also add PROCESSOR_IAMCU to the respective comment.
2023-10-23x86: respect ".arch nonop" when selecting which NOPs to emitJan Beulich5-27/+23
Making GENERIC64 a special case was never correct; prior to the generalization of ".arch .no*" to cover all ISA extensions other processor families supporting long NOPs should have been covered as well. When introducing ".arch .nonops" (among others) it wasn't apparent that a hidden implication of .cpunop not being possible to separately turn off existed here. Seeing that the two large case label blocks in the 2nd switch() already had identical behavior, simply collapse all of the (useful) case labels into a single "default" one.
2023-10-23x86: don't use operand size override with NOP in 16-bit codeJan Beulich4-11/+12
Since we don't key the NOP selection to user-controlled properties, we may not use i386 features; otherwise we would violate a possible .arch directive restricting ISA to pre-386.
2023-10-23x86: don't use 32-bit LEA as NOP surrogate in 64-bit codeJan Beulich3-197/+41
Except for the shared 1- and 2-byte cases, the LEA uses corrupt %rsi (by zero-extending %esi to %rsi). Introduce separate 64-bit patterns which keep %rsi intact.
2023-10-23x86: i386_generate_nops() may not derive decisions from global variablesJan Beulich7-2/+43
What matters is what was in effect at the time the original directive was issued. Later changes to global state (bitness or ISA) must not affect what code is generated.
2023-10-23x86: record flag_code in tc_frag_dataJan Beulich2-14/+16
The recorded value, and not the global variable, will want using in TC_FRAG_INIT(). The so far file scope variable therefore needs to become external, to be accessible there.
2023-10-20gas: testsuite: microblaze: cosmetic fixNeal Frager1-1/+1
This patch makes a cosmetic change to the reloc_weaksym.s by making the bneid instruction all lower case like all of the other instructions in the example. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-20bfd: microblaze: Add 32_NONE reloc typeNeal Frager3-1/+12
This patch adds the R_MICROBLAZE_32_NONE relocation type. This is a 32-bit reloc that stores the 32-bit pc relative value in two words (with an imm instruction). Add test case to gas test suite. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-19opcodes: microblaze: Fix bit masking bugNeal Frager1-2/+2
There is currently a bug in the bit masking for the barrel shift instructions because the bit mask is not including all of the register bits which must be zero. With this patch, the disassembler can be sure that the 32-bit value is indeed a barrel shift instruction and not a data value in memory. This fix can be verified by assembling and disassembling the following: .text .long 0x65005f5f With this patch, the bug is fixed, and the objdump will know that 0x65005f5f is not a barrel shift instruction. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-18RISC-V: Make sure rv32q conflict won't affect the zfa gas testcases.Nelson Chu2-2/+2
According to the commit 51498ab9abc6, the q extension was no longer allowed for rv32 since version 2.2. Therefore, make sure the version of q is larger than 2.2, in case the new extension conflict breaks the toolchain regressions, which built with the old -misa-spec. gas/ * testsuite/gas/riscv/zfa-zvfh.d: Set q to v2.2. * testsuite/gas/riscv/zfa.d: Likewise.
2023-10-17gas: testsuite: microblaze: Add new bit-field testsNeal Frager2-1/+14
This patch adds new gas tests for the microblaze bsefi and bsifi instructions. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-16RISC-V: Add "lp64e" ABI supportTsukasa OI5-7/+8
Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise.
2023-10-16RISC-V: Remove RV64E conflictTsukasa OI2-5/+0
Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed.
2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+82
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref With version 6 of the patch, no new relocation types are added as this was unnecessary for adding the bsefi and bsifi instructions. FIXED: Segfault caused by incorrect termination of microblaze_opcodes. Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-10LoongArch/GAS: Add support for branch relaxationmengqinggang5-41/+355
For the instructions of R_LARCH_B16/B21, if the immediate overflow, add a B instruction and R_LARCH_B26 relocation. For example: .L1 ... blt $t0, $t1, .L1 R_LARCH_B16 change to: .L1 ... bge $t0, $t1, .L2 b .L1 R_LARCH_B26 .L2
2023-10-08Add testsuits for new assembler option of mthin-add-sub.gdb-14-branchpointcailulu6-24/+131
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu2-6/+36
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame.
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-76/+1
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+76
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-05aarch64: Enable Cortex-X4 CPUSaurabh Jha4-1/+12
2023-10-02Fix memory leak in RiscV assembler.Nick Clifton2-0/+7
PR 30861 * config/tc-riscv.c (riscv_insert_uleb128_fixes): Release duplicated memory.
2023-09-29tc-microblaze.c - int compare for X_add_number.Neal Frager1-1/+1
The range check should be checking for the range ffffffff80000000..7fffffff, not ffffffff70000000. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-28Added support in gas for mlittle-endian and mbig-endian flags as options.Michael J. Eager3-1/+22
Updated show usage for MicroBlaze specific assembler options to include new entries. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> --- V1->V2: - removed new options which were unnecessary - added documentation for MicroBlaze specific options Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-27x86: prefer VEX encodings over EVEX ones when possibleJan Beulich10-10/+246
AVX-* features / insns paralleling earlier introduced AVX512* ones can be encoded more compactly when the respective feature was explicitly enabled by the user.
2023-09-27x86: drop cpu_arch_tune_flagsJan Beulich1-22/+4
Apparently from its introduction the variable was only ever written (the only read is merely to determine whether to write it with another value). (Since, due to the need to re-indent, the adjacent lines setting cpu_arch_tune need touching anyway, switch to using PREOCESSOR_* constants where applicable, to make more obvious what the resulting state is going to be.)
2023-09-27x86: correct cpu_arch_isa_flags maintenanceJan Beulich4-47/+83
These may not be set from a value derived from cpu_arch_flags: That starts with (almost) all functionality enabled, while cpu_arch_isa_flags is supposed to track features that were explicitly enabled (and perhaps later disabled) by the user. To avoid needing to do any such adjustment in two places (each), introduce helper functions used by both command line handling and directive processing.
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-0/+4
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for FMA ones as well, requiring one further adjustment to cpu_flags_match().
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-4/+12
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for VAES and VPCLMULQDQ ones as well.
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-5/+102
In anticipation of APX introduce logic to reduce the number of templates we have now, allowing to limit some the number of ones we then need to gain. The fundamental requirements are that - attributes be compatible, which specifically means VexW needs to be the same in the templates (which often isn't the case, for VEX encodings having far more WIG tha, EVEX ones), - the EVEX form being AVX512F (with or without AVX512VL), not any of its extensions (the same will then be required for APX - it'll need to be APX_F). Note that in check_register() there's now a redundant zmm check. Since this logic will need revisiting for APX anyway, I'd like to keep it that way for now. (Similarly a couple of if()-s which could be folded are kept separate, to reduce code churn when adding APX support.)
2023-09-27x86: tighten .insn SAE and broadcast checkingJan Beulich1-2/+3
SAE / embedded rounding are invalid when there's the memory operand, as the bit encoding this specifies broadcast in that case. Broadcast needs to be specified on the memory operand.
2023-09-27x86-64: REX.W overrides DATA_PREFIXJan Beulich1-2/+5
REX.W needs to be respected when immediate size and relocation type are determined.
2023-09-27x86-64: fix suffix-less PUSH of symbol addressJan Beulich3-1/+18
PR gas/30856 In 5cc007751cdb ("x86: further adjust extend-to-32bit-address conditions") I neglected the case of PUSH, which is the only insn allowing (proper) symbol addresses to be used as immediates (not displacements, like CALL/JMP) in the absence of any register operands. Since it defaults to 64-bit operand size, guessing an L suffix is wrong there.
2023-09-27Add support for "pcaddi rd, symbol"mengqinggang6-155/+174
Add a macro pcaddi instruction to support "pcaddi rd, symbol". pcaddi has a 20-bit signed immediate, it can address a +/- 2MB pc relative address, and the address should be 4-byte aligned.
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-300/+162
The AArch64 feature-flag code is currently limited to a maximum of 64 features. This patch reworks it so that the limit can be increased more easily. The basic idea is: (1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum counting bit positions. (2) Make the feature-list macros take an array index argument (currently always 0). The macros then return the aarch64_feature_set contents for that array index. An N-element array would then be initialised as: { MACRO (0), ..., MACRO (N - 1) } (3) Provide convenience macros for initialising an aarch64_feature_set for: - a single feature - a list of individual features - an architecture version - an architecture version + a list of additional features (2) and (3) use the preprocessor to generate static initialisers. The main restriction was that uses of the same preprocessor macro cannot be nested. So if a macro wants to do something for N individual arguments, it needs to use a chain of N macros to do it. There then needs to be a way of deriving N, as a preprocessor token suitable for pasting. The easiest way of doing that was to precede each list of features by the number of features in the list. So an aarch64_feature_set initialiser for three features A, B and C would be written: AARCH64_FEATURES (3, A, B, C) This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-25Revert "arc: Add new GAS tests for ARCv3."Claudiu Zissulescu17-920/+0
This reverts commit 462693a455f04fc52c1c91ffc52ea2446a086444.
2023-09-25Revert "arc: Update ARC's Gnu Assembler backend with ARCv3 ISA."Claudiu Zissulescu6-563/+241
This reverts commit f3d38d7d0b7346515ba603454feeddc58a3fc451.
2023-09-25Revert "arc: Update arc's gas tests"Claudiu Zissulescu17-53/+53
This reverts commit ef90c0991e78c28bebdd3ed31a77c05be0444191.
2023-09-25Revert "arc: Update NEWS files"Claudiu Zissulescu1-2/+0
This reverts commit a47d304b1229ecf8912fac17ee9c48d1bf3c729a.
2023-09-25arc: Update NEWS filesClaudiu Zissulescu1-0/+2
Add ARCv3 support in NEWS files. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-09-25arc: Update arc's gas testsClaudiu Zissulescu17-53/+53
The disassembler can recognize the alternative register names ILINK1 and ILINK2. Update tests. gas/testsuite/gas/arc xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/testsuite/gas/arc/adc.d: Update ILINK1/INLINK2 reg names. * gas/testsuite/gas/arc/add.d: Likewise. * gas/testsuite/gas/arc/and.d: Likewise. * gas/testsuite/gas/arc/asl.d: Likewise. * gas/testsuite/gas/arc/asr.d: Likewise. * gas/testsuite/gas/arc/bic.d: Likewise. * gas/testsuite/gas/arc/lsr.d: Likewise. * gas/testsuite/gas/arc/nps400-1.d: Likewise. * gas/testsuite/gas/arc/or.d: Likewise. * gas/testsuite/gas/arc/ror.d: Likewise. * gas/testsuite/gas/arc/sbc.d: Likewise. * gas/testsuite/gas/arc/sub.d: Likewise. * gas/testsuite/gas/arc/textinsn3op.d: Likewise. * gas/testsuite/gas/arc/warn.exp: Update predicate. * gas/testsuite/gas/arc/arc.exp: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Update ARC's Gnu Assembler backend with ARCv3 ISA.Claudiu Zissulescu6-241/+563
The new Synopsys ARCv3 ISA has a similar instruction format like the old ARCv1 and ARCv2 ISA. Thus, the ARCv3 addition is using whatever we have for old ARC processors plus some ARCv3 spcific mods. To distinguish between various ARC variants, we introduced two new configure defines named TARGET_ARCv3_32 and TARGET_ARCv3_64 which are set when we choose either an ARC32 (ARCv3/32) ISA toolchain or an ARC64 (ARCv3/64) ISA toolchain. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/config/tc-arc.h: Selectively define default target macros. * gas/configure.ac: Add ARC64 target. * gas/configure.tgt: Likewise. * gas/configure: Regenerate * gas/config.in: Regenerate. * gas/config/tc-arc.c (DEFAULT_ARCH): New macro. (default_arch): New variable. (md_pseudo_table): Add xword. (md_shortopts): Only a few options are recognized by the new ARC64 assembler. (md_longopts): Likewise. (ARC_CPU_TYPE_A64x): New define. (ARC_CPU_TYPE_A32x): Likewise. (cpu_type): New arch field. (selected_cpu): Update fields. (arc_opcode_hash_entry_iterator_init): Formating. (arc_opcode_hash_entry_iterator_next): Likewise. (arc_select_cpu): Likewise. (arc_option): Likewise. (check_cpu_feature): Likewise. (debug_exp): Recognize new expression operands. (parse_reloc_symbol): Parse new signed/unsigend cases. (parse_opcode_flags): Update for the case when the flags needs insert/extract functions. (find_opcode_match): Match new signed/unsigned 32-bit immediates. (autodetect_attributes): PLT34 only available for ARC64. (md_assemble): Extend match characters. (declare_fp_set): New function. (init_default_arch): Likewise. (md_begin): Detect and initialize the correct CPU and coresponding registers. (md_pcrel_from_section): Add new relocs. (arc_target_format): New function. (md_apply_fix): Add new relocs. (md_parse_option): Update options. (arc_show_cpu_list): Update with ARC64 cpus. (md_show_usage): Update messages. (may_relax_expr): Add PLT34 case. (assemble_insn): Update for ARC64. (arc_make_nops): New function. (arc_handle_align): Refurbish this function, use arc_make_nops. (tc_arc_fix_adjustable): Update messages. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Add new GAS tests for ARCv3.Claudiu Zissulescu17-0/+920
Add new assembler tests for ARCv3 ISA. All the new tests are added in a distinct folder named arc64. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/testsuite/gas/arc64/arc64.exp: New file. * gas/testsuite/gas/arc64/float01.d: Likewise. * gas/testsuite/gas/arc64/float01.s: Likewise. * gas/testsuite/gas/arc64/ldd.d: Likewise. * gas/testsuite/gas/arc64/ldd.s: Likewise. * gas/testsuite/gas/arc64/lddl.d: Likewise. * gas/testsuite/gas/arc64/lddl.s: Likewise. * gas/testsuite/gas/arc64/load.d: Likewise. * gas/testsuite/gas/arc64/load.s: Likewise. * gas/testsuite/gas/arc64/st.d: Likewise. * gas/testsuite/gas/arc64/st.s: Likewise. * gas/testsuite/gas/arc64/std.d: Likewise. * gas/testsuite/gas/arc64/std.s: Likewise. * gas/testsuite/gas/arc64/stdl.d: Likewise. * gas/testsuite/gas/arc64/stdl.s: Likewise. * gas/testsuite/gas/arc64/stl.d: Likewise. * gas/testsuite/gas/arc64/stl.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-20elf-attrs.c memory allocation failAlan Modra9-81/+137
Report errors rather than segfaulting. bfd/ * elf-attrs.c (elf_new_obj_attr): Return NULL on bfd_alloc fail. (bfd_elf_add_obj_attr_int): Handle NULL return from the above, and propagate return to callers. (elf_add_obj_attr_string, elf_add_obj_attr_int_string): Likewise. (bfd_elf_add_obj_attr_string): Similarly. (_bfd_elf_copy_obj_attributes): Report error on alloc fails. (_bfd_elf_parse_attributes): Likewise. * elf-bfd.h (bfd_elf_add_obj_attr_int): Update prototype. (bfd_elf_add_obj_attr_string): Likewise. (bfd_elf_add_obj_attr_int_string): Likewise. gas/ * config/obj-elf.c (obj_elf_vendor_attribute): Report fatal error on out of memory from bfd attribute functions. * config/tc-arc.c (arc_set_attribute_int): Likewise. (arc_set_attribute_string, arc_set_public_attributes): Likewise. * config/tc-arm.c (aeabi_set_attribute_int): Likewise. (aeabi_set_attribute_string): Likewise. * config/tc-mips.c (mips_md_finish): Likewise. * config/tc-msp430.c (msp430_md_finish): Likewise. * config/tc-riscv.c (riscv_write_out_attrs): Likewise. * config/tc-sparc.c (sparc_md_finish): Likewise. * config/tc-tic6x.c (tic6x_set_attribute_int): Likewise. * config/tc-csky.c (md_begin): Likewise. (set_csky_attribute): Return ok status.
2023-09-18Fix: Use of uninitialized memoryJacob Navia2-1/+6
* config/tc-riscv.c (riscv_ip_hardcode): Fully initialise the allocated riscv_opcode structure.
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