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2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento3-0/+67
Implement, together with the necessary tests, the following new LSE128 atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); gas/ChangeLog: * testsuite/gas/aarch64/lse128-atomic.d: New. * testsuite/gas/aarch64/lse128-atomic.s: Likewise. opcodes/ChangeLog: * aarch64-tbl.h (ldclrp): new _LSE128_INSN entry. (ldclrpa): Likewise. (ldclrpal): Likewise. (ldclrpl): Likewise. (ldsetp): Likewise. (ldsetpa): Likewise. (ldsetpal): Likewise. (ldsetpl): Likewise. (swpp): Likewise. (swppa): Likewise. (swppal): Likewise. (swppl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento2-0/+3
Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise.
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+5
Given the particular encoding of the LSE128 instructions, create the necessary shared input+output operand register description and handling in the code to allow for the encoding of the LSE128 128-bit atomic operations. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): opcodes/ChangeLog: * aarch64-opc.c (fields): (aarch64_print_operand): * aarch64-opc.h (enum aarch64_field_kind): * aarch64-tbl.h (AARCH64_OPERANDS):
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento4-0/+13
Add Binutils support for system registers associated with the Translation Hardening Extension (THE). In doing so, we also add core feature support for THE, enabling its associated feature flag and implementing the necessary feature-checking machinery. Regression tested on aarch64-linux-gnu, no regressions. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier. * doc/c-aarch64.texi (AArch64 Extensions): Update documentation for `the' option. * testsuite/gas/aarch64/sysreg-8.s: Add tests for `the' associated system registers. * testsuite/gas/aarch64/sysreg-8.d: Likewise. include/ChangeLog: * opcode/aarch64.h (enum aarch64_feature_bit): Add AARCH64_FEATURE_THE. opcode/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the' system register check support. * aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1' * aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett31-0/+671
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett10-0/+557
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-06RISC-V: Make sure rv32q conflict won't affect the fp-q-insns-32 gas testcase.Nelson Chu1-1/+1
Same as commit 4352c0ac04a. gas/ * testsuite/gas/riscv/fp-q-insns-32.d: Set q to v2.2.
2023-11-03gas: correct ignoring of C-style number suffixesJan Beulich4-4/+116
First of all the respective original changes didn't deal with just 0 having such a suffix - this needs additional logic outside of integer_constant(). Further bogus suffixes having more than two L-s were accepted, while valid suffixes with U following the L(s) weren't. Finally respective tests were introduced for Sparc only. Reviewed-by: Neal Frager <neal.frager@amd.com>
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-85/+6
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and FS{H,W,D,Q} the sole difference between the handling is the insn mnemonic passed to the common handling functions. The intended mnemonic, however, can easily be retrieved. Furthermore leverags that Sx and FSx are then handled identically, too, and hence their cases can also be folded.
2023-11-03RISC-V: Lx/Sx macro insn testsJan Beulich2-0/+70
Make sure these (continue to) work as intended.
2023-11-03RISC-V: add F- and D-extension testcasesJan Beulich10-0/+1111
Make sure future changes won't regress any of this. Also cover the FLH and FSH macro insns of the Zfh extension.
2023-11-03RISC-V: make FLQ/FSQ macro-insns workJan Beulich5-0/+516
When support for the Q extension was added, the libopcodes side of these macro-insns was properly covered, but no backing support in gas was added. In new testcases cover not just these, but all Q-extension insns.
2023-11-02aarch64: Add GCS system registers.Srinath Parvathaneni4-0/+73
This patch adds support for 10 new AArch64 system registers (gcscre0_el1, gcscr_el1, gcscr_el12, gcscr_el2, gcscr_el3, gcspr_el0, gcspr_el1 ,gcspr_el12, gcspr_el2 and gcspr_el3), which are enabled on using Guarded Control Stack (+gcs flag) feature.
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni7-64/+45
This patch adds support for Guarded control stack data synchronization instruction (GCSB DSYNC). This instruction is allocated to existing HINT space and uses the HINT number 19 and to match this an entry is added to the aarch64_hint_options array.
2023-11-02aarch64: Add support for GCS extension.srinath7-0/+126
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is optional from Armv9.4-A architecture and enabled by passing +gcs option to -march (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file. Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx, gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni9-10/+67
This patch adds support for Check Feature Status Extension (CHK) which is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction (hint #40).
2023-11-02aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.srinath3-2/+6
This patch adds AArch64 support for Armv8.9-A architecture (-march=armv8.9-a) and Armv9.4-A architecture (-march=armv9.4-a).
2023-10-31Support Intel USER_MSRHu, Lin112-5/+208
This patches aims to support Intel USER_MSR. In addition to the usual support, this patch includes encoding and decoding support for MAP7 and immediate numbers as the last operand (ATT style). gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit mode. (build_vex_prefix): Add VEXMAP7. (md_assemble): Handling the imm32 of USER_MSR. (match_template): Handling the unusual immediate. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add a new attribute has_skipped_modrm. (Gq): New. (Rq): Ditto. (q_mm_mode): Ditto. (Nq): Change mode from q_mode to q_mm_mode. (VEX_LEN_TABLE): (get_valid_dis386): Add VEX_MAP7 in VEX prefix. and handle the map7_f8 for save space. (OP_Skip_MODRM): Set has_skipped_modrm. (OP_E): Skip codep++ when has skipped modrm byte. (OP_R): Support q_mode and q_mm_mode. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated.
2023-10-30gas: bpf: new test for MOV with C-like numbers ll suffixJose E. Marchesi4-0/+11
The BPF pseudo-c syntax supports both MOV and LDDW instructions: mov: r1 = EXPR lddw: r1 = EXPR ll Note that the white space between EXPR and `ll' is necessary in order to avoid ambiguity with the assembler's support for C-like numerical suffixes. This patch adds a new test to the GAS BPF testsuite to make sure that instructions like: r1 = 666ll are interpreted as `mov %r1,666', not as `lddw %r1,666'. This matches clang's assembler behavior. 2023-10-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu-pseudoc.s: Add test to make sure C-like suffix `ll' is not interpreted as lddw syntax. * testsuite/gas/bpf/alu-pseudoc.d: Update expected results. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-10-28gas: tc-bpf.c: fix formatting of commentJose E. Marchesi1-4/+5
2023-10-27RISC-V: Clarify the behaviors of SET/ADD/SUB relocations.Nelson Chu1-0/+1
We are used to generate these kinds of relocations by data directives. Considering the following example, .word (A + 3) - (B + 2) The GAS will generate a pair of ADD/SUB for this, R_RISCV_ADD, A + 1 R_RISCV_SUB, 0 The addend of R_RISCV_SUB will always be zero, and the summary of the constants will be stored in the addend of R_RISCV_ADD/SET. Therefore, we can always add the addend of these data relocations when doing relocations. But unfortunately, I had heard that if we are using .reloc to generate the data relocations will make the relocations failed. Refer to this, .reloc offset, R_RISCV_ADD32, A + 3 .reloc offset, R_RISCV_SUB32, B + 2 .word 0 Then we can get the relocations as follows, R_RISCV_ADD, A + 3 R_RISCV_SUB, B + 2 Then... Current LD does the relocation, B - A + 3 + 2, which is wrong obviously... So first of all, this patch fixes the wrong relocation behavior of R_RISCV_SUB* relocations. Afterwards, considering the uleb128 direcitve, we will get a pair of SET_ULEB128/SUB_ULEB128 relocations for it for now, .uleb128 (A + 3) - (B + 2) R_RISCV_SET_ULEB128, A + 1 R_RISCV_SUB_ULEB128, B + 1 Which looks also wrong obviously, the summary of the constants should only be stored into the addend of SET_ULEB128, and the addend of SUB_ULEB128 should be zero like other SUB relocations. But the current LD will still get the right relocation values since we only add the addend of SUB_ULEB128 by accident... Anyway, this patch also fixes the behaviors above, to make sure that no matter using .uleb128 or .reloc directives, we should always get the right values. bfd/ * elfnn-riscv.c (perform_relocation): Clarify that SUB relocations should substract the addend, rather than add. (riscv_elf_relocate_section): Since SET_ULEB128 won't go into perform_relocation, we should add it's addend here in advance. gas/ * config/tc-riscv.c (riscv_insert_uleb128_fixes): Set the addend of SUB_ULEB128 to zero since it should already be added into the addend of SET_ULEB128.
2023-10-24as: fixed internal error when immediate value of relocation overflow.Lulu Cai7-1/+21
The as and ld use _bfd_error_handler to output error messages when checking relocation alignment and relocation overflow. However, the abfd value passed by as to the function is NULL, resulting in an internal error. The ld passes a non-null value to the function, so it can output an error message normally.
2023-10-23gas: make .nops output visible in listingJan Beulich5-2/+71
Due to using a different frag type (in turn due to storing data differently), making the resulting code appear in listings requires special handling.
2023-10-23x86: fold NOP testcase expectations where possibleJan Beulich14-2340/+14
Like done earlier for files needing adjustment anyway, also do this for the remaining set.
2023-10-23x86: fold a few of the "alternative" NOP patternsJan Beulich1-6/+3
Since named objects may not overlap, the compiler is not permitted to do this for us, to avoid wasting space and cache bandwidth/capacity.
2023-10-23x86: add a few more NOP patternsJan Beulich32-2270/+465
First of all add f32_5[], allowing to eliminate the extra slot-is-NULL code from i386_output_nops(). Plus then introduce f32_8[] and f16_5[] following the same concept of adding a %cs segment override prefix. Also re-use patterns when possible and correct comments as applicable. Similarly re-use testcase expectations as much as possible, where they need touching anyway.
2023-10-23x86: don't record full i386_cpu_flags in struct i386_tc_frag_dataJan Beulich2-4/+4
We only use a single bit of this ever growing structure.
2023-10-23x86: i686 != PentiumProJan Beulich2-3/+6
The two are distinct in opcodes/, distinguished precisely by CpuNOP that's relevant in i386_generate_nops(), yet the function has the PPro case label in the other group. Simply removing it revealed that cpu_arch[] had a wrong entry for i686. While there also add PROCESSOR_IAMCU to the respective comment.
2023-10-23x86: respect ".arch nonop" when selecting which NOPs to emitJan Beulich5-27/+23
Making GENERIC64 a special case was never correct; prior to the generalization of ".arch .no*" to cover all ISA extensions other processor families supporting long NOPs should have been covered as well. When introducing ".arch .nonops" (among others) it wasn't apparent that a hidden implication of .cpunop not being possible to separately turn off existed here. Seeing that the two large case label blocks in the 2nd switch() already had identical behavior, simply collapse all of the (useful) case labels into a single "default" one.
2023-10-23x86: don't use operand size override with NOP in 16-bit codeJan Beulich4-11/+12
Since we don't key the NOP selection to user-controlled properties, we may not use i386 features; otherwise we would violate a possible .arch directive restricting ISA to pre-386.
2023-10-23x86: don't use 32-bit LEA as NOP surrogate in 64-bit codeJan Beulich3-197/+41
Except for the shared 1- and 2-byte cases, the LEA uses corrupt %rsi (by zero-extending %esi to %rsi). Introduce separate 64-bit patterns which keep %rsi intact.
2023-10-23x86: i386_generate_nops() may not derive decisions from global variablesJan Beulich7-2/+43
What matters is what was in effect at the time the original directive was issued. Later changes to global state (bitness or ISA) must not affect what code is generated.
2023-10-23x86: record flag_code in tc_frag_dataJan Beulich2-14/+16
The recorded value, and not the global variable, will want using in TC_FRAG_INIT(). The so far file scope variable therefore needs to become external, to be accessible there.
2023-10-20gas: testsuite: microblaze: cosmetic fixNeal Frager1-1/+1
This patch makes a cosmetic change to the reloc_weaksym.s by making the bneid instruction all lower case like all of the other instructions in the example. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-20bfd: microblaze: Add 32_NONE reloc typeNeal Frager3-1/+12
This patch adds the R_MICROBLAZE_32_NONE relocation type. This is a 32-bit reloc that stores the 32-bit pc relative value in two words (with an imm instruction). Add test case to gas test suite. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-19opcodes: microblaze: Fix bit masking bugNeal Frager1-2/+2
There is currently a bug in the bit masking for the barrel shift instructions because the bit mask is not including all of the register bits which must be zero. With this patch, the disassembler can be sure that the 32-bit value is indeed a barrel shift instruction and not a data value in memory. This fix can be verified by assembling and disassembling the following: .text .long 0x65005f5f With this patch, the bug is fixed, and the objdump will know that 0x65005f5f is not a barrel shift instruction. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-18RISC-V: Make sure rv32q conflict won't affect the zfa gas testcases.Nelson Chu2-2/+2
According to the commit 51498ab9abc6, the q extension was no longer allowed for rv32 since version 2.2. Therefore, make sure the version of q is larger than 2.2, in case the new extension conflict breaks the toolchain regressions, which built with the old -misa-spec. gas/ * testsuite/gas/riscv/zfa-zvfh.d: Set q to v2.2. * testsuite/gas/riscv/zfa.d: Likewise.
2023-10-17gas: testsuite: microblaze: Add new bit-field testsNeal Frager2-1/+14
This patch adds new gas tests for the microblaze bsefi and bsifi instructions. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-16RISC-V: Add "lp64e" ABI supportTsukasa OI5-7/+8
Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise.
2023-10-16RISC-V: Remove RV64E conflictTsukasa OI2-5/+0
Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed.
2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+82
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref With version 6 of the patch, no new relocation types are added as this was unnecessary for adding the bsefi and bsifi instructions. FIXED: Segfault caused by incorrect termination of microblaze_opcodes. Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-10LoongArch/GAS: Add support for branch relaxationmengqinggang5-41/+355
For the instructions of R_LARCH_B16/B21, if the immediate overflow, add a B instruction and R_LARCH_B26 relocation. For example: .L1 ... blt $t0, $t1, .L1 R_LARCH_B16 change to: .L1 ... bge $t0, $t1, .L2 b .L1 R_LARCH_B26 .L2
2023-10-08Add testsuits for new assembler option of mthin-add-sub.gdb-14-branchpointcailulu6-24/+131
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu2-6/+36
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame.
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-76/+1
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-1/+76
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-05aarch64: Enable Cortex-X4 CPUSaurabh Jha4-1/+12
2023-10-02Fix memory leak in RiscV assembler.Nick Clifton2-0/+7
PR 30861 * config/tc-riscv.c (riscv_insert_uleb128_fixes): Release duplicated memory.
2023-09-29tc-microblaze.c - int compare for X_add_number.Neal Frager1-1/+1
The range check should be checking for the range ffffffff80000000..7fffffff, not ffffffff70000000. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-28Added support in gas for mlittle-endian and mbig-endian flags as options.Michael J. Eager3-1/+22
Updated show usage for MicroBlaze specific assembler options to include new entries. This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> --- V1->V2: - removed new options which were unnecessary - added documentation for MicroBlaze specific options Signed-off-by: Michael J. Eager <eager@eagercon.com>
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