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2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI12-0/+125
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI12-0/+817
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI12-0/+525
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-28RISC-V: Add new CSR feature gate handling (RV32,H)Tsukasa OI1-4/+7
To support feature gate like Smstateen && H, this commit adds certain CSR feature gate handling. It also changes how RV32-only CSRs are handled for cleanliness. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Add CSR feature gate handling for H. Change handling on RV32.
2022-06-27drop XC16x bitsJan Beulich55-2676/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu6-15/+0
This patch has been pending for almost a year... However, I noticed that llvm can already re-order the extensions, even if they are out of orders. Not really sure if they can also re-order the single letter extensions, but at least we can do this for the multi-letter extensions in binutils. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are used to check the prefixed extension orders. gas/ * testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help tp reorder the prefixed extensions for now. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.d: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu12-309/+361
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22RISC-V: Fix inconsistent error message (range)Tsukasa OI1-1/+1
This commit fixes inconsistent error message format involving compressed funct<n> fields. In specific, funct6 had an error message with range 0..2^<n> ("0..64") unlike other funct<n> fields with 0..2^<n>-1 (e.g. funct4 with "0..15"). gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Fix inconsistent error message.
2022-06-17PR29256, memory leak in obj_elf_section_nameAlan Modra1-14/+18
When handling section names in quotes obj_elf_section_name calls demand_copy_C_string, which puts the name on the gas notes obstack. Such strings aren't usually freed, since obstack_free frees all more recently allocated objects as well as its arg. When handling non-quoted names, obj_elf_section_name mallocs the name. Due to the mix of allocation strategies it isn't possible for callers to free names, if that was desirable. Partially fix this by always creating names on the obstack, which is more efficient anyway. (You still can't obstack_free on error paths due to the xtensa tc_canonicalize_section_name.) Also remove a couple of cases where the name is dup'd for no good reason as far as I know. PR 29256 * config/obj-elf.c (obj_elf_section_name): Create name on notes obstack. (obj_elf_attach_to_group): Don't strdup group name. (obj_elf_section): Likewise. (obj_elf_vendor_attribute): Use xmemdup0 rather than xstrndup.
2022-06-16use of uninitialised value in input_file_openAlan Modra1-7/+7
Triggered by a file containing just "#N" or "#A". fgets when hitting EOF before reading anything returns NULL and does not write to buf. strchr (buf, '\n') then is reading from uninitialised memory. * input-file.c (input_file_open): Don't assume buf contains zero string terminator when fgets returns NULL.
2022-06-16Restore readelf -wFAlan Modra1-1/+1
Commit 94585d6d4495 resulted in readelf -wF failing with Unrecognized debug letter option 'F' binutils/ * dwarf.c (debug_dump_long_opts): Add letter. (debug_option_table): New, replacing.. (opts_table, letter_table): ..these. (dwarf_select_sections_by_names): Adjust to suit. Set do_debug_frames outside of loop. (dwarf_select_sections_by_letters): Similarly. gas/ * testsuite/gas/i386/ehinterp.d: Use readelf -wF.
2022-06-16PR29250, readelf erases CIE initial register stateAlan Modra3-1/+56
PR 29250 binutils/ * dwarf.c (display_debug_frames): Set col_type[reg] on sizing pass over FDE to cie->col_type[reg] if CIE specifies reg. Handle DW_CFA_restore and DW_CFA_restore_extended on second pass using the same logic. Remove unnecessary casts. Don't call frame_need_space on second pass over FDE. gas/ * testsuite/gas/i386/ehinterp.d, * testsuite/gas/i386/ehinterp.s: New test. * testsuite/gas/i386/i386.exp: Run it.
2022-06-14BFD_RELOC_MIPS_16Alan Modra1-8/+8
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation, since R_MIPS_16 specifies a 16-bit field in a 32-bit word. BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data directives, expects fixups to operate on the whole of a 16-bit word. This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in md_apply_fix for cases where the fixup can be applied at assembly time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object file relocation, and thus .half, .hword, .short and .dc.w must be resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this patch since it isn't used. PR 3243 PR 26542 * reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16. * elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16. * elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16. * elfn32-mips.c (mips_reloc_map): Likewise. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16. (macro_build): Likewise. (mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16. (md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done. ld/ * testsuite/ld-mips-elf/reloc-local-overflow.d, * testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
2022-06-14gas dwarf2dbg.c tidyAlan Modra5-41/+81
Make it a little more obvious that remap_debug_filename returns an allocated string (that should be freed) by returning a char * rather than const char *. Free a few missed cases in dwarf2dbg.c, and free other memory allocated in dwarf2dbg.c. Also remove static initialisation of variables and initialise in dwarf2_init instead, in order to ensure gas state is saner for oss-fuzz. * remap.c (remap_debug_filename): Remove const from return. * as.h (remap_debug_filename): Update prototype. * config/obj-elf.c (obj_elf_ident): Simplify free of remap_debug_filename output. * stabs.c (stabs_generate_asm_file): Likewise. * dwarf2dbg.c (dirs, dirs_in_use, dirs_allocated, current): Don't initialise statically.. (dwarf2_init): ..do so here, along with most other static vars. (assign_file_to_slot): Don't set files_allocated until we succeed in allocating memory. (purge_generated_debug): Add bool param, free more stuff if true. (dwarf2_directive_filename): Adjust purge_generated_debug call. (process_entries): Don't free line_entry here.. (dwarf2_cleanup): ..do so here instead, new function. (dwarf2_finish): Call dwarf2_cleanup. When chaining together subseg line entries, unhook entries from old subseg list. (dwarf2_directive_loc): Free remap_debug_filename string. (out_dir_and_file_list): Likewise. (out_debug_str): Likewise.
2022-06-08asan: double free sb_killAlan Modra1-2/+1
oss-fuzz hits a flaky crash with a double-free. I think this is due to gas static state not being reinitialised between testcases, a bug with oss-fuzz not gas. Anyway, this patch should avoid the problem. * input-scrub.c (input_scrub_push): Move init of sb_index.. (input_scrub_reinit): ..to here.
2022-06-03Re: ubsan: undefined shift in frag_align_codeAlan Modra1-1/+2
This one needs the same fix too. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Avoid signed integer overflow.
2022-06-03x86: exclude certain ISA extensions from v3/v4 ISAJan Beulich8-4/+43
Like TBM and LWP, XOP and FMA4 also shouldn't be included in v3. Like AVX512-4VNNIW, AVX512-4FMAPS also shouldn't be included in v4.
2022-06-02Re: ubsan: signed integer overflow in atof_genericAlan Modra1-0/+1
Oops. * atof-generic.c: Include limits.h.
2022-06-02ubsan: signed integer overflow in atof_genericAlan Modra1-8/+8
Fix the signed overflows by using unsigned variables and detect overflow at BUG! comment. * atof-generic.c (atof_generic): Avoid signed integer overflow. Return ERROR_EXPONENT_OVERFLOW if exponent overflows a long.
2022-06-02ubsan: undefined shift in frag_align_codeAlan Modra1-1/+1
* frags.c (MAX_MEM_FOR_RS_ALIGN_CODE): Avoid signed integer overflow.
2022-06-02gas read_a_source_file #APP processingAlan Modra1-91/+10
This fixes some horrible code using do_scrub_chars. What we had ran text through do_scrub_chars twice, directly in read_a_source_file and again via the input_scrub_include_sb call. That's silly, and since do_scrub_chars is a state machine, possibly wrong. More silliness is evident in the temporary malloc'd buffer for do_scrub_chars output, which should have been written directly to sbuf. So, get rid of the do_scrub_chars call and support functions, leaving scrubbing to input_scrub_include_sb. I did wonder about #NO_APP overlapping input_scrub_next_buffer buffers, but that should only happen if the string starts in one file and finishes in another. * read.c (scrub_string, scrub_string_end): Delete. (scrub_from_string): Delete. (read_a_source_file): Rewrite #APP processing.
2022-06-02sb_scrub_and_add_sb not draining input string bufferAlan Modra1-2/+14
It is possible for sb_scrub_and_add_sb to not consume all of the input string buffer. If this happens for reasons explained in the comment, do_scrub_chars can leave pointers to the string buffer for the next call. This patch fixes that by ensuring the input is drained. Note that the behaviour for an empty string buffer is also changed, avoiding another do_scrub_chars bug where empty input and single char sized output buffers could result in a write past the end of the output. sb.c (sb_scrub_and_add_sb): Loop until all of input sb is consumed.
2022-06-02asan: heap buffer overflow in dwarf2_directive_filenameAlan Modra1-3/+5
Seen with .file 4294967289 "xxx.c" * dwarf2dbg.c (assign_file_to_slot): Catch more cases of integer overflow. Make param i an unsigned int.
2022-05-31ia64 gas: Remove unnecessary initAlan Modra1-2/+0
The whole struct is cleared by alloc_record. * config/tc-ia64.c (output_prologue, output_prologue_gr): Don't zero r.record.r.mask.
2022-05-31Trailing spaces in objdump -r headerAlan Modra106-142/+142
git commit 202be274a4 went a little wild in removing trailing spaces in gas/testsuite/gas/i386/{secidx.d,secrel.d}, causing x86_64-w64-mingw32 +FAIL: i386 secrel reloc x86_64-w64-mingw32 +FAIL: i386 secidx reloc I could have just replaced the trailing space, but let's fix the objdump output instead. Touches lots of testsuite files.
2022-05-30Fix failing test for armeb-gnu-eabiLuis Machado1-18/+2
The following test fails on the armeb-gnu-eabi target: FAIL: Unwind information for Armv8.1-M.Mainline PACBTI extension This patch adjusts the expected output for big endian.
2022-05-30RISC-V: Add zhinx extension supports.jiawei2-0/+125
The zhinx extension is a sub-extension in zfinx, corresponding to zfh extension but use GPRs instead of FPRs. This patch expanded the zfh insn class define, since zfh and zhinx use the same opcodes, thanks for Nelson's works. changelog in V2: Add missing classes of 'zfh' and 'zhinx' in "riscv_multi_subset_supports_ext". bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): New extensions. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: New test. * testsuite/gas/riscv/fp-zhinx-insns.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): New INSN classes. opcodes/ChangeLog: * riscv-opc.c: Modify INSN_CLASS.
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess203-1666/+1666
While working on another patch[1] I had need to touch this code in i386-dis.c: ins->obufp = ins->mnemonicendp; for (i = strlen (ins->obuf) + prefix_length; i < 6; i++) oappend (ins, " "); oappend (ins, " "); (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_mnemonic, "%s", ins->obuf); What this code does is add whitespace after the instruction mnemonic and before the instruction operands. The problem I ran into when working on this code can be seen by assembling this input file: .text nop retq Now, when I disassemble, here's the output. I've replaced trailing whitespace with '_' so that the issue is clearer: Disassembly of section .text: 0000000000000000 <.text>: 0: 90 nop 1: c3 retq___ Notice that there's no trailing whitespace after 'nop', but there are three spaces after 'retq'! What happens is that instruction mnemonics are emitted into a buffer instr_info::obuf, then instr_info::mnemonicendp is setup to point to the '\0' character at the end of the mnemonic. When we emit the whitespace, this is then added starting at the mnemonicendp position. Lets consider 'retq', first the buffer is setup like this: 'r' 'e' 't' 'q' '\0' Then we add whitespace characters at the '\0', converting the buffer to this: 'r' 'e' 't' 'q' ' ' ' ' ' ' '\0' However, 'nop' is actually an alias for 'xchg %rax,%rax', so, initially, the buffer is setup like this: 'x' 'c' 'h' 'g' '\0' Then in NOP_Fixup we spot that we have an instruction that is an alias for 'nop', and adjust the buffer to this: 'n' 'o' 'p' '\0' '\0' The second '\0' is left over from the original buffer contents. However, when we rewrite the buffer, we don't afjust mnemonicendp, which still points at the second '\0' character. Now, when we insert whitespace we get: 'n' 'o' 'p' '\0' ' ' ' ' ' ' ' ' '\0' Notice the whitespace is inserted after the first '\0', so, when we print the buffer, the whitespace is not printed. The fix for this is pretty easy, I can change NOP_Fixup to adjust mnemonicendp, but now a bunch of tests start failing, we now produce whitespace after the 'nop', which the tests don't expect. So, I could update the tests to expect the whitespace.... ...except I'm not a fan of trailing whitespace, so I'd really rather not. Turns out, I can pretty easily update the whitespace emitting code to spot instructions that have zero operands and just not emit any whitespace in this case. So this is what I've done. I've left in the fix for NOP_Fixup, I think updating mnemonicendp is probably a good thing, though this is not really required any more. I've then updated all the tests that I saw failing to adjust the expected patterns to account for the change in whitespace. [1] https://sourceware.org/pipermail/binutils/2022-April/120610.html
2022-05-27Replace bfd_hostptr_t with uintptr_tAlan Modra2-6/+6
bfd_hostptr_t is defined as a type large enough to hold either a long or a pointer. It mostly appears in the coff backend code in casts. include/coff/internal.h struct internal_syment and union internal_auxent have the only uses in data structures, where comparison with include/coff/external.h and other code reveals that the type only needs to be large enough for a 32-bit integer or a pointer. That should mean replacing with uintptr_t is OK.
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra8-70/+55
Requiring C99 means that uses of bfd_uint64_t can be replaced with uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_* and tidies a few places that print 64-bit values.
2022-05-27x86/Intel: allow MASM representation of embedded rounding / SAEJan Beulich12-1960/+2015
MASM doesn't support the separate operand form; the modifier belongs after the instruction instead. Accept this form alongside the original (now legacy) one. Short of having access to a MASM version to actually check in how far "after the instruction" is a precise statement in their documentation, allow both that and the SDM mandated form where the modifier is on the last register operand (with a possible immediate operand following). Sadly the split out function, at least for the time being, needs to cast away constness at some point, as the two callers disagree in this regard. Adjust some, but not all of the testcases.
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich4-72/+119
As a preparatory step to allowing proper non-operand forms of specifying embedded rounding / SAE, convert the internal representation to non- operand form. While retaining properties (and in a few cases perhaps providing more meaningful diagnostics), this means doing away with a few hundred standalone templates, thus - as a nice side effect - reducing memory consumption / cache occupancy.
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich36-9924/+9924
MASM doesn't consider {sae} and alike a separate operand; it is attached to the last register operand instead, just like spelled out by the SDM. Make the disassembler follow this first, before also adjusting the assembler (such that it'll be easy to see that the assembler change doesn't alter generated code).
2022-05-27x86/Intel: allow MASM representation of embedded broadcastJan Beulich24-4140/+4262
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Accept these forms alongside the original (now legacy) ones. Acceptance of the original {1to<n>} operand suffix is retained both for backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes. I have no insight (yet) into how MASM expects those to be disambiguated. Adjust some, but not all of the testcases.
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich50-16765/+16765
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Make the disassembler follow this first, before also adjusting the assembler (such that it'll be easy to see that the assembler change doesn't alter generated code). For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes the original {1to<n>} operand suffix is retained, to disambiguate output. I have no insight (yet) into how MASM expects those to be disambiguated.
2022-05-26 arm: avoid use of GNU builtin function in s_arm_unwind_save_mixedRichard Earnshaw1-40/+17
Whilst reviewing Luis' proposed change to s_arm_unwind_save_mixed yesterday I noticed that we were making use of __builting_clzl directly within the main function, which is not guaranteed to be portable. Whilst studying the code further, I also realized that it could be rewritten without using it and also reworked to remove a lot of unnecessary iterations steps. So this patch does that (and also removes the source of the warning that Luis was trying to fix). Finally, with the rewrite we can also simplify the caller of this routine as the new version can handle all the cases directly. * config/tc-arm.c (s_arm_unwind_save_mixed): Rewrite without using __builtin_clzl. (s_arm_unwind_save): Simplify logic for simple/mixed register saves.
2022-05-25RISC-V: Fix RV32Q conflictTsukasa OI7-3/+19
This commit makes RV32 + 'Q' extension (version 2.2 or later) not conflicting since this combination is no longer prohibited by the specification. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict detection that prohibits RV32Q on 'Q' version 2.2 or later. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32iq.d: Removed. * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test showing RV32IQ fails on 'Q' extension version 2.0. * testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test showing RV32IQ fails on ISA specification version 2.2. * testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test showing RV32IQ succesds on 'Q' extension version 2.2. * testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test showing RV32IQ succesds on ISA specification 20190608.
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin4-4/+4
Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB field present in binutils sources. Also, per 1.6.2, BC has the same semantics as BA and BB fields, so this should keep the same flags and mask, only with the different offset. opcodes/ * ppc-opc.c (BC): Define new field, with the same definition as CRB field, but with the PPC_OPERAND_CR_BIT flag present. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/a2.d: Update. * testsuite/gas/ppc/e500.d: Update. * testsuite/gas/ppc/power7.d: Update.
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin2-13/+17
With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org include/ * opcode/ppc.h (ppc_opindex_t): New typedef. (struct powerpc_opcode): Use it. (PPC_OPINDEX_MAX): Define. gas/ * write.h (struct fix): Increase size of fx_pcrel_adjust. Reorganise. * config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands. (md_assemble): Likewise. (md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX. (ppc_setup_opcodes): Adjust opcode index assertion. opcodes/ * ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for operand pointer. (lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise. (print_insn_powerpc): Likewise.
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-0/+36
Update zfinx implement with zicsr, fix missing fcsr use by zfinx. add zicsr imply by zfinx. bfd/ChangeLog: * elfxx-riscv.c: New imply. gas/ChangeLog: * testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test. opcodes/ChangeLog: * riscv-opc.c: Update insn class.
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI3-0/+8
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only), it should be removed until RV128 support for GNU Binutils is required again. gas/ChangeLog: * testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test. * testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise. * testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q, MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
2022-05-19arm: Fix system register fpcxt_ns and fpcxt_s naming convention.Srinath Parvathaneni3-3/+88
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M Mainline Instructions VSTR, VLDR, VMRS and VMSR. Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s and fpcxts. This patch fixes the issue.
2022-05-19Arm64: force emission of ILP32-dependent relocsJan Beulich1-1/+1
Like the placeholder types added in 04dfe7aa5217 ("Arm64: follow-on to PR gas/27217 fix"), these are also placeholders which are subsequently resolved (albeit later, hence this being a separate issue). As for the resolved types 1 is returned, these pseudo-relocs should also have 1 returned to force retaining of the [eventual] relocations. This is also spelled out individually for each of them in md_apply_fix().
2022-05-18Arm64: follow-on to PR gas/27217 fixJan Beulich1-2/+7
PR gas/27217 Prior to trying to address PR gas/28888 I noticed anomalies in how certain insns would / wouldn't be affected in similar ways. Commit eac4eb8ecb26 ("Fix a problem assembling AArch64 sources when a relocation is generated against a symbol that has a defined value") had two copy-and-paste mistakes, passing the wrong type to aarch64_force_reloc(). It further failed to add placeholder relocation types to that function's block of case labels leading to a return of 1. While not of interest for aarch64_force_relocation() (these placeholders are resolved right in parse_operands()), calls to aarch64_force_reloc() happen before that resolution would take place.
2022-05-18oops - forgot changelog entry for the previous delta.Victor Do Nascimento1-0/+16
2022-05-18arm: Add unwind support for mixed register listsVictor Do Nascimento4-42/+107
* config/tc-arm.c (parse_reg_list): Add handling of mixed register types. (reg_names): Enumerate pseudoregister according to mapped physical register number. (s_arm_unwind_save_pseudo): Modify function signature. (s_arm_unwind_save_core): Likewise. (s_arm_unwind_save_mixed): New function. (s_arm_unwind_save): Generate register list mask to pass to nested functions. * testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed register type lists. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
2022-05-18gas: avoid octal numbers being accepted when processing .linefileJan Beulich3-0/+12
Compilers would put decimal numbers there, so I think we should treat finding octal numbers the same as finding bignums - ignore them as actually being comments of some very specific form.
2022-05-18gas: avoid bignum related errors when processing .linefileJan Beulich4-4/+27
Any construct which to the scrubber looks like a C preprocessor line/file "directive" is converted to .linefile, but the amount of checking the scrubber does is minimal (albeit it does let through only decimal digits for the line part of the contruct). Since the scrubber conversion is further tied to # being a line comment character, anything which upon closer inspection turns out not to be a line/file "directive" is supposed to be treated as a comment, i.e. ignored. Therefore we cannot use get_absolute_expression(), as this may raise errors. Open- code the function instead, treating everything not resulting in O_constant as a comment as well. Furthermore also bounds-check the parsed value. This bounds check tries to avoid implementation defined behavior (which may be the raising of an implementation defined signal), but for now makes the assumption that int has less than 64 bits. The way bfd_signed_vma (which is what offsetT aliases) is defined in bfd.h for the BFD64 case I cannot really see a clean way of avoiding this assumption. Omitting the #ifdef, otoh, would risk "condition is always false" warnings by compilers. Convert get_linefile_number() to return bool at this occasion as well.
2022-05-18gas: fold do_repeat{,_with_expander}()Jan Beulich4-46/+15
do_repeat_with_expander() already deals with the "no expander" case quite fine, so there's really little point having two functions. What it lacks compared with do_repeat() is a call to sb_build(), which can simply be moved (and the then redundant sb_new() be avoided). Along with this moving also flip if the main if()'s condition such that the "no expander" case is handled first.
2022-05-18gas: don't ignore .linefile inside false conditionalsJan Beulich4-0/+26
When assembling code previously pre-processed by a C compiler, long enough comments may have been collapsed into "# <line> <file>" constructs. If we skip these, line numbers (and possibly even file names) will be off / wrong in both diagnostics and debug info.
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