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2017-07-05[ARM] Add support for Cortex-A55 and Cortex-A75.James Greenhalgh3-0/+13
This patch adds support for the ARM Cortex-A55 and Cortex-A75 processors. The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions, including support for the 16-bit floating point extensions. The 16-bit floating-point extensions are optional, and we haven't defined an option mapping straight to them thus far, so this patch first needs to add one of those in include/opcode/arm.h, then we can simply add the CPU names as usual in config/tc-arm.c . Tested on arm-none-eabi. 2017-07-05 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75. * doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov5-0/+37
The instructions are not documented in the Intel SDM but are documented in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant. Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as expected, i.e., like the /4 aliases: #include <stdio.h> int main(void) { int a = 2; printf ("a before: %d\n", a); asm volatile(".byte 0xd0,0xf0" /* SHL %al */ : "+a" (a)); printf("a after : %d\n", a); return 0; } $ ./a.out a before: 2 a after : 4
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+11
40c7d50720e04c3d1ef1695a8097f735bafbe54f
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan6-0/+28
This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). Tristan - are you ok with the backports ? Applied to trunk. regards Ramana 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
2017-07-04Regenerate configure.Tristan Gingold2-10/+14
bfd/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.29.51 * configure: Regenerate. binutils/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2017-07-04Add markers.Tristan Gingold2-0/+6
binutils/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29. gas/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29. ld/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29.
2017-07-03Disable symver test on hppa64-hpuxAlan Modra2-0/+5
The syntax for common symbols is different on that target. * testsuite/gas/elf/symver.d: Don't run on hppa64-hpux.
2017-07-01MIPS/GAS: Use a switch on relaxation type in microMIPS fixup creationMaciej W. Rozycki2-10/+20
Use a switch on the relaxation type rather than a chain of conditionals in microMIPS fixup creation, improving source code structure and aiding the compiler with code generation. gas/ * config/tc-mips.c (md_convert_frag): Use a switch on the microMIPS relaxation type rather than a chain of conditionals.
2017-07-01MIPS/GAS: Use frag symbol/offset directly in fixup creationMaciej W. Rozycki2-44/+38
There is no need to use a helper expression in the creation of fixups made from a frag's symbol and offset, because a simple `symbol+offset' expression can be handled directly, with the use of a `fix_new' rather than a `fix_new_exp' call. Rewrite `md_convert_frag' using `fix_new' then and remove all the unneeded helper expressions, simplifying code. gas/ * config/tc-mips.c (md_convert_frag): Rewrite `fix_new_exp' calls in terms of `fix_new'.
2017-07-01MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxationMaciej W. Rozycki10-12/+137
Use frag symbols with a non-zero offset directly in `fix_new_exp' calls made in PIC branch relaxation. There is no need here to make a helper symbol to hold the result of a `symbol+offset' calculation requested as only branches to local symbols are relaxed and in this case the LO16 part of the PIC address load sequence will have the offset accounted for in calculation against the local GOT entry retrieved as the GOT16 high part. Consequently actual code produed is identical whether a helper symbol is used or the original `symbol+offset' expression used directly. Verify that this is indeed the case with GAS and LD tests. gas/ * config/tc-mips.c (md_convert_frag): Don't make a helper expression symbol for `fix_new_exp' called with a non-zero offset. * testsuite/gas/mips/relax-offset.d: New test. * testsuite/gas/mips/mips1@relax-offset.d: New test. * testsuite/gas/mips/r3000@relax-offset.d: New test. * testsuite/gas/mips/r3900@relax-offset.d: New test. * testsuite/gas/mips/micromips@relax-offset.d: New test. * testsuite/gas/mips/relax-offset.l: New stderr output. * testsuite/gas/mips/relax-offset.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/relax-offset.dd: New test. * testsuite/ld-mips-elf/relax-offset.gd: New test. * testsuite/ld-mips-elf/relax-offset-umips.dd: New test. * testsuite/ld-mips-elf/relax-offset-umips.gd: New test. * testsuite/ld-mips-elf/relax-offset.ld: New test linker script. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. (prune_warnings): New temporary procedure.
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay10-7/+1050
PR gas/21683 include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr. gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it. (AVR Pseudo Instructions): New node. * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook. (md_undefined_symbol): Define to avr_undefined_symbol. (avr_pre_output_hook, avr_undefined_symbol): New protos. * config/tc-avr.c (struc-symbol.h): Include it. (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums. (avr_isr, avr_gccisr_opcode) (avr_no_sreg_hash, avr_no_sreg): New static variables. (avr_opt_s) <have_gccisr>: Add field. (avr_opt): Add initializer for have_gccisr. (enum options) <OPTION_HAVE_GCCISR>: Add enum. (md_longopts) <"mgcc-isr">: Add entry. (md_show_usage): Document -mgcc-isr. (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it. (md_undefined_symbol): Remove. (avr_undefined_symbol, avr_pre_output_hook): New fuctions. (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them. (avr_operand) <pregno>: Add argument and set *pregno if function is called for a register constraint. [N]: Handle constraint. (avr_operands) <avr_operand>: Pass 5th parameter to calls. [avr_opt.have_gccisr]: Call avr_update_gccisr. Call avr_gccisr_operands instead of avr_operands. (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag) (avr_gccisr_operands, avr_check_gccisr_done): New static functions. * testsuite/gas/avr/gccisr-01.d: New test. * testsuite/gas/avr/gccisr-01.s: New test. * testsuite/gas/avr/gccisr-02.d: New test. * testsuite/gas/avr/gccisr-02.s: New test. * testsuite/gas/avr/gccisr-03.d: New test. * testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30MIPS/GAS: Update `match_float_constant' and `match_operand' descriptionsMaciej W. Rozycki2-5/+10
Complement commit a92713e60ef4 ("Preparse MIPS instructions into tokens"), <https://sourceware.org/ml/binutils/2013-07/msg00143.html>, and update `match_float_constant' and `match_operand' function descriptions according to semantics changes. gas/ * config/tc-mips.c (match_float_constant): Update description. (match_operand): Likewise.
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki4-5/+37
Add support for the base and Virtualization ASE microMIPS instructions as per the architecture specifications[1][2][3][4]. Most of this change by Andrew Bennett. [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", p. 340 [2] "microMIPS32 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00848, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 133, 136 [3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 415, 444 [4] "microMIPS64 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00849, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140 binutils/ * NEWS: Mention microMIPS XPA support. opcodes/ * micromips-opc.c (XPA, XPAVZ): New macros. (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_ases): Add microMIPS XPA support. * testsuite/gas/mips/micromips@xpa.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. Enable `xpa-virt-err' test for `micromips'.
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki3-1/+16
Add base microMIPS Release 5 ISA support and the ERETNC instruction in particular, as per the architecture specifications[1][2]. Most of this change by Andrew Bennett. References: [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 266-267 [2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 326-327 binutils/ * NEWS: Mention microMIPS Release 5 ISA support. opcodes/ * micromips-opc.c (I36): New macro. (micromips_opcodes): Add "eretnc". gas/ * testsuite/gas/mips/micromips@r5.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki10-3/+62
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki3-42/+20
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") disassembler bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, where the calculation uses MIPS ABI Flags directly rather than calculated internal ASE flags. Consequently code does not correctly set the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag come from different sources, i.e. one from the BFD chosen and the other one from MIPS ABI Flags. Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate subsequent step, factored out to a dedicated function for use with future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d' test case accordingly, where the MT flag comes from the BFD selected for the disassembler and the MIPS16e2 flag comes from the ELF binary itself. opcodes/ * mips-dis.c (mips_calculate_combination_ases): New function. (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT calculation to the new function. (set_default_mips_dis_options): Call the new function. gas/ * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the ASE_MIPS16E2_MT flag disassembler fix. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: Likewise.
2017-06-30MIPS/GAS: Clear the ASE_MIPS16E2_MT flag for recalculationMaciej W. Rozycki6-0/+35
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which is not correctly calculated as `.set nomips16e2' and `.set nomt' pseudo-ops are processed. This leads to code like: $ cat foo.s .set nomt evpe .align 4, 0 $ cat bar.s .set nomips16e2 dvpe .align 4, 0 $ to successfully assemble where it should not: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s $ objdump -m mips:16 -d foo.o foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f027 6700 evpe ... bar.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f026 6700 dvpe ... $ This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never cleared. Fix the problem by clearing it there before it is calculated based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as expected: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s foo.s: Assembler messages: foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe' $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s bar.s: Assembler messages: bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe' $ gas/ * config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT flag before recalculating. * testsuite/gas/mips/mips16e2-mt-err.d: New test. * testsuite/gas/mips/mips16e2-mt-err.l: New stderr output. * testsuite/gas/mips/mips16e2-mt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina5-3/+1105
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod.
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang11-1/+787
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-28MIPS: Add new Imagination interAptiv MR2 GAS and LD testsMaciej W. Rozycki33-9/+615
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly, disassembly and ELF object file flags. Add LD tests to verify Imagination interAptiv MR2 ELF object file link-time compatibility and flag merging/propagation. Use the framework enhancement added with commit 7575e6a752ec ("MIPS/LD/testsuite: mips-elf-flags: Add MIPS ABI Flags handling"). gas/ * testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test. * testsuite/gas/mips/save-err.d: New test. * testsuite/gas/mips/save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save.d: New test. * testsuite/gas/mips/mips1@save-sub.d: New test. * testsuite/gas/mips/mips2@save-sub.d: New test. * testsuite/gas/mips/mips3@save-sub.d: New test. * testsuite/gas/mips/mips4@save-sub.d: New test. * testsuite/gas/mips/mips5@save-sub.d: New test. * testsuite/gas/mips/mips32@save-sub.d: New test. * testsuite/gas/mips/mips64@save-sub.d: New test. * testsuite/gas/mips/mips16@save-sub.d: New test. * testsuite/gas/mips/mips16e@save-sub.d: New test. * testsuite/gas/mips/r3000@save-sub.d: New test. * testsuite/gas/mips/r3900@save-sub.d: New test. * testsuite/gas/mips/r4000@save-sub.d: New test. * testsuite/gas/mips/vr5400@save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test. * testsuite/gas/mips/sb1@save-sub.d: New test. * testsuite/gas/mips/octeon2@save-sub.d: New test. * testsuite/gas/mips/octeon3@save-sub.d: New test. * testsuite/gas/mips/xlr@save-sub.d: New test. * testsuite/gas/mips/r5900@save-sub.d: New test. * testsuite/gas/mips/mips16e2-copy.d: New test. * testsuite/gas/mips/mips16e2-copy-err.d: New test. * testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name' option. Adjust for trailing padding change. * testsuite/gas/mips/mips16e2-copy-err.l: New stderr output. * testsuite/gas/mips/save-sub.s: New test source. * testsuite/gas/mips/mips16e2-copy.s: New test source. * testsuite/gas/mips/mips16e2-copy-err.s: New test source. * testsuite/gas/mips/save.s: Update description, change trailing padding and remove trailing white space. * testsuite/gas/mips/mips.exp: Expand `save' and `save-err' tests across the regular MIPS interAptiv MR2 architecture. Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2 tests.
2017-06-28MIPS: Add Imagination interAptiv MR2 GAS test infrastructureMaciej W. Rozycki32-6/+592
Define a new regular MIPS and MIPS16 interAptiv MR2 test architecture and adjust existing tests now run against these architectures accordingly. This change causes new test failures: FAIL: MIPS jal-svr4pic (interaptiv-mr2) FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2) with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are consistent with the remaining architecture results for these cases, that do not take into account the lack of R_MIPS_JALR relocations produced by GAS for these targets. As a preexisting issue these failures are not addressed with this change. gas/ * testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture. (mips16e2-interaptiv-mr2): Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d: New test. * testsuite/gas/mips/interaptiv-mr2@mcu.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test. * testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE flag lines present rather than just one. * testsuite/gas/mips/attr-gnu-4-6.d: Likewise. * testsuite/gas/mips/attr-gnu-4-7.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise. * testsuite/gas/mips/attr-none-o32-fp64.d: Likewise. * testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New stderr output. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr output. * testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr output.
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki3-15/+76
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-27MIPS/GAS/testsuite: Drop the `mips16e-' prefix from SAVE/RESTORE testsMaciej W. Rozycki7-4/+21
In preparation to running these tests against regular MIPS instructions. gas/ * testsuite/gas/mips/mips16e-save.d: Rename to... * testsuite/gas/mips/save.d: ... this. * testsuite/gas/mips/mips16e-save-err.d: Update the `error-output' option and rename to... * testsuite/gas/mips/save-err.d: ... this. * testsuite/gas/mips/mips16e-save-err.l: Rename to... * testsuite/gas/mips/save-err.l: ... this. * testsuite/gas/mips/mips16e-save.s: Rename to... * testsuite/gas/mips/save.s: ... this. * testsuite/gas/mips/mips16e-save-err.s: Rename to... * testsuite/gas/mips/save-err.s: ... this. * testsuite/gas/mips/mips.exp: Rename `mips16e-save' and `mips16e-save-err' invocations to `save' and `save-err' respectively and reorder these tests away from MIPS16 tests.
2017-06-27MIPS/GAS/testsuite: Run SAVE/RESTORE tests across all MIPS16e architecturesMaciej W. Rozycki6-7/+20
gas/ * testsuite/gas/mips/mips16e-save.d: Remove `-mmips:isa32 -mmips:16' from `objdump' flags and `-march=mips32 -mips16' from `as' flags. * testsuite/gas/mips/mips16e-save-err.d: Remove `-march=mips32' from `as' flags. * testsuite/gas/mips/mips16e-save.s: Remove the `.set mips16' pseudo-op. * testsuite/gas/mips/mips16e-save-err.s: Likewise. * testsuite/gas/mips/mips.exp: Run SAVE/RESTORE tests across all MIPS16e architectures.
2017-06-27MIPS/GAS/testsuite: Convert `mips16e-save-err' list test to a dump testMaciej W. Rozycki3-1/+10
gas/ * testsuite/gas/mips/mips16e-save-err.d: New test. * gas/testsuite/gas/mips/mips.exp: Fold `mips16e-save-err' list test into the new test.
2017-06-27MIPS/GAS/testsuite: Capitalize the name of the `mips16e-save' testMaciej W. Rozycki2-1/+6
For consistency with the subsequent changes in this area. gas/ * testsuite/gas/mips/mips16e-save.d: Capitalize the `name' option.
2017-06-26RISC-V: Use pc-relative relocation for FDE initial locationKuan-Lin Chen2-1/+24
The symbol address in .eh_frame may be adjusted in _bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert a relocation whose addend symbol is in .eh_frame. Othrewise, the value may be adjusted twice. bfd/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elfnn-riscv.c (perform_relocation): Support the new R_RISCV_32_PCREL relocation. (riscv_elf_relocate_section): Likewise. * elfxx-riscv.c (howto_table): Likewise. (riscv_reloc_map): Likewise. * bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation. * libbfd.h: Regenerate. gas/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a R_RISCV_32_PCREL relocation. include/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elf/riscv.h (R_RISCV_32_PCREL): New.
2017-06-26Check unsupported .symver with common symbolH.J. Lu6-0/+35
The .symver directive on common symbol creates a new common symbol, which shouldn't be allowed, similar to alias on common symbol: $ cat y.S .comm bar,8,8 .set bar1,bar $ as -o y.o y.S y.S: Assembler messages: y.S:2: Error: `bar1' can't be equated to common symbol 'bar' $ PR gas/21661 * config/obj-elf.c (obj_elf_symver): Don't allow .symver with common symbol. (elf_frob_symbol): Likewise. * testsuite/gas/elf/elf.exp: Run pr21661. * testsuite/gas/elf/pr21661.d: New file. * testsuite/gas/elf/pr21661.s: Likewise.
2017-06-26Fix compile time warning building gas for arm-wince target.Nick Clifton2-0/+6
* config/tc-arm.c (fpu_any): Only define for ELF based targets.
2017-06-26Update check conditions for illegal placed instructions.claziss5-2/+50
ARC cpus do not accept any jump or instructions with long immediate into the delay slots. gas/ 2017-06-07 Claudiu Zissulescu <claziss@synopsys.com> * /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known instructions to be accounted as jumps. (assemble_insn): Check for limms into the delay slots. Emit an error if so. * testsuite/gas/arc/asm-errors-3.d: New file. * testsuite/gas/arc/asm-errors-3.err: Likewise. * testsuite/gas/arc/asm-errors-3.s: Likewise.
2017-06-24[ARM] Add support for ARM Cortex-R52 processorThomas Preud'homme4-1/+12
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARM Cortex-R52 processor. === Patch description === This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC extensions. 2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * NEWS: Mention support of ARM Cortex-R52 processor. * config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor. * doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme41-132/+714
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro.
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme2-26/+24
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to remove special casing for ARMv6S-M autodetection. === Motivation === Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor architectures with extra checks in the handler function (do_t_swi) to give an error message when ARMv6-M is targeted and some more special casing in aeabi_set_public_attributes. This was made to exclude these mnemonics for ARMv6-M unless the OS extension is in use. However this logic is superfluous: there is already code to check whether an instruction is available based on the feature bit it is part of and whether the targeted architecture has that feature bit. This patch aims at removing that unneeded complexity. === Patch description === The OS extension is already limited to the ARMv6-M architecture so all this patch does is redefined availability of the ARM_EXT_OS feature bit to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any change either because it already includes ARM_EXT_OS. The patch also make sure that the error message that was given by do_t_swi when SWI/SVC is unavailable is still the same by detecting the situation in md_assemble. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v6m): Delete. (arm_ext_v7m): Delete. (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M profile. (arm_arch_v6m_only): Delete. (do_t_swi): Remove special case for ARMv6S-M. (md_assemble): Display error message previously in do_t_swi when SVC is not available. (insns): Guard swi and svc by arm_ext_os for Thumb mode. (aeabi_set_public_attributes): Remove special case for ARMv6S-M. include/ * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set. (ARM_AEXT_V4T): Likewise. (ARM_AEXT_V5TxM): Likewise. (ARM_AEXT_V5T): Likewise. (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-23RISC-V: Error, don't warn, for shfit amounts/CSRsAndrew Waterman2-8/+13
gas/ChangeLog 2017-05-11 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (riscv_ip): Changes as_warn to as_bad for improper shift amounts.
2017-06-22Fix compile time warning about unused static variable.Nick Clifton2-1/+5
* config/tc-arm.c (arm_ext_v7m): Add ATTRIBUTE_UNUSED.
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme8-69/+231
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to rework the Tag_CPU_arch build attribute value selection to (i) match architecture or CPU if specified by user without any need for hack and (ii) match an architecture with all the features used if in autodetection mode or return an error. === Motivation === Currently, Tag_CPU_arch build attribute value selection assumes that an architecture is always a superset of architectures released earlier. As such, the logic is to browse architectures in chronological order of release and selecting the Tag_CPU_arch value of the last one to contribute a feature used[1]/requested[2] not contributed by earlier architectures. [1] in case of autodetection mode [2] otherwise, ie. in case of -mcpu/-march or associated directives This logic fails the two objectives mentionned in the Context section. First, due to the assumption it does an architecture can be selected while not having all the features used/requested which fails the second objective. Second, not doing an exact match when an architecture or CPU is selected by the user means the wrong value is chosen when a later architecture provides a subset of the feature bits of an earlier architecture. This is the case for the implementation of ARMv8-R (see later patch). An added benefit of this patch is that it is possible to easily generate more consistent build attribute by setting the feature bits from the architecture matched in aeabi_set_public_attributes in autodetection mode. This is better done as a separate patch because lots of testcase' expected results must then be updated accordingly. === Patch description === The patch changes the main logic for Tag_CPU_arch and Tag_CPU_arch_profile values selection to: - look for an exact match in case an architecture or CPU was specified on the command line or in a directive - select the first released architecture that provides a superset of the feature used in the autodetection case - select the most featureful architecture in case of -march=all The array cpu_arch_ver is updated to include all architectures in order to make the first point work. Note that when looking for an exact match, the architecture with selected extension is tried first and then only the architecture. This is because some architectures are exactly equivalent to an earlier architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS extension) and ARMv6KZ (ARMv6K + security extension) are two such examples. Other adjustments are also necessary in aeabi_set_public_attributes to make this change work. 1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the absence of feature bit used/requested to decide whether to give the default value for empty files (see EABI attribute defaults test). It was previously checking that arch == 0 which would only happen if no feature bit could be matched by any architecture, ie there is no feature bit to match. 2) A fallback to a superset match must exist when no_cpu_selected () returns true. This is because aeabi_set_public_attributes is called again after relaxation and at this point selected_cpu is set from the previous execution of that function. There is therefore no way to check whether the user specified an architecture or CPU. 3) Tag_CPU_arch lines are removed from expected output when the detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch value for pre-ARMv4 architectures and default value for an absent entry is 0. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (fpu_any): Defined from FPU_ANY. (cpu_arch_ver): Add all architectures and sort by release date. (have_ext_for_needed_feat_p): New. (get_aeabi_cpu_arch_from_fset): New. (aeabi_set_public_attributes): Call above function to determine Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use and Tag_THUMB_ISA_use selection logic to check absence of feature bit accordingly. * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build attribute value. * testsuite/gas/arm/attr-march-armv2.d: Likewise. * testsuite/gas/arm/attr-march-armv2a.d: Likewise. * testsuite/gas/arm/attr-march-armv2s.d: Likewise. * testsuite/gas/arm/attr-march-armv3.d: Likewise. * testsuite/gas/arm/attr-march-armv3m.d: Likewise. * testsuite/gas/arm/pr12198-2.d: Likewise. include/ * opcode/arm.h (FPU_ANY): New macro.
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu7-30/+39
Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu7-12/+21
Replace savessp with saveprevssp for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace savessp with saveprevssp. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu12-81/+221
Update NOTRACK prefix handling to support memory indirect branch for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (md_assemble): Update NOTRACK prefix check. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with memory indirect branch. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove memory indirect branch with NOTRACK prefix. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. opcodes/ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" and "jmp{&|}". (NOTRACK_Fixup): Support memory indirect branch with NOTRACK prefix.
2017-06-21[ARM] Allow Thumb division as an extension for ARMv7Thomas Preud'homme4-0/+33
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to allow ARMv7 to be selected in automatic architecture selection in presence of Thumb division instructions. === Motivation === any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect autodetection code to select ARMv7 in presence of Thumb integer division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do not contain these instructions and the idiv extension is only available for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic detection code proposed in the subsequent patch of the series ARMv7 is refused if a Thumb division instruction is present. === Patch description === This patch adds a new "idiv" extension after the existing one that is available to all ARMv7 targets. This new entry is ignored by all current code parsing arm_extensions such that it would be unavailable on the command-line and remain a purely internal hack, easily removed in favor of a better solution later. This is considered though by the subsequent patch reworking automatic detection of build attributes such that ARMv7 is allowed to match in present of Thumb division instructions. For good measure, comments are added in all instances of code browsing arm_extensions to mention the expected behavior in case of duplicate entries as well as a new testcase. 2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable Thumb division for ARMv7 architecture. (arm_parse_extension): Document expected behavior for duplicate entries. (s_arm_arch_extension): Likewise. * testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test. * testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for above test.
2017-06-21[ARM] Rework selection of feature bits to base build attributes onThomas Preud'homme2-16/+30
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to set the feature bits on which to decide what the build attributes should be according to the mode (autodetection, user specified architecture or CPU, or -march/-mcpu=all). === Motivation === Currently, the flags variable which is used to determine the build attribute is constructed from the instruction used (arm_arch_used and thumb_arch_used) as well as the user specified architecture or CPU (selected_cpu). This means when several .arch are specified the resulting feature bits can be such that no architecture provide them all and can thus result in incorrect Tag_CPU_arch. See for instance what having both .arch armv8-a and .arch armv8-m.base would result in. This is not caught by the testsuite because of further bugs in the Tag_CPU_arch build attribute value selection logic (see next patch in the series). === Patch description === As one would expect, this patch solves the problem by setting flags from feature bits used if in autodetection mode [1] and from selected_cpu otherwise. The logic to set arm_ext_v1, arm_ext_v4t and arm_ext_os feature bits is also moved to only run in autodetection mode since otherwise the architecture or CPU would have a consistent set of feature bits already. [1] No architecture or CPU was specified by the user 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Populate flags from feature bits used or selected_cpu depending on whether a CPU was selected by the user.
2017-06-21[ARM] Simplify Tag_DSP_extension selection logicThomas Preud'homme2-23/+11
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to simplify the logic to decide whether to set Tag_DSP_extension. === Motivation === To decide whether to set Tag_DSP_extension, the current code was checking whether the flags had DSP instruction but the architecture selected for Tag_CPU_arch did not have any. This was necessary because extension feature bit were not available separately. This is no longer necessary and can be simplified. === Patch description === The patch change the logic to set Tag_DSP_extension to check whether any DSP feature bit is set in the extension feature bit, as per the definition of that build attribute. The patch also removes all definitions of arm_arch which is now unneeded. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to decide whether to set Tag_DSP_extension build attribute value. Remove now useless arm_arch variable.
2017-06-21[ARM] Keep separation between extensions and architecture bits throughout ↵Thomas Preud'homme3-29/+101
execution === Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to keep the distinction between architecture feature bits and extension ones after parsing has occured. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. The previous patch in the patch series makes the distinction possible when parsing -mcpu and .cpu directives but the distinction gets lost after. Similarly feature bits contributed by extensions in -march or .arch_extensions directive are mixed together with architecture extensions. === Patch description === The patch adds new feature bit pointer for extension feature bits. Information from the parsing regarding extensions can then be kept separate in those. This requires adapting arm_parse_extension to deal with two feature bits, allowing the architecture bits to be marked as const. It also requires extra care when setting cpu_variant and selected_cpu because the extension bits are optional since there might not be any extension in use. Note that contrary to cpu feature bits, the extension feature bits are made read/write and are always dynamically allocated. This allows to unconditionally free them in arm_md_post_relax added for this occasion, thereby fixing a longstanding memory leak when arm_parse_extension was invoked (XNEW of ext_fset without corresponding XDELETE). Introduction of arm_md_post_relax is necessary to only free the extension feature bits after aeabi_set_attribute_string has been called for the last time. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (dyn_mcpu_ext_opt): New static variable. (dyn_march_ext_opt): Likewise. (md_begin): Copy extension feature bits alongside architecture ones. Merge extensions feature bits in selected_cpu and cpu_variant if there is some. (arm_parse_extension): Pass architecture and extension feature bits in separate parameters, with architecture bits being read only. Update **opt_p directly rather than *ext_set and initialize it if needed. (arm_parse_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Adapt to change in parameters of arm_parse_extension. (arm_parse_arch): Adapt to change in parameters of arm_parse_extension. (aeabi_set_attribute_string): Make function static. (arm_md_post_relax): New function. (s_arm_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Merge extension feature bits in cpu_variant if there is any. (s_arm_arch): Reset extension feature bit. Set selected_cpu from *mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for consistency with s_arm_cpu. (s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than selected_cpu, allocating it before hand if needed. Set selected_cpu from it and then cpu_variant. (s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant. * config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax. (aeabi_set_public_attributes): Delete external declaration. (arm_md_post_relax): Declare externally.
2017-06-21[ARM] Separate extensions from architectures in arm_cpusThomas Preud'homme2-162/+381
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to distinguish for a CPU the feature bits coming from its architecture from the feature bits coming from extension(s) available in this CPU. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. === Patch description === The patch creates a new field in the arm_cpus table to hold the feature set for the extensions available in each CPU. The existing architecture feature set is then updated to remove those feature bit. The patch also takes advantage of all the lines being changed to reindent the whole table. Note: This patch *adds* a memory leak due to mcpu_cpu_opt sometimes pointing to dynamically allocated feature bits which is never freeed. The subsequent patch in the series solves this issue as well as a preexisting identical issue in arm_parse_extension. The patches are kept separate for ease of review since they are both big enough already. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_cpu_option_table): New ext field. (ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical name field just after the name field. (arm_cpus): Move extension feature bit from value field to ext field, reorder parameter according to changes in ARM_CPU_OPT and reindent. (arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and ext field from the selected arm_cpus entry. (s_arm_cpu): Likewise.
2017-06-21Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 ↵James Greenhalgh3-0/+13
architecture. * config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75. * doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75.
2017-06-15i386-dis: Add 2 tests with invalid bnd registerH.J. Lu5-0/+41
PR binutils/21594 * testsuite/gas/i386/mpx.s: Add 2 tests with invalid bnd register. * testsuite/gas/i386/x86-64-mpx.s: Likewise. * testsuite/gas/i386/mpx.d: Updated. * testsuite/gas/i386/x86-64-mpx.d: Likewise.
2017-06-14xtensa: don't expect XCHAL_* macros to be constantMax Filippov3-12/+40
Get rid of the assumption that XCHAL_* macros are preprocessor constants: don't use them in preprocessor conditionals or in static variable initializers. 2017-06-14 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (elf_xtensa_be_plt_entry, elf_xtensa_le_plt_entry): Add dimension for the ABI to arrays, keep both windowed and call0 ABI PLT definitions. (elf_xtensa_create_plt_entry): Use selected ABI to choose upper elf_xtensa_*_plt_entry endex. (ELF_MAXPAGESIZE): Fix at minimal supported MMU page size. gas/ * config/tc-xtensa.c (density_supported, xtensa_fetch_width, absolute_literals_supported): Leave definitions uninitialized. (directive_state): Leave entries for directive_density and directive_absolute_literals initialized to false. (xg_init_global_config, xtensa_init): New functions. * config/tc-xtensa.h (TARGET_BYTES_BIG_ENDIAN): Define as 0. (HOST_SPECIAL_INIT): New definition. (xtensa_init): New declaration.
2017-06-08[ARC] Don't convert _DYNAMIC@ to _GLOBAL_OFFSET_TABLE_Vineet Gupta2-5/+1
Historically the arc abi demanded that a GOT[0] should be referencible as [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a GOTPC reference to _GLOBAL_OFFSET_TABLE_. This is no longer the case and uClibc and upcomming GNU libc don't expect this to happen. gas/ChangeLog: Vineet Gupta <vgupta@synopsys.com> Cupertino Miranda <cmiranda@synopsys.com> * config/tc-arc.c (md_undefined_symbol): Changed. * config/tc-arc.h (DYNAMIC_STRUCT_NAME): Removed.
2017-06-07Add support for AArch64 system register names IP0, IP1, FP and LR.Michael Collison4-2/+16
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0, IP1, FP, and LR as register aliases of register 16, 17, 29 and 30 respectively. * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic prohibiting register 'lr' which is now an alias. * testsuite/gas/aarch64/diagnostic.s: Remove instruction utilizing register 'lr' which is now an alias.
2017-06-06[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-AJiong Wang12-18/+328
For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through the "reject_bad_reg" macro and several scattered checks. This patch only rejects REG_SP in "reject_bad_reg" and several related places for legacy architectures before ARMv8-A. I have checked those affected instructions , all of them qualify such relaxations. Testcases adjusted accordingly. * ld-sp-warn.d was written without .arch and without -march options passed. By default it assumes all architectures, so I deleted the REG_SP warning on ldrsb as it's supported on ARMv8-A. There are actually quite a few seperate tests on other architectures, for example ld-sp-warn-v7.l etc., so there the test for ldrsb on legacy architectures are still covered. * sp-pc-validations-bad-t has been extended to armv8-a. * strex-bad-t.d restricted on armv7-a. * Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*. gas/ * config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A. (parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on ARMv8-A. (do_co_reg): Allow REG_SP for Rd on ARMv8-A. (do_t_add_sub): Likewise. (do_t_mov_cmp): Likewise. (do_t_tb): Likewise. * testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for ldrsb. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test. * testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a. * testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a". * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test. * testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test. * testsuite/gas/arm/sp-usage-thumb2-relax.s: New test. * testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
generated by cgit v1.1 at 2024-11-20 16:15:59 +0000