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2020-10-06Fix gas sh-link-zero test for hppa64-hpuxAlan Modra2-7/+11
* testsuite/gas/elf/sh-link-zero.s: Don't start directives in first column. Don't use numeric labels.
2020-10-05[PATCH][GAS][AArch64] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-2/+6
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-aarch64.c: Update Cortex-X1 feature flags.
2020-10-05[PATCH][GAS][arm] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-1/+1
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Update Cortex-X1 feature flags.
2020-10-05Add NetBSD AArch64 GAS support.Kamil Rytarowski2-0/+5
gas * configure.tgt (aarch64*-*-netbsd*): Add target.
2020-10-05Fix spelling mistakesSamanta Navarro3-2/+7
2020-10-05i386: Allow non-absolute segment values for lcall/ljmpT.K. Chia8-6/+67
Allow an unresolved or non-absolute symbol as the segment operand of an immediate far jump (`ljmp SEG, OFF') or far call (`lcall SEG, OFF'). gas/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * NEWS: Updated for i386 lcall and ljmp change. * config/tc-i386.c (output_interseg_jump): Allow non-absolute segment operand for immediate lcall and ljmp. * testsuite/gas/i386/jump.d, * testsuite/gas/i386/jump.s, * testsuite/gas/i386/jump16.d, * testsuite/gas/i386/jump16.e, * testsuite/gas/i386/jump16.s: Add tests for non-absolute segment operand for immediate ljmp. ld/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * testsuite/ld-i386/ljmp.s, * testsuite/ld-i386/ljmp1.d, * testsuite/ld-i386/ljmp1.s, * testsuite/ld-i386/ljmp2.d, * testsuite/ld-i386/ljmp2.s, * testsuite/ld-x86-64/ljmp1.d, * testsuite/ld-x86-64/ljmp2.d: New testcases. * testsuite/ld-i386/i386.exp, * testsuite/ld-x86-64/x86-64.exp: Run them.
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu5-4/+13
In 64bit, assembler generates a warning for "sysret": $ echo sysret | as --64 -o x.o - {standard input}: Assembler messages: {standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret' Always display suffix for %LQ in 64bit to display "sysretl". gas/ PR binutils/26704 * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of sysret. * testsuite/gas/i386/noreg64.d: Likewise. * testsuite/gas/i386/x86-64-intel64.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR binutils/26704 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
2020-10-05x86: Clear modrm if not neededH.J. Lu4-0/+14
The MODRM byte can be checked to display the instruction name only if the MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that modrm field checks in putop like, modrm.mod == N with N != 0, can be done without checking need_modrm. gas/ PR binutils/26705 * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before sysretq. * testsuite/gas/i386/x86-64-suffix-intel.d: Updated. * testsuite/gas/i386/x86-64-suffix.d: Likewise. opcodes/ PR binutils/26705 * i386-dis.c (print_insn): Clear modrm if not needed. (putop): Check need_modrm for modrm.mod != 3. Don't check need_modrm for modrm.mod == 3.
2020-10-05GAS: Update the .section directive so that a numeric section index can be ↵Nick Clifton9-33/+86
provided when the "o" flag is used. PR 26253 gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for the "o" section flag. Interpret it as a section index. Allow an index of zero. * doc/as.texi: Document the new behaviour. * NEWS: Mention the new feature. Tidy entries. * testsuite/gas/elf/sh-link-zero.s: New test. * testsuite/gas/elf/sh-link-zero.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/section21.l: Updated expected assembler output. bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an sh_link value of zero when the SLF_LINK_ORDER flag is set. (assign_section_numbers): Likewise.
2020-10-03x86: Update register operand check for AddrPrefixOpRegH.J. Lu19-60/+196
When the address size prefix applies to both the memory and the register operand, we need to extract the address size prefix from the register operand if the memory operand has no real registers, like symbol, DISP or symbol(%rip). NB: GCC always generates symbol(%rip) for RIP-relative addressing for both x32 and x86-64. Move the .code16 tests in movdir.s to movdir-16bit to show the correct output from objdump. PR gas/26685 * config/tc-i386.c (process_suffix): Also check the register operand for the address size prefix if the memory operand has no real registers. * testsuite/gas/i386/enqcmd-16bit.d: New file. * testsuite/gas/i386/enqcmd-16bit.s: Likewise. * testsuite/gas/i386/movdir-16bit.d: Likewise. * testsuite/gas/i386/movdir-16bit.s: Likewise. * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP. Remove the .code16 test. * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/enqcmd-intel.d: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/movdir-intel.d: Likewise. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise.
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus5-0/+22
bfd/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * cpu-arm.c: Add cortex-a78 and cortex-a78ae. gas/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. * doc/c-arm.texi: Update docs. * NEWS: Update news. * testsuite/gas/arm/cpu-cortex-a78.d: New test. * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
2020-10-02Fix the mve-vcvtne-it assembler test for the arm-*-pe targets.Nick Clifton2-1/+7
* testsuite/gas/arm/mve-vcvtne-it.d: Allow for padding inserted by PE based targets.
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton11-1/+108
* config/obj-elf (elf_pseudo_table): Add attach_to_group. (obj_elf_attach_to_group): New function. * doc/as.texi: Document the new directive. * NEWS: Mention the new feature. * testsuite/gas/elf/attach-1.s: New test. * testsuite/gas/elf/attach-1.d: New test driver. * testsuite/gas/elf/attach-2.s: New test. * testsuite/gas/elf/attach-2.d: New test driver. * testsuite/gas/elf/attach-err.s: New test. * testsuite/gas/elf/attach-err.d: New test driver. * testsuite/gas/elf/attach-err.err: New test error output. * testsuite/gas/elf/elf.exp: Run the new tests.
2020-09-30x86: Check register operand for AddrPrefixOpRegH.J. Lu8-34/+114
If the address prefix changes the register operand, we need to check the register operand when the memory operand is RIP-relative. PR gas/26685 * config/tc-i386.c (process_suffix): Check the register operand for the address size prefix if the memory operand is symbol(%rip). * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative addressing. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise.
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus4-0/+24
* config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. * doc/c-aarch64.texi: Update docs. * NEWS: Update news.
2020-09-30NEWS: Mention recent Arm CPU supportAlex Coplan2-0/+9
Mentions Armv8-R AArch64, Cortex-R82, Neoverse V1, and Neoverse N2. gas/ChangeLog: 2020-09-30 Alex Coplan <alex.coplan@arm.com> * NEWS: Mention recent Arm processor support.
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan3-0/+16
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. * doc/c-aarch64.texi: Document support for Neoverse N2.
2020-09-30gcc-4.4.7 warning fixesAlan Modra3-3/+10
* config/obj-elf.c (obj_elf_change_section): Rename variable to avoid shadowing warning. * symbols.c (symbol_entry_find): Init all symbol_flags fields.
2020-09-29Add a note about recent changes to the AArch64 assembler: TRBE, ETE and ↵Przemyslaw Wirkus2-0/+15
ETMv4 system registers and Cortex-X1 enablement. gas * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus4-0/+16
bfd * cpu-arm.c: (processors) Add Cortex-X1. gas * config/tc-arm.c: (arm_cpus): Add Cortex-X1. * doc/c-arm.texi: Document -mcpu=cortex-x1. * testsuite/gas/arm/cpu-cortex-x1.d: New test.
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for ↵Przemyslaw Wirkus14-9/+933
the AArch64 architecture. gas * testsuite/gas/aarch64/etm-ro-invalid.d: New test. * testsuite/gas/aarch64/etm-ro-invalid.l: New test. * testsuite/gas/aarch64/etm-ro-invalid.s: New test. * testsuite/gas/aarch64/etm-ro.s: New test. * testsuite/gas/aarch64/etm-wo-invalid.d: New test. * testsuite/gas/aarch64/etm-wo-invalid.l: New test. * testsuite/gas/aarch64/etm-wo-invalid.s: New test. * testsuite/gas/aarch64/etm-wo.s: New test. * testsuite/gas/aarch64/etm.s: New test. * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled now to trcstatr. opcodes * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus3-1/+10
gas * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1. * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for ↵Przemyslaw Wirkus3-0/+38
the AArch64 architecture. gas * testsuite/gas/aarch64/ete.d: New test. * testsuite/gas/aarch64/ete.s: New test. opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ↵Przemyslaw Wirkus6-0/+52
AArch64 architecture. gas * testsuite/gas/aarch64/trbe-invalid.d: New test. * testsuite/gas/aarch64/trbe-invalid.l: New test. * testsuite/gas/aarch64/trbe-invalid.s: New test. * testsuite/gas/aarch64/trbe.d: New test. * testsuite/gas/aarch64/trbe.s: New test. opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
2020-09-28arm: Add missing Neoverse V1 featureAlex Coplan2-1/+7
This simple follow-on patch adds a feature bit (FP16) that was missing from the initial Neoverse V1 support. gas/ChangeLog: * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
2020-09-28aarch64: Neoverse V1 tweaksAlex Coplan2-8/+14
This simple follow-on patch groups the Neoverse cores together and adds a missing feature bit (F16) to the entry for Neoverse V1. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together, add missing F16 bit to Neoverse V1.
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra2-48/+51
opcodes/ * csky-opc.h: Formatting. (GENERAL_REG_BANK): Correct spelling. Update use throughout file. (get_register_name): Mask arch with CSKY_ARCH_MASK for shift, and shift 1u. (get_register_number): Likewise. * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag. gas/ * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag for csky_get_control_regno. (csky_get_reg_val): Likewise when calling csky_get_general_regno.
2020-09-24RISC-V: Error for relaxable branch in absolute section.Jim Wilson5-0/+23
Emit an error instead of crashing in frag_new, handling this same as the i386 port. gas/ PR 26400 * config/tc-riscv.c (append_insn): If in absolute section, emit error before add_relaxed_insn call. * testsuite/gas/riscv/absolute-sec.d: New. * testsuite/gas/riscv/absolute-sec.l: New. * testsuite/gas/riscv/absolute-sec.s: New.
2020-09-24readelf: Show Unit Type for DWARF5Mark Wielaard2-0/+5
binutils/ChangeLog: * dwarf.c (process_debug_info): Print Unit Type for DWARF5. * testsuite/binutils-all/dw5.W: Adjust expected output. * testsuite/binutils-all/dwarf-attributes.W: Likewise. gas/ChangeLog: * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output.
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan3-0/+9
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse V1. * doc/c-arm.texi: Document Neoverse V1 support.
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan3-0/+14
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1. * doc/c-aarch64.texi: Document Neoverse V1 support.
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan3-0/+11
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the AArch32 assembler. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
2020-09-24Add support for Intel TDX instructions.Cui,Lili9-1/+62
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu7-416/+327
Add option parser for disassembler, and refine the codes of parse register operand and disassemble register operand. While strengthen the operands legality check of some instructions. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (parse_type_ctrlreg): Use function csky_get_control_regno to operand. (csky_get_reg_val): Likewise. (is_reg_sp_with_bracket): Use function csky_get_reg_val to parse operand. (is_reg_sp): Refine. (is_oimm_within_range): Fix, report error when operand is not constant. (parse_type_cpreg): Refine. (parse_type_cpcreg): Refine. (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS. (md_assemble): Fix no error reporting somtimes when operands number are not fit. (csky_addc64): Refine. (csky_subc64): Refine. (csky_or64): Refine. (v1_work_fpu_fo): Refine. (v1_work_fpu_read): Refine. (v1_work_fpu_writed): Refine. (v1_work_fpu_readd): Refine. (v2_work_addc): New function, strengthen the operands legality check of addc. * gas/testsuite/gas/csky/all.d : Use register number format when disassemble register name by default. * gas/testsuite/gas/csky/cskyv2_all.d : Likewise. * gas/testsuite/gas/csky/trust.d: Likewise. * gas/testsuite/gas/csky/cskyv2_ck860.d : Fix. * gas/testsuite/gas/csky/trust.s : Fix. opcodes/ * csky-dis.c (using_abi): New. (parse_csky_dis_options): New function. (get_gr_name): New function. (get_cr_name): New function. (csky_output_operand): Use get_gr_name and get_cr_name to disassemble and add handle of OPRND_TYPE_IMM5b_LS. (print_insn_csky): Parse disassembler options. * opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum. (GENARAL_REG_BANK): Define. (REG_SUPPORT_ALL): Define. (REG_SUPPORT_ALL): New. (ASH): Define. (REG_SUPPORT_A): Define. (REG_SUPPORT_B): Define. (REG_SUPPORT_C): Define. (REG_SUPPORT_D): Define. (REG_SUPPORT_E): Define. (csky_abiv1_general_regs): New. (csky_abiv1_control_regs): New. (csky_abiv2_general_regs): New. (csky_abiv2_control_regs): New. (get_register_name): New function. (get_register_number): New function. (csky_get_general_reg_name): New function. (csky_get_general_regno): New function. (csky_get_control_reg_name): New function. (csky_get_control_regno): New function. (csky_v2_opcodes): Prefer two oprerans format for bclri and bseti, strengthen the operands legality check of addc, zext and sext.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo14-1/+263
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-21PR26569, R_RISCV_RVC_JUMP results in buffer overflowAlan Modra2-3/+15
This patch corrects "size" and "bitsize" in R_RISCV_RVC_* reloc howtos so that elfnn-riscv.c:perform_relocation doesn't access past the end of a section. I've also corrected "size" in the R_RISCV_CALL* reloc howtos since these relocs apply to two consecutive instructions. That caused fallout in the assembler with complaints about "fixup not contained within frag" due to tc-riscv.c:append_insn finishing off a frag after the auipc insn making up a "call" macro. Which is a little rude since the CALL reloc also relocates the following jalr. Fixed by changing the frag handling a little. I've also changed R_RISCV_ALIGN and R_RISCV_TPREL_ADD marker reloc howtos to look like R_RISCV_NONE, and corrected dst_mask for numerous relocs, not that it matters very much. bfd/ PR 26569 * elfxx-riscv.c (howto_table): Correct size and bitsize of R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, and R_RISCV_RVC_LUI. Correct size for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPREL32, R_RISCV_CALL, and R_RISCV_CALL_PLT. Make R_RISCV_TPREL_ADD and R_RISCV_ALIGN like R_RISCV_NONE. Correct dst_mask many relocs. gas/ * config/tc-riscv.c (append_insn): Don't tie off frags at CALL relocs. (riscv_call): Tie them off after the jalr. (md_apply_fix): Zero fx_size of RELAX fixup.
2020-09-18bpf: xBPF SDIV, SMOD instructionsDavid Faust6-0/+67
Add gas and opcodes support for two xBPF-exclusive ALU operations: SDIV (signed division) and SMOD (signed modulo), and add tests for them in gas. cpu/ * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD. (define-alu-insn-bin, daib): Take ISAs as an argument. (define-alu-instructions): Update calls to daib pmacro with ISAs; add sdiv and smod. gas/ * testsuite/gas/bpf/alu-xbpf.d: New file. * testsuite/gas/bpf/alu-xbpf.s: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise.
2020-09-18Ensure that space allocated by assembler directives converts from an octet ↵Nick Clifton2-1/+7
count to a byte count. PR 26556 * read.c (bss_alloc): Convert size parameter from octets to bytes.
2020-09-17Tidy gas i386.expAlan Modra2-34/+38
Possibly a quirk of my version of tcl, but I see "nm-new --help" being run on non-x86 targets. * testsuite/gas/i386/i386.exp: Return early if not x86.
2020-09-16Tidy elf_symbol_fromAlan Modra6-11/+18
bfd/ * elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter. * elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data), (swap_out_syms): Adjust elf_symbol_from invocation. binutils/ * nm.c (print_symbol): Adjust elf_symbol_from invocation. * objcopy.c (is_hidden_symbol): Likewise. gas/ * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust elf_symbol_from invocation. * config/tc-aarch64.c (s_variant_pcs): Likewise. * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise. * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation), (ppc_fix_adjustable): Likewise. * config/tc-xgate.c (xgate_frob_symbol): Likewise. ld/ * plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from invocation. opcodes/ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
2020-09-15PE/x86-64: Display PE relocation namesH.J. Lu3-5/+10
For PE/x86-64, display PE relocation names: R_X86_64_64 -> IMAGE_REL_AMD64_ADDR64 R_X86_64_32 -> IMAGE_REL_AMD64_ADDR32. rva32 -> IMAGE_REL_AMD64_ADDR32NB R_X86_64_PC32 -> IMAGE_REL_AMD64_REL32 DISP32+1 -> IMAGE_REL_AMD64_REL32_1 DISP32+2 -> IMAGE_REL_AMD64_REL32_2 DISP32+3 -> IMAGE_REL_AMD64_REL32_3 DISP32+4 -> IMAGE_REL_AMD64_REL32_4 DISP32+5 -> IMAGE_REL_AMD64_REL32_5 secrel32 -> IMAGE_REL_AMD64_SECREL bfd/ * coff-x86_64.c (howto_table): Display PE relocation names. gas/ * testsuite/gas/cfi/reloc-pe-i386.d: Updated. * testsuite/gas/i386/x86-64-w64-pcrel.d: Likewise.
2020-09-15PR26610, ARM's "VFPv3 vldr to vmov" gas testcase failAlan Modra2-19/+28
I removed a few too many parentheses in git commit 7af677524e2. This patch fixes that problem, rewriting the expression so it won't happen again. The patch also avoids more UB with shifts of signed values. PR 26610 * config/tc-arm.c (move_or_literal_pool): Correct extraction of bignum. Use unsigned "v" (is_double_a_single): Make "v" and "mantissa" unsigned. Formatting. (double_to_single): Likewise.
2020-09-15Fix the assembler's new .nop directive so that the input line pointer is ↵Nick Clifton3-6/+14
preserved. * read.c (s_nop): Preserve the input_line_pointer around the call to md_assemble. * config/tc-s12z.c (md_assemble): Revert previous delta.
2020-09-15Change the /nop directive for the BPF port of the assembler to use the ↵David Faust2-1/+7
encoding expected by the kernel. * config/tc-bpf.h (md_single_noop_insn): Use 'ja 0' for no-op.
2020-09-14Fix support for theassembler's new ".nop" directive on the IA64 target.Nick Clifton2-0/+3
* config/tc-ia64.h (md_single_noop_insn): Define.
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op ↵Nick Clifton18-39/+165
instructions in an architeture neutral manner. * read.c (s_nop): New function. Handles the .nop directive. (potable): Add entry for "nop". (s_nops): Code tidy. * read.h (s_nop): Add prototype. * config/tc-bpf.h (md_single_noop_insn): Define. * config/tc-mmix.h (md_single_noop_insn): Define. * config/tc-or1k.h (md_single_noop_insn): Define. * config/tc-s12z.c (md_assemble): Preserve the input line pointer, rather than corrupting it. * write.c (relax_segment): Update error message regarding non-absolute values passed to .fill and .nops. * NEWS: Mention the new directive. * doc/as.texi: Document the new directive. * doc/internals.texi: Document the new internal macros used to implement the new directive. * testsuite/gas/all/nop.s: New test. * testsuite/gas/all/nop.d: New test control file. * testsuite/gas/all/gas.exp: Run the new test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test control file. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/space1.l: Adjust expected output.
2020-09-14CSKY: Set feature flags for default cpu.Cooper Qu1-3/+2
Fix floating point instructions not recognized when building GCC. gas/ PR 26608 * config/tc-csky.c (md_begin): Set feature flags for default cpu.
2020-09-11gas: Don't error when .debug_line already exists, unless .loc was usedMark Wielaard13-10/+369
When -g was used to generate DWARF gas would error out when a .debug_line already exists. But when a .debug_info section already exists it would simply skip generating one without warning or error. Do the same for .debug_line. It is only an error when the user explicitly uses .loc directives and also generates the .debug_line table itself. The tests are unfortunately arch specific because the line table is only generated when actual instructions have been emitted. Use i386 because that is probably the most used architecture. Before this patch the new dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't try to add its own line table). gas/ChangeLog: * as.texi (-g): Explicitly mention when .debug_info and .debug_line are generated for the DWARF format. (Loc): Add that it is an error to both use a .loc directive and generate a .debug_line yourself. * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable. (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE. (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting an error. Only create .debug_line if it is empty (or doesn't exist). * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing an elf target. * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
2020-09-10CSKY: Enable extend lrw by default for CK802, CK803 and CK860.Cooper Qu2-1/+9
gas/ * config/tc-csky.c (md_begin): Enable extend lrw by default for CK802, CK803 and CK860.
2020-09-10CSKY: Add L2Cache instructions for CK860.Cooper Qu1-1/+1
opcodes/ * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions. * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva opcode fixing.
generated by cgit v1.1 at 2024-11-19 23:16:24 +0000