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AgeCommit message (Expand)AuthorFilesLines
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki5-0/+71
2016-12-23MIPS16/GAS: Clean up invalid unextended operand handlingMaciej W. Rozycki7-0/+222
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki23-43/+1096
2016-12-23MIPS16/GAS: Fix forced size suffixes with argumentless instructionsMaciej W. Rozycki3-0/+27
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki3-0/+44
2016-12-21Remove high bit set charactersAlan Modra1-5/+5
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki14-0/+1664
2016-12-20MIPS/GAS/testsuite: Add RESTORE instruction to `mips16e' testMaciej W. Rozycki2-1/+3
2016-12-20MIPS/GAS/testsuite: Extend MIPS16 testing over multiple ISAsMaciej W. Rozycki23-167/+1948
2016-12-20MIPS/GAS/testsuite: Implement individual MIPS16 ISA testingMaciej W. Rozycki5-7/+163
2016-12-20MIPS/GAS/testsuite: Fix trailing padding in `loc-swap.s'Maciej W. Rozycki4-4/+3
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki12-0/+274
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-0/+13
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki4-0/+13
2016-12-20MIPS/GAS/testsuite: Correct NewABI test selectionMaciej W. Rozycki1-27/+79
2016-12-14MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructionsMaciej W. Rozycki6-0/+31
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki3-0/+45
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2-108/+110
2016-12-13[AArch64] Make GAS testcases support ILP32 modeJiong Wang109-210/+234
2016-12-09MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand codeMaciej W. Rozycki3-0/+40
2016-12-06Fix mmix assembler test to account for changes in the error messages produced...Nick Clifton1-2/+3
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy5-0/+188
2016-12-05[ARC] Don't check extAuxRegister second argument for sign.Claudiu Zissulescu4-0/+19
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy5-0/+40
2016-12-02[ARC] Sync cpu names with the ones accepted by GCC.Claudiu Zissulescu6-0/+27
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2-1/+10
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar3-0/+29
2016-11-27Fix spelling in comments in Expect scripts (gas)Ambrogino Modigliani7-11/+11
2016-11-27Fix spelling in comments in Assembler files (gas)Ambrogino Modigliani12-13/+13
2016-11-27Fix spelling in comments in C source files (gas)Ambrogino Modigliani2-6/+6
2016-11-25gas: fix CBCOND diagnostics for invalid immediate operands.Jose E. Marchesi3-0/+9
2016-11-23gas: run the hwcaps-bump tests with 64-bit sparc objects only.Jose E. Marchesi1-1/+1
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi3-0/+8
2016-11-22[ARC] Fix printing 'b' mnemonics.Claudiu Zissulescu1-2/+2
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-73/+73
2016-11-21[GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL s...Renlin Li2-0/+16
2016-11-18[ARC] Fix and extend features of .cpu directive.Claudiu Zissulescu6-0/+43
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy5-0/+113
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy5-0/+85
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy8-0/+50
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy5-0/+126
2016-11-11Accept L and LL suffixes to integer constants.Nick Clifton3-0/+18
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2-0/+35
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2-0/+5
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2-0/+68
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy4-0/+73
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy3-13/+88
2016-11-11[AArch64] Fix feature dependencies for +simd and +cryptoSzabolcs Nagy5-0/+37
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu7-72/+5
2016-11-09X86: Update opcode-suffix.dH.J. Lu1-0/+8
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