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2021-11-19RISC-V: Support new .option arch directive.Nelson Chu10-0/+80
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu4-0/+42
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton6-0/+30
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus5-0/+270
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus5-0/+61
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus5-0/+74
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus15-0/+694
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus5-0/+230
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus14-0/+357
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus9-0/+746
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu18-3/+3884
2021-11-16x86: Don't allow KMOV in TLS code sequencesH.J. Lu5-0/+16
2021-11-16RISC-V: Scalar crypto instruction and entropy source CSR testcases.jiawei41-3/+490
2021-11-15Deal with full path in .file 0 directiveEric Botcazou5-4/+130
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu3-5/+5
2021-11-10arm: enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+6
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot4-0/+30
2021-11-02ARM: match armeb output for unwind-pacbti-m testAlan Modra1-3/+3
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2-1/+18
2021-10-29Re: arm: add unwinder encoding support for PACBTIAlan Modra3-0/+59
2021-10-28ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPO...Markus Klein2-0/+9
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu3-12/+69
2021-10-24LoongArch gas supportliuzhensong24-1/+1973
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu4-0/+62
2021-10-14Re: s12z/disassembler: call memory_error_func when appropriateAlan Modra1-1/+2
2021-10-07RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich4-0/+26
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich4-2/+58
2021-09-30arm: enable Cortex-R52+ CPUPrzemyslaw Wirkus1-0/+6
2021-09-29Add a testcase for PR binutils/27202H.J. Lu3-0/+28
2021-09-28RISC-V: Allow to add numbers in the prefixed extension names.Nelson Chu8-9/+14
2021-09-28x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili4-5/+23
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner5-8/+21
2021-09-24gas/testsuite/ld-elf/dwarf2-21.d: Pass -WHans-Peter Nilsson1-1/+1
2021-09-22dwarf2 sub-section testAlan Modra3-0/+27
2021-09-18PR28149 part 2, purge generated line infoAlan Modra4-47/+11
2021-09-18PR28149, debug info with wrong file associationAlan Modra6-4/+14
2021-09-13RISC-V: Update the assembler insn testcase.Nelson Chu2-4/+0
2021-09-10Re: gas: Use the directory name in .file 0Alan Modra1-18/+18
2021-09-09gas: Use the directory name in .file 0H.J. Lu3-0/+127
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson4-17/+17
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton2-3/+8
2021-08-31RISC-V: Extend .insn directive to support hardcode encoding.Nelson Chu5-0/+29
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu17-1/+292
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-0/+1
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu3-0/+17
2021-08-18Re: as: Replace the removed symbol with the versioned symbolAlan Modra1-2/+2
2021-08-17x86: Always run fp testsH.J. Lu4-208/+1
2021-08-16x86: Don't pad .tfloat directive outputH.J. Lu2-0/+122
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