aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Collapse)AuthorFilesLines
2008-07-10include/elf/Richard Sandiford4-0/+17
* mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. bfd/ * elfxx-mips.c (mips_elf_check_mips16_stubs): Use ELF_ST_IS_MIPS16. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. opcodes/ * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. gas/ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16. (mips_fix_adjustable): Likewise. (mips_frob_file_after_relocs): Likewise. gas/testsuite/ * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests. * gas/mips/mips.exp: Run them.
2008-07-092008-07-09 Kai Tietz <kai.tietz@onevision.com>Kai Tietz3-4/+41
* gas/i386/i386.exp (x86-64-pcrel): Disable for w64. (x86-64-sse5): Likewise. (x86-64-opcode-inval): Likewise. (x86-64-opcode-inval-intel): Likewise. (x86-64-w64-pcrel): New. * gas/i386/x86-64-w64-pcrel.d: New.
2008-07-07 * gas/mips/mips32.s: Move out coprocessor2 insns from here ...Adam Nemet18-127/+286
* gas/mips/mips32-cp2.s: ... to here. * gas/mips/mips32.d: Update. * gas/mips/mips32-cp2.d: New file. * gas/mips/mips32r2.s: Move out coprocessor2 insns from here ... * gas/mips/mips32r2-cp2.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-cp2.d: New file. * gas/mips/mips64.s: Move out coprocessor2 insns from here ... * gas/mips/mips64-cp2.s: ... to here. * gas/mips/mips64.d: Update. * gas/mips/mips64-cp2.d: New file. * gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp except for Octeon. * gas/mips/octeon.s: Add supported coprocessor insns. Move pop down to keep alphabetical order. * gas/mips/octeon.d: Update. * gas/mips/octeon-ill.s: Add unsupported coprocessor insns. * gas/mips/octeon-ill.l: Update.
2008-07-07gas/Carlos O'Donell3-0/+34
2008-07-07 Paul Brook <paul@codesourcery.com> * config/tc-arm.c (arm_fix_adjustable): Don't adjust MOVW/MOVT relocations. gas/testsuite/ 2008-07-07 Paul Brook <paul@codesourcery.com> * gas/arm/movw-local.d: New test. * gas/arm/movw-local.s: New test.
2008-06-27* gas/mips/odd-float.d: Replace ... with #pass.Chao-ying Fu5-3/+11
* gas/mips/ldstla-32-shared.d: Add -march=mips1 for as. * gas/mips/ldstla-32.d: Likewise. * gas/mips/mips16-hilo-match.d: Add -mabi=32 -march=mips1 for as.
2008-06-20* gas/mips/e32-rel2.d: Add -march=mips1 for as.Chao-ying Fu2-1/+5
2008-06-16 PR gas/6607Hans-Peter Nilsson7-0/+49
* gas/mmix/err-loc-10.s, gas/mmix/err-loc-9.s, gas/mmix/loc-6.d, gas/mmix/loc-6.s, gas/mmix/loc-7.d, gas/mmix/loc-7.s: New tests.
2008-06-12 * mips.h: Document new field descriptors +Q.Nick Clifton5-0/+70
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.
2008-06-12include/opcode/Nick Clifton6-3/+161
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.
2008-06-03gas/H.J. Lu5-0/+65
2008-06-03 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_sse_check): New. (md_pseudo_table): Add "sse_check". gas/testsuite/ 2008-06-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run sse-check-none and x86-64-sse-check-none. * gas/i386/sse-check-none.d: New. * gas/i386/sse-check-none.s: Likewise. * gas/i386/x86-64-sse-check-none.d: Likewise.
2008-06-032008-06-03 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
gas/ * config/tc-arm.c (do_t_rbit): Populate both rm fields. gas/testsuite/ * gas/arm/thumb32.d: Update expected output.
2008-05-30gas/testsuite/H.J. Lu6-76/+109
2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands. * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit operands. * gas/testsuite/gas/i386/x86-64-avx.d: Updated. * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise. * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add vmovd with 64bit operand. * i386-tbl.h: Regenerated.
2008-05-272008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>Martin Schwidefsky3-2/+6
* s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> * gas/s390/zarch-z990.d (idte): Fix operand format.
2008-05-23gas/testsuite/H.J. Lu5-0/+21
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and cvttpd2pi. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. * i386-tbl.h: Regenerated.
2008-05-22gas/testsuite/H.J. Lu11-46/+3673
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * gas/i386/avx.s: Add tests for unspecified memory operand size in Intel syntax. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with unspecified memory operand size in Intel syntax. * gas/i386/avx.d: Updated. * gas/i386/avx-intel.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss into 32bit and 64bit. Remove Reg64|Qword and add IgnoreSize|No_qSuf on 32bit version. * i386-tbl.h: Regenerated.
2008-05-21gas/testsuite/H.J. Lu5-0/+16
2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. * i386-tbl.h: Regenerated.
2008-05-09 gas/Catherine Moore4-0/+194
* config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs with non-MIPS16 relocs. gas/testsuite/ * gas/mips/mips16-hilo-match.s: New test. * gas/mips/mip16-hilo-match.d: New test output.Index: config/tc-mips.c
2008-05-02gas/H.J. Lu30-58/+560
2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE, EPT and MOVBE. * config/tc-i386.c (cpu_arch): Add .movbe and .ept. (md_show_usage): Add .movbe and .ept. * doc/c-i386.texi: Add movbe and ept to -march=. Document .movbe and .ept. gas/testsuite/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept, ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel, x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and x86-64-inval-ept. * gas/i386/arch-10.s: Add movbe and invept. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/ept.d: New file * gas/i386/ept-intel.d: Likewise. * gas/i386/ept.s: Likewise. * gas/i386/inval-ept.l: Likewise. * gas/i386/inval-ept.s: Likewise. * gas/i386/inval-movbe.l: Likewise. * gas/i386/inval-movbe.s: Likewise. * gas/i386/movbe.d: Likewise. * gas/i386/movbe-intel.d: Likewise. * gas/i386/movbe.s: Likewise. * gas/i386/x86-64-inval-ept.l: Likewise. * gas/i386/x86-64-inval-ept.s: Likewise. * gas/i386/x86-64-inval-movbe.l: Likewise. * gas/i386/x86-64-inval-movbe.s: Likewise. * gas/i386/x86-64-ept.d: Likewise. * gas/i386/x86-64-ept-intel.d: Likewise. * gas/i386/x86-64-ept.s: Likewise. * gas/i386/x86-64-movbe.d: Likewise. * gas/i386/x86-64-movbe-intel.d: Likewise. * gas/i386/x86-64-movbe.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOVBE_Fixup): New. (Mo): Likewise. (PREFIX_0F3880): Likewise. (PREFIX_0F3881): Likewise. (PREFIX_0F38F0): Updated. (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and CPU_EPT_FLAGS. (cpu_flags): Add CpuMovbe and CpuEPT. * i386-opc.h (CpuMovbe): New. (CpuEPT): Likewise. (CpuLM): Updated. (i386_cpu_flags): Add cpumovbe and cpuept. * i386-opc.tbl: Add entries for movbe and EPT instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-04-30missed from 20080414 commit for e500mc supportAlan Modra1-0/+1
2008-04-28 * gas/mips/mips4.s: Split out fp instruction from here ...Adam Nemet23-98/+423
* gas/mips/mips4-fp.s: ... to here. * gas/mips/mips4.d: Update. * gas/mips/mips4-fp.l: New file. Check error messages with -msoft-float. * gas/mips/mips4-fp.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2.s: Split out fp instructions from here ... * gas/mips/mips32r2-fp32.s: ... to here. * gas/mips/mips32r2.d: Update. * gas/mips/mips32r2-fp32.l: New file. Check error messages with -msoft-float. * gas/mips/mips32r2-fp32.d: New file. Check disassembly with hard-float. * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New test derived from mips32r2-ill. * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check error messages for soft-float targets. * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l: New test for -msingle-float. * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l: New test for -msoft-float. * gas/mips/mips-hard-float-flag.s, gas/mips/mips-hard-float-flag.l: New test for -mhard-float. * gas/mips/mips-double-float-flag.s, gas/mips/mips-double-float-flag.l: New test for -mdouble-float. * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests. Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list test with -msoft-float. Run new mips-macro-ill-sfp test with -msingle-float. Run new mips-macro-ill-nofp test with -msoft-float. Run new mips-hard-float-flag and mips-double-float-flag tests.
2008-04-232008-04-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu6-0/+229
* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx. * gas/i386/sse-noavx.d: New. * gas/i386/sse-noavx.s: Likewise. * gas/i386/x86-64-sse-noavx.d: Likewise. * gas/i386/x86-64-sse-noavx.s: Likewise.
2008-04-232008-04-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu7-249/+376
* gas/i386/sse2.s: Add tests for pmuludq, paddq and psubq. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/sse2.d: Updated. * gas/i386/x86-64-simd.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd-suffix.d: Likewise.
2008-04-23opcodes/David S. Miller4-0/+26
* sparc-opc.c (asi_table): Add UltraSPARC and Niagara extended values. (prefetch_table): Add missing values. gas/ * config/tc-sparc.c (v9a_asr_table): Add missing 'stick' and 'stick_cmpr', and document ordering rules of table. (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and BFD_RELOC_SPARC_PC10. * doc/c-sparc.texi: New section on Sparc constants. Add documentation for %stick and %stick_cmpr. gas/testsuite/ * gas/sparc/pc2210.d: New file. * gas/sparc/pc2210.d: Likewise. * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
2008-04-18gas/H.J. Lu7-676/+685
2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Swap REG and NDS for FMA. gas/testsuite/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.d: Updated. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_VEX_FMA): New. (OP_EX_VexImmW): Likewise. (VexFMA): Likewise. (Vex128FMA): Likewise. (EXVexImmW): Likewise. (get_vex_imm8): Likewise. (OP_EX_VexReg): Likewise. (vex_i4_done): Renamed to ... (vex_w_done): This. (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on FMA instructions. (print_insn): Updated. (OP_EX_VexW): Rewrite to swap register in VEX with EX. (OP_REG_VexI4): Check invalid high registers.
2008-04-16<opcode changes>Dwarakanath Rajagopal3-1/+15
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * i386-opc.tbl: Fix protX to allow memory in the middle operand. * i386-tbl.h: Regenerate from i386-opc.tbl. <gas/testsuite changes> 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle operand. * gas/i386/x86-64-sse5.d: Likewise.
2008-04-16Sorry, missed this ChangeLog updat in previous commit.David S. Miller1-0/+8
2008-04-16bfd/David S. Miller5-1/+52
* reloc.c (BFD_RELOC_SPARC_GOTDATA_HIX22, BFD_RELOC_SPARC_GOTDATA_LOX10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, BFD_RELOC_SPARC_GOTDATA_OP): New. * libbfd.h: Regnerate. * bfd-in2.h: Regenerate. * elfxx-sparc.c (_bfd_sparc_elf_howto_table): Add entries for GOTDATA relocations. (sparc_reloc_map): Likewise. (_bfd_sparc_elf_check_relocs): Handle R_SPARC_GOTDATA_* like R_SPARC_GOT*. (_bfd_sparc_elf_gc_sweep_hook): Likewise. (_bfd_sparc_elf_relocate_section): Transform R_SPARC_GOTDATA_HIX22, R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, and R_SPARC_GOTDATA_OP_LOX10 into the equivalent R_SPARC_GOT* reloc. Simply ignore R_SPARC_GOTDATA_OP relocations. gas/ * config/tc-sparc.c (sparc_ip): Add support for gotdata mnemonics and relocation generation. (tc_gen_reloc): Likewise. gas/testsuite/ * gas/sparc/gotops32.d: New. * gas/sparc/gotops32.s: Likewise. * gas/sparc/gotops64.d: Likewise. * gas/sparc/gotops64.s: Likewise. * gas/sparc/sparc.exp: Run new gotdata tests. ld/testsuite/ * ld-sparc/gotop32.dd: New. * ld-sparc/gotop32.rd: Likewise. * ld-sparc/gotop32.s: Likewise. * ld-sparc/gotop32.sd: Likewise. * ld-sparc/gotop32.td: Likewise. * ld-sparc/gotop64.dd: Likewise. * ld-sparc/gotop64.rd: Likewise. * ld-sparc/gotop64.s: Likewise. * ld-sparc/gotop64.sd: Likewise. * ld-sparc/gotop64.td: Likewise. * ld-sparc/sparc.exp: Run new gotdata tests.
2008-04-152008-04-15 Andrew Stubbs <andrew.stubbs@st.com>Andrew Stubbs23-41/+133
gas/ * config/tc-sh.c (md_apply_fix): Make sure BFD_RELOC_SH_PCRELIMM8BY4 relocations are properly aligned, and not negative. gas/testsuite/ * gas/sh/arch/arch.exp: Align PC-relative instructions in the gererated assembly files. * gas/sh/arch/sh-dsp.s: Regenerate. * gas/sh/arch/sh.s: Regenerate. * gas/sh/arch/sh2.s: Regenerate. * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate. * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate. * gas/sh/arch/sh2a-nofpu.s: Regenerate. * gas/sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate. * gas/sh/arch/sh2a-or-sh4.s: Regenerate. * gas/sh/arch/sh2a.s: Regenerate. * gas/sh/arch/sh2e.s: Regenerate. * gas/sh/arch/sh3-dsp.s: Regenerate. * gas/sh/arch/sh3-nommu.s: Regenerate. * gas/sh/arch/sh3.s: Regenerate. * gas/sh/arch/sh3e.s: Regenerate. * gas/sh/arch/sh4-nofpu.s: Regenerate. * gas/sh/arch/sh4-nommu-nofpu.s: Regenerate. * gas/sh/arch/sh4.s: Regenerate. * gas/sh/arch/sh4a-nofpu.s: Regenerate. * gas/sh/arch/sh4a.s: Regenerate. * gas/sh/arch/sh4al-dsp.s: Regenerate. * gas/sh/err-mova.s: New test. ld/testsuite/ * ld-sh/arch/sh-dsp.s: Regenerate. * ld-sh/arch/sh.s: Regenerate. * ld-sh/arch/sh2.s: Regenerate. * ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate. * ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate. * ld-sh/arch/sh2a-nofpu.s: Regenerate. * ld-sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate. * ld-sh/arch/sh2a-or-sh4.s: Regenerate. * ld-sh/arch/sh2a.s: Regenerate. * ld-sh/arch/sh2e.s: Regenerate. * ld-sh/arch/sh3-dsp.s: Regenerate. * ld-sh/arch/sh3-nommu.s: Regenerate. * ld-sh/arch/sh3.s: Regenerate. * ld-sh/arch/sh3e.s: Regenerate. * ld-sh/arch/sh4-nofpu.s: Regenerate. * ld-sh/arch/sh4-nommu-nofpu.s: Regenerate. * ld-sh/arch/sh4.s: Regenerate. * ld-sh/arch/sh4a-nofpu.s: Regenerate. * ld-sh/arch/sh4a.s: Regenerate. * ld-sh/arch/sh4al-dsp.s: Regenerate.
2008-04-14ppc e500mc supportAlan Modra3-0/+101
2008-04-112008-04-11 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu5-4/+11
* gas/lns/lns-big-delta.d: Updated. * gas/lns/lns-common-1.d: Likewise. * gas/lns/lns-common-1-alt.d: Likewise. * gas/lns/lns-duplicate.d: Likewise.
2008-04-10gas/H.J. Lu12-0/+201
2008-04-10 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention -msse-check=[none|error|warning]. * config/tc-i386.c (sse_check): New. (OPTION_MSSE_CHECK): Likewise. (md_assemble): Check SSE instructions if needed. (md_longopts): Add -msse-check. (md_parse_option): Handle OPTION_MSSE_CHECK. (md_show_usage): Show -msse-check=[none|error|warning]. * doc/c-i386.texi: Document -msse-check=[none|error|warning]. gas/testsuite/ 2008-04-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run sse-check, sse-check-warn, sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and x86-64-sse-check-error. * gas/i386/sse-check.d: New. * gas/i386/sse-check.s: Likewise. * gas/i386/sse-check-error.l: Likewise. * gas/i386/sse-check-error.s: Likewise. * gas/i386/sse-check-warn.d: Likewise. * gas/i386/sse-check-warn.e: Likewise. * gas/i386/x86-64-sse-check.d: Likewise. * gas/i386/x86-64-sse-check-error.l: Likewise. * gas/i386/x86-64-sse-check-error.s: Likewise. * gas/i386/x86-64-sse-check-warn.d: Likewise.
2008-04-10 * listing.c: Add -ag listing flag to show general information inNick Clifton2-0/+30
listings such as gas version, passed options, and time stamp. (listing_general_info): New function. (print_options): New function. (print_single_option): New function. (print_timestamp): New function. (MAX_DATELEN): Define. (listing_print): Add call to listing_general_info. * listing.h (LISTING_GENERAL): Define. (listing_print): Add new parameter. * as.c (show_usage): Print new switch. (parse_args): Parse new switch. (main): Pass command line on to listing_print. * NEWS: Mention this new feature. * doc/as.texinfo: Document the new sub-option. * gas/all/gas.exp: Check the performance of the -ag command line switch.
2008-04-102008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel2-212/+217
* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic extensions for conditional jumps (o, p, m, nz, z, nm, np, no). (s390_crb_extensions): New extensions table. (insertExpandedMnemonic): Handle '$' tag. * s390-opc.txt: Remove conditional jump variants which can now be expanded automatically. Replace '*' tag with '$' in the compare and branch instructions. 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: Map the compare and branch variants with odd condition code mask to version with an even mask.
2008-04-07Add the missing ymm test in the last checkin.H.J. Lu4-0/+4
2008-04-07gas/H.J. Lu5-0/+16
2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (parse_real_register): Return AVX register only if AVX is enabled. gas/testsuite/ 2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/att-regs.s: Add AVX register test. * gas/i386/intel-regs.s: Likewise. * gas/i386/att-regs.d: Updated. * gas/i386/intel-regs.d: Likewise.
2008-04-07 PR gas/6043Kaz Kojima3-0/+27
* config/tc-sh64.c (shmedia_md_pcrel_from_section): Use md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL. * gas/sh/sh64/eh-1.d: New. * gas/sh/sh64/eh-1.d: Likewise.
2008-04-04gas/H.J. Lu15-14/+32
2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE. Change CLMUL to PCLMUL. * config/tc-i386.c (cpu_arch): Add .pclmul. (md_show_usage): Replace clmul with pclmul. * doc/c-i386.texi: Likewise. gas/testsuite/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/arch-10.d: Replace clmul with pclmul. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL with CPU_PCLMUL_FLAGS/CpuPCLMUL. (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. * i386-opc.tbl: Likewise. * i386-opc.h (CpuCLMUL): Renamed to ... (CpuPCLMUL): This. (CpuFMA): Updated. (i386_cpu_flags): Replace cpuclmul with cpupclmul. * i386-init.h: Regenerated.
2008-04-03binutils/H.J. Lu45-109/+21537
2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-03-26gas/testsuite/:Bernd Schmidt29-2281/+2313
From Robin Getz <rgetz@blackfin.uclinux.org> * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in recent changes in opcodes/bfin-dis.c. gas/bfin/arithmetic.s: Likewise. gas/bfin/bit.d: Likewise. gas/bfin/bit2.d: Likewise. gas/bfin/control_code.d: Likewise. gas/bfin/control_code2.d: Likewise. gas/bfin/event.d: Likewise. gas/bfin/event2.d: Likewise. gas/bfin/flow.d: Likewise. gas/bfin/flow2.d: Likewise. gas/bfin/load.d: Likewise. gas/bfin/logical.d: Likewise. gas/bfin/logical2.d: Likewise. gas/bfin/move.d: Likewise. gas/bfin/move2.d: Likewise. gas/bfin/parallel.d: Likewise. gas/bfin/parallel2.d: Likewise. gas/bfin/parallel3.d: Likewise. gas/bfin/parallel4.d: Likewise. gas/bfin/shift.d: Likewise. gas/bfin/shift2.d: Likewise. gas/bfin/stack.d: Likewise. gas/bfin/stack2.d: Likewise. gas/bfin/store.d: Likewise. gas/bfin/vector.d: Likewise. gas/bfin/vector2.d: Likewise. gas/bfin/video.d: Likewise. gas/bfin/video2.d: Likewise. opcodes/: * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, c_imm32, c_huimm32e): Define. (constant_formats): Add flags for printing decimal, leading spaces, and exact symbols. (comment, parallel): Add global flags in all disassembly. (fmtconst): Take advantage of new flags, and print default in hex. (fmtconst_val): Likewise. (decode_macfunc): Be consistant with spaces, tabs, comments, capitalization in disassembly, fix minor coding style issues. (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, _print_insn_bfin, print_insn_bfin): Likewise.
2008-03-26gas/:Bernd Schmidt3-27/+17
* config/tc-bfin.c (bfin_start_line_hook): Localize the labels generated for LOOP_BEGIN and LOOP_END instructions. (bfin_gen_loop): Likewise. gas/testsuite/: * gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN and LOOP_END instruction are local now. * gas/bfin/flow2.d: Likewise.
2008-03-26gas/Bernd Schmidt5-37/+52
* config/bfin-parse.y (check_macfunc_option): Allow (IU) option for multiply and multiply-accumulate to data register instruction. (check_macfuncs): Don't check if accumulator matches the data register here. (assign_macfunc): Check if accumulator matches the data register in each rule that moves to the data register. gas/testsuite/ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check for IU option. * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add check for mismatch of accumulator and data register. opcodes/ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction.
2008-03-26gas/:Bernd Schmidt5-674/+717
* config/bfin-parse.y (check_macfunc_option): New. (check_macfuncs): Check option by calling check_macfunc_option. Fix comparison always true warnings. Both scalar instructions of vector instruction must share the same mode option. Only allow option mode at the end of the second instruction of the vector. (asm_1): Check option by calling check_macfunc_option. gas/testsuite/: * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add tests for bad options of "multiply and multipy-accumulate to accumulator" instructions. Add new vector instruction option mode tests. * gas/bfin/vector2.s: Add new vector instruction option mode test. * gas/bfin/vector2.d: Adjust accordingly. * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test for mismatched half registers in vector multipy-accumulate instructions.
2008-03-26gas/Bernd Schmidt4-0/+35
From Jie Zhang <jie.zhang@analog.com> * config/bfin-parse.y (asm_1): Check AREGS in comparison instructions. And call yyerror () when comparing PREG with DREG. gas/testsuite/: * gas/bfin/expected_comparison_errors.l: New test. * gas/bfin/expected_comparison_errors.s: New test. * gas/bfin/bfin.exp: Add expected_comparison_errors.
2008-03-26opcodes:Bernd Schmidt2-10/+15
From Robin Getz <robin.getz@analog.com> * bfin-dis.c (bu32): Typedef. (enum const_forms_t): Add c_uimm32 and c_huimm32. (constant_formats[]): Add uimm32 and huimm16. (fmtconst_val): New. (uimm32): Define. (huimm32): Define. (imm16_val): Define. (luimm16_val): Define. (struct saved_state): Define. (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. gas/testsuite: From Jie Zhang <jie.zhang@analog.com> * gas/bfin/load.d: Update.
2008-03-192008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel4-0/+754
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.
2008-03-18 * gas/macros/test1.s: Rename symbols to avoid conflicts withNick Clifton2-4/+4
possible register names. * gas/macros/test1.d: Update expected disassembly.
2008-03-17gas/testsuite/Richard Sandiford3-2/+7
* gas/mips/elf-rel26.d: Add -32. * gas/mips/mips16-intermix.d: Likewise. ld/testsuite/ * ld-mips-elf/mips-elf.exp (o32_as_flags, o32_ld_flags): New variables. (mips16_call_global_test, mips16_intermix_test): Use them.
2008-03-13PR gas/5895Nick Clifton3-0/+20
* read.c (s_mexit): Warn if attempting to exit a macro when not inside a macro definition. * gas/macros/exit.s: New test case. * gas/macros/macros.exp: Run the new test, expect it to produce an error result.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+62
bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-062008-03-06 Florian Krohm <fkrohm@us.ibm.com>Andreas Krebbel7-48/+60
* s390-opc.c (INSTR_RSL_R0RD): Fix operands. * s390-opc.txt (cmpsc): Duplicate entry removed. (dxr, sqdr, sqer, cxfbr, cdfbr, cefbr, lzer, lzdr, lzxr, cegbr, cdgbr, cxgbr, cegr, cdgr, cxgr, cxfr, cdfr, cefr, fixr, fidr, fier, cu42, cu41): Fix operand format. 2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr, dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix operand format. * gas/s390/esa-g5.s: Likewise. * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr, cxgr): Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand. * gas/s390/zarch-z9-109.s: Likewise.
generated by cgit v1.1 at 2025-03-15 21:11:09 +0000