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2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich7-0/+105
Generally, the documentation doesn't allow for any explicit operands to be specified with MONITOR/MWAIT. To permit the more legible overriding of the address size via specifying operands, the option is being retained even in Intel mode, but operand swapping is being suppressed by this patch. This is both because it makes no sense here (all of the operands are inputs) and because, as a result, old gcc (prior to 4.8) actually expects it this way with -mintel-syntax (and hence gets fixed by this change rather than, as claimed by a reply in the bug report, broken).
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich8-5/+62
Conversions which shrink element size and which have a memory source can't be disambiguated between their 128- and 256-bit variants by looking at the register operand. "operand size mismatch", however, is a pretty misleading diagnostic. Generalize the logic introduced for VFPCLASSP{S,D} such that, with suitable similar adjustments to the respective templates, it'll cover these cases too. For VCVTNEPS2BF16 also fold the two previously separate AVX512VL templates to achieve the intended effect. This is then also accompanied by a respective addition to the inval-avx512f testcase.
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich27-68/+1596
For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
2020-02-14x86: adjust segment override prefix emissionJan Beulich2-1/+14
Since we already suppress the prefix altogether when it's the default one for the chosen addressing mode, let's do so also when instruction prefix and override specified with the memory operand match. (Note that insn prefix specified segment overrides never get discarded.)
2020-02-14x86: optimize away pointless segment overridesJan Beulich2-0/+14
When optimizing there's no point keeping the segment overrides when we warn about their presence in the first place.
2020-02-14x86: extend LEA's segment override warningJan Beulich4-0/+20
For one both possible forms should be warned about. And then, to guard against future surprises, qualify the original opcode check by excluding VEX/EVEX-like templates.
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu5-0/+50
Since PLT entry isn't needed for branch to local symbol, we can resolve R_386_PLT32/R_X86_64_PLT32 relocation aganst local symbol to section, similar to R_386_PC32/R_X86_64_PC32. 2020-02-13 Fangrui Song <maskray@google.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/25551 * config/tc-i386.c (tc_i386_fix_adjustable): Don't check BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32. * testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4. * testsuite/gas/i386/relax-5.d: New file. * testsuite/gas/i386/relax-5.s: Likewise. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. * testsuite/gas/i386/x86-64-relax-4.s: Likewise.
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich4-2/+22
With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich7-0/+54
AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich5-26/+39
Along the lines of be4c5e58bd ("x86: Always disallow double word suffix with word general register") also adjust check_{byte,word}_reg(), to make overall behavior consistent again in this regard.
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson11-0/+1103
Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson7-0/+960
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu2-1/+7
Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by default. By default, assembler should accept common, Intel64 only and AMD64 ISAs since there are no conflicts. gas/ PR gas/25516 * config/tc-i386.c (intel64): Renamed to ... (isa64): This. (match_template): Accept Intel64 only instruction by default. (i386_displacement): Updated. (md_parse_option): Updated. * c-i386.texi: Update -mamd64/-mintel64 documentation. * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass -mamd64 to x86-64-sysenter-amd. * testsuite/gas/i386/x86-64-sysenter.d: New file. opcodes/ PR gas/25516 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 with ISA64. * i386-opc.h (AMD64): Removed. (Intel64): Likewose. (AMD64): New. (INTEL64): Likewise. (INTEL64ONLY): Likewise. (i386_opcode_modifier): Replace amd64 and intel64 with isa64. * i386-opc.tbl (Amd64): New. (Intel64): Likewise. (Intel64Only): Likewise. Replace AMD64 with Amd64. Update sysenter/sysenter with Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. * i386-tbl.h: Regenerated.
2020-02-10gas: error for section type, attr, or entsize changeAlan Modra2-5/+6
* config/obj-elf.c (obj_elf_change_section): Error for section type, attr or entsize changes in assembly. * testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test. * testsuite/gas/elf/section5.l: Update.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov6-0/+3499
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-06ELF: Support the section flag 'o' in .section directiveH.J. Lu10-0/+98
As shown in https://sourceware.org/bugzilla/show_bug.cgi?id=25490 --gc-sections will silently remove __patchable_function_entries section and generate corrupt result. This patch adds the section flag 'o' to .section directive: .section __patchable_function_entries,"awo",@progbits,foo .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat .section __patchable_function_entries,"awo",@progbits,bar,unique,4 .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1 which specifies the symbol name which the section references. Assmebler will set its elf_linked_to_section to a local section where the symbol is defined. Linker is updated to call mark_hook if gc_mark of any of its linked-to sections is set after all sections, except for backend specific ones, have been garbage collected. bfd/ PR gas/25381 * bfd-in2.h: Regenerated. * elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook on section if gc_mark of any of its linked-to sections is set and don't set gc_mark again. * section.c (asection): Add linked_to_symbol_name to map_head union. gas/ PR gas/25381 * config/obj-elf.c (get_section): Also check linked_to_symbol_name. (obj_elf_change_section): Also set map_head.linked_to_symbol_name. (obj_elf_parse_section_letters): Handle the 'o' flag. (build_group_lists): Renamed to ... (build_additional_section_info): This. Set elf_linked_to_section from map_head.linked_to_symbol_name. (elf_adjust_symtab): Updated. * config/obj-elf.h (elf_section_match): Add linked_to_symbol_name. * doc/as.texi: Document the 'o' flag. * testsuite/gas/elf/elf.exp: Run PR gas/25381 tests. * testsuite/gas/elf/section18.d: New file. * testsuite/gas/elf/section18.s: Likewise. * testsuite/gas/elf/section19.d: Likewise. * testsuite/gas/elf/section19.s: Likewise. * testsuite/gas/elf/section20.d: Likewise. * testsuite/gas/elf/section20.s: Likewise. * testsuite/gas/elf/section21.d: Likewise. * testsuite/gas/elf/section21.l: Likewise. * testsuite/gas/elf/section21.s: Likewise. ld/ PR ld/24526 PR ld/25021 PR ld/25490 * testsuite/ld-elf/elf.exp: Run PR ld/25490 tests. * testsuite/ld-elf/pr24526.d: New file. * testsuite/ld-elf/pr24526.s: Likewise. * testsuite/ld-elf/pr25021.d: Likewise. * testsuite/ld-elf/pr25021.s: Likewise. * testsuite/ld-elf/pr25490-2-16.rd: Likewise. * testsuite/ld-elf/pr25490-2-32.rd: Likewise. * testsuite/ld-elf/pr25490-2-64.rd: Likewise. * testsuite/ld-elf/pr25490-2.s: Likewise. * testsuite/ld-elf/pr25490-3-16.rd: Likewise. * testsuite/ld-elf/pr25490-3-32.rd: Likewise. * testsuite/ld-elf/pr25490-3-64.rd: Likewise. * testsuite/ld-elf/pr25490-3.s: Likewise. * testsuite/ld-elf/pr25490-4-16.rd: Likewise. * testsuite/ld-elf/pr25490-4-32.rd: Likewise. * testsuite/ld-elf/pr25490-4-64.rd: Likewise. * testsuite/ld-elf/pr25490-4.s: Likewise. * testsuite/ld-elf/pr25490-5-16.rd: Likewise. * testsuite/ld-elf/pr25490-5-32.rd: Likewise. * testsuite/ld-elf/pr25490-5-64.rd: Likewise. * testsuite/ld-elf/pr25490-5.s: Likewise. * testsuite/ld-elf/pr25490-6-16.rd: Likewise. * testsuite/ld-elf/pr25490-6-32.rd: Likewise. * testsuite/ld-elf/pr25490-6-64.rd: Likewise. * testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-06x86: Run unique tests only for ELF targetsH.J. Lu3-4/+2
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique only for ELF targets. * testsuite/gas/i386/unique.d: Don't xfail. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06xfail x86 gas unique testAlan Modra2-0/+2
* testsuite/gas/i386/unique.d: xfail for non-elf targets. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06mbind gas tests and supports_gnu_osabi testsuite infrastructureAlan Modra4-12/+8
With the addition of section16 tests we have multiple tests advertising themselves as "mbind sections" and "mbind section contents". This patch fixes that, and fails on quite a few targets that force an OSABI value. It's a pain specifying all the relevant arm targets on an xfail line, so I wrote supports_gnu_osabi. binutils/ * testsuite/lib/binutils-common.exp (match_target): Accept '!' before TCL procedure. (supports_gnu_osabi): New procedure. (is_generic): New, from ld-lib.exp. (supports_gnu_unique): Use the above. gas/ * testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in xfail, and rename test. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. ld/ * testsuite/lib/ld-lib.exp (is_generic): Delete. * testsuite/ld-unique/unique.exp: Exclude tic6x.
2020-02-02ELF: Add support for unique section ID to assemblerH.J. Lu13-0/+317
Clang's integrated assembler supports multiple section with the same name: .section .text,"ax",@progbits,unique,1 nop .section .text,"ax",@progbits,unique,2 nop "unique,N" assigns the number, N, as the section ID, to a section. The valid values of the section ID are between 0 and 4294967295. It can be used to distinguish different sections with the same section name. This is useful with -fno-unique-section-names -ffunction-sections. -ffunction-sections by default generates .text.foo, .text.bar, etc. Using the same string can save lots of space in .strtab. This patch adds section_id to bfd_section and reuses the linker internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler internal use to mark valid section_id. It also updates objdump to compare section pointers if 2 sections comes from the same file since 2 different sections can have the same section name. bfd/ PR gas/25380 * bfd-in2.h: Regenerated. * ecoff.c (bfd_debug_section): Add section_id. * section.c (bfd_section): Add section_id. (SEC_ASSEMBLER_SECTION_ID): New. (BFD_FAKE_SECTION): Add section_id. binutils/ PR gas/25380 * objdump.c (sym_ok): Return FALSE if 2 sections are in the same file with different section pointers. gas/ PR gas/25380 * config/obj-elf.c (section_match): Removed. (get_section): Also match SEC_ASSEMBLER_SECTION_ID and section_id. (obj_elf_change_section): Replace info and group_name arguments with match_p. Also update the section ID and flags from match_p. (obj_elf_section): Handle "unique,N". Update call to obj_elf_change_section. * config/obj-elf.h (elf_section_match): New. (obj_elf_change_section): Updated. * config/tc-arm.c (start_unwind_section): Update call to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texi: Document "unique,N" in .section directive. * testsuite/gas/elf/elf.exp: Run "unique,N" tests. * testsuite/gas/elf/section15.d: New file. * testsuite/gas/elf/section15.s: Likewise. * testsuite/gas/elf/section16.s: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. * testsuite/gas/elf/section17.d: Likewise. * testsuite/gas/elf/section17.l: Likewise. * testsuite/gas/elf/section17.s: Likewise. * testsuite/gas/i386/unique.d: Likewise. * testsuite/gas/i386/unique.s: Likewise. * testsuite/gas/i386/x86-64-unique.d: Likewise. * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique. ld/ PR gas/25380 * testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section directives. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-02elf/section13.s: Replace @nobits with %nobitsH.J. Lu1-1/+1
* testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
2020-01-31arm: PR gas/25472 Enable DSP instructions with +mveAndre Vieira1-0/+140
We noticed +mve was not enabling DSP instructions as it should, reported in PR 25472. The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions. This patch reflects that in the '+mve' command line option. gas/ChangeLog: 2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com> PR gas/25472 * config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding. (armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for +mve. * testsuite/gas/arm/mve_dsp.d: New test.
2020-01-31[ARM]: Add support for vldmia/vldmdb/vstmia/vstmdb instructions in MVE.Srinath Parvathaneni2-0/+56
This patch adds support for assembly instructions vldmia, vldmdb, vstmia and vstmdb in MVE. This instructions are already supported for Armv8-M Floating-point Extension. gas/ChangeLog: 2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMIA instruction for MVE. (fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB instruction for MVE. (fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA instruction for MVE. (fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB instruction for MVE. * testsuite/gas/arm/mve-ldst.d: New test. * testsuite/gas/arm/mve-ldst.s: Likewise.
2020-01-31aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford5-2/+86
bfcvt converts a .S input to a .H output, so any predicated movprfx needs to operate on .S rather than .H. In common with SVE2 narrowing top operations, bfcvtnt doesn't accept movprfx. 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. Remove C_SCAN_MOVPRFX for SVE bfcvtnt. gas/ * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than .s for the movprfx. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_28.d, * testsuite/gas/aarch64/sve-movprfx_28.l, * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-30x86: prevent undue use of GOT32X and alike relocationsJan Beulich3-28/+59
Comparison of i.tm.base_opcode against particular but not sufficiently specific values needs to be accompanied by other qualification. Exclude VEX and alike encodings here, and also exclude all forms of prefixes explicitly specified in the opcodes table. While using @GOT with such insns may not be very useful, it also isn't with e.g. ADC and SBB, yet these get explicitly listed in comments as supported.
2020-01-30cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi4-4/+4
This patch fixes the neg/neg32 BPF instructions, which have K (=0) instead of X (=1) in their header source bit, despite operating on registes. cpu/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-alu-insn-un): The unary BPF instructions (neg and neg32) use OP_SRC_K even if they operate only in registers. opcodes/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c: Regenerate. gas/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. * testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich7-22/+52
While vendors agree about default operand size (64 bits) and hence unavilability of a 32-bit form, AMD honors a 16-bit operand size override (0x66) while Intel doesn't.
2020-01-30x86-64: also diagnose far returns / IRET with ambiguous operand sizeJan Beulich15-41/+101
Other than near returns these default to 32-bit operand size, and hence it isn't really unlikely that 64-bit forms are meant. Hence these should have disambiguating suffixes. In Intel mode, however, don't error in these cases unconditionally - MASM accepts these without suffix _and_ without warning.
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu11-0/+230
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit destination registers. Its AT&T mnemonic is movslq which only supports 64-bit destination register. There is also a discrepancy between AMD64 and Intel64 on movsxd with 16-bit destination register. AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit destination registers. It also handles movsxd with 16-bit destination register for AMD64 and Intel 64. gas/ PR binutils/25445 * config/tc-i386.c (check_long_reg): Also convert to QWORD for movsxd. * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA differences. Document movslq and movsxd. * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd.d: Likewise. * testsuite/gas/i386/x86-64-movsxd.s: Likewise. opcodes/ PR binutils/25445 * i386-dis.c (MOVSXD_Fixup): New function. (movsxd_mode): New enum. (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. (intel_operand_size): Handle movsxd_mode. (OP_E_register): Likewise. (OP_G): Likewise. * i386-opc.tbl: Remove Rex64 and allow 32-bit destination register on movsxd. Add movsxd with 16-bit destination register for AMD64 and Intel64 ISAs. * i386-tbl.h: Regenerated.
2020-01-27Replace deprecated tcl case statements with switch statementsAlan Modra4-104/+106
binutils/ * testsuite/lib/binutils-common.exp (big_or_little_endian): Replace case statement with switch statement. gas/ * testsuite/gas/all/gas.exp: Replace case statements with switch statements. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/macros/macros.exp: Likewise. * testsuite/lib/gas-defs.exp: Likewise. ld/ * testsuite/ld-elfvers/vers.exp: Replace case statements with switch statements. * testsuite/ld-ifunc/ifunc.exp: Likewise. * testsuite/ld-unique/unique.exp: Likewise.
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina2-0/+4
This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2020-01-22RISC-V: Change -march parsing.Jim Wilson7-1/+12
bfd/ 2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com> * bfd/elfnn-riscv.c (riscv_skip_prefix): New. (riscv_prefix_cmp): Likewise. (riscv_non_std_ext_p): Deleted. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_merge_non_std_and_sv_ext): Rename to... (riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp. (riscv_merge_arch_attr_info): Replace 3 calls to riscv_merge_non_std_and_sv_ext with single call to riscv_merge_multi_letter_ext. * bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we encounter a 'z' prefix. (riscv_get_prefix_class): New function, return prefix class based on first few characters of input string. (riscv_parse_config): New structure to factor out minor differences in extension class parsing behaviour. (riscv_parse_sv_or_non_std_ext): Rename to... (riscv_parse_prefixed_ext): and parameterise with riscv_parse_config. (riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New. (riscv_multi_letter_ext_valid_p): New. (riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New. (riscv_parse_subset): Delegate all non-single-letter parsing work to riscv_parse_prefixed_ext. * bfd/elfxx-riscv.h (riscv_isa_ext_class): New type. (riscv_get_prefix_class): Declare. gas/ 2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com> * testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and s exts must be known, so rename *ok* to *fail*. * testsuite/gas/riscv/march-ok-sx.d: Likewise. * testsuite/gas/riscv/march-ok-s-with-version: Likewise. * testsuite/gas/riscv/march-fail-s.l: Expected error messages for above change. * testsuite/gas/riscv/march-fail-sx.l: Likewise. * testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise. Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
2020-01-22x86: Always disallow double word suffix with word general registerH.J. Lu4-12/+17
In 64-bit mode, double word suffix in mnemonic with word general register is disallowed. Otherwise, assembler gives a warning: $ cat /tmp/x.s movl %ax, %bx movl %ds, %ax movl %ax, %cs $ gcc -c /tmp/x.s /tmp/x.s: Assembler messages: /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix $ gcc -c /tmp/x.s -m32 /tmp/x.s: Assembler messages: /tmp/x.s: Assembler messages: /tmp/x.s:1: Warning: using `%ebx' instead of `%bx' due to `l' suffix /tmp/x.s:1: Warning: using `%eax' instead of `%ax' due to `l' suffix /tmp/x.s:2: Warning: using `%eax' instead of `%ax' due to `l' suffix /tmp/x.s:3: Warning: using `%eax' instead of `%ax' due to `l' suffix This patch makes it a hard error in all modes. Now we get: $ gcc -c /tmp/x.s -m32 /tmp/x.s: Assembler messages: /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix PR gas/25438 * config/tc-i386.c (check_long_reg): Always disallow double word suffix in mnemonic with word general register. * testsuite/gas/i386/general.s: Replace word general register with double word general register for movl. * testsuite/gas/i386/inval.s: Add tests for movl with word general register. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/inval.l: Likewise.
2020-01-21x86: testsuite adjustments after commit 1a0351246a5cJan Beulich4-0/+8
The odd behavior of certain COFF/PE targets makes necessary some mechanical adjustments.
2020-01-21x86: replace adhoc ambiguous operand checking for CRC32Jan Beulich11-6/+24
There's no need (anymore?) to heavily special case this - just make generic logic consider only its first operand, and deal with the case of an 'l' suffix not being allowed in a pattern.
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich43-95/+961
Commit b76bc5d54e ("x86: don't default variable shift count insns to 8-bit operand size") pointed out a very bad case, but the underlying problem is, as mentioned on various occasions, much larger: Silently selecting a (nowhere documented afaict) certain default operand size when there's no "sizing" suffix and no suitable register operand(s) is simply dangerous (for the programmer to make mistakes). While in Intel syntax mode such mistakes already lead to an error (which is going to remain that way), AT&T syntax mode now gains warnings in such cases by default, which can be suppressed or promoted to an error if so desired by the programmer. Furthermore at least general purpose insns now consistently have a default applied (alongside the warning emission), rather than accepting some and refusing others. No warnings are (as before) to be generated for "DefaultSize" insns as well as ones acting on selector and other fixed-width values. For SYSRET, however, the DefaultSize needs to be dropped - it had been wrongly put there in the first place, as it's unrelated to .code16gcc (no stack accesses involved). As set forth as a prereq when I first mentioned this intended change a few years back, Linux as well as gcc have meanwhile been patched to avoid (emission of) ambiguous operands (and hence triggering of the new warning). Note that I think that in 64-bit mode IRET and far RET would better get a diagnostic too, as it's reasonably likely that a suffix-less instance really is meant to be a 64-bit one. But I guess I better make this a separate follow-on patch. Note further that floating point operations with integer operands are an exception for now: They continue to use short (16-bit) operands by default even in 32- and 64-bit modes. Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also need to be diagnosed, with their 64-bit forms not being very useful I think it is better to continue to avoid warning about them (by way of them carrying IgnoreSize attributes).
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich4-0/+16
Just like other VCVT*{X,Y} templates do, and to allow the programmer flexibility (might be relevant in particular when heavily macro-izing code), the two templates should also have Broadcast set, just like their X/Y-suffix-less counterparts. This in turn requires them to also have * Dword set on their memory operands, to cover the logic added to i386gen by 4a1b91eabbe7 ("x86: Expand Broadcast to 3 bits"), * RegXMM/RegYMM set on their source operands, to satisfy broadcast sizing logic in gas itself. Otherwise ATTSyntax templates wouldn't need such operand size attributes. While extending the test cases, also add Intel syntax broadcast forms without explicit size specifiers.
2020-01-20x86-64: Fix TLSDESC relaxation for x32H.J. Lu2-0/+4
For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix even if it isn't required. Otherwise linker can’t safely perform GDesc -> IE/LE optimization. X32 TLSDESC sequences can be: 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg ... 67 ff 10 call *x@TLSCALL(%eax) or the same sequence as LP64: 48 8d 05 00 00 00 00 lea foo@TLSDESC(%rip), %reg ... ff 10 call *foo@TLSCALL(%rax) We need to support both sequences for x32. For both GDesc -> IE/LE transitions, 67 ff 10 call *x@TLSCALL(%eax) should relaxed to 0f 1f 00 nopl (%rax) For GDesc -> LE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 c7 c0 fc ff ff ff rex movl $x@tpoff, %reg For GDesc -> IE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 8b 05 00 00 00 00 rex movl x@gottpoff(%rip), %eax bfd/ PR ld/25416 * elf64-x86-64.c (elf_x86_64_check_tls_transition): Support "rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in X32 mode. (elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl x@gottpoff(%rip), %eax". For both transitions, relax "call *(%eax)" to "nopl (%rax)". gas/ PR ld/25416 * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating x32 object. * testsuite/gas/i386/ilp32/x32-tls.d: Updated. * testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with R_X86_64_GOTPC32_TLSDESC relocation. ld/ PR ld/25416 * testsuite/ld-x86-64/pr25416-1.s: New file * testsuite/ld-x86-64/pr25416-1a.d: Likewise. * testsuite/ld-x86-64/pr25416-1b.d: Likewise. * testsuite/ld-x86-64/pr25416-1.s: Likewise. * testsuite/ld-x86-64/pr25416-2.s: Likewise. * testsuite/ld-x86-64/pr25416-2a.d: Likewise. * testsuite/ld-x86-64/pr25416-2b.d: Likewise. * testsuite/ld-x86-64/pr25416-3.d: Likewise. * testsuite/ld-x86-64/pr25416-3.s: Likewise. * testsuite/ld-x86-64/pr25416-4.d: Likewise. * testsuite/ld-x86-64/pr25416-4.s: Likewise. * testsuite/ld-x86-64/pr25416-5a.c: Likewise. * testsuite/ld-x86-64/pr25416-5b.s: Likewise. * testsuite/ld-x86-64/pr25416-5c.s: Likewise. * testsuite/ld-x86-64/pr25416-5d.s: Likewise. * testsuite/ld-x86-64/pr25416-5e.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu2-6/+6
There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix can't encode all operands. By default, assembler tries 2-byte VEX prefix first. {vex3} can be used to force 3-byte VEX prefix. This patch adds {vex} pseudo prefix and keeps {vex2} for backward compatibility. gas/ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 with vex_encoding_vex. (parse_insn): Likewise. * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} and {vex3} documentation. * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with {vex}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-opc.tbl: Add {vex} pseudo prefix. * i386-tbl.h: Regenerated.
2020-01-17Forgot to add testcases to commit for [binutils][arm] PR25376 Change MVE ...Andre Vieira4-0/+30
The original commit was 2da2eaf4ce299c84c5a1f1bc6f7944266cb36d6e
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich3-0/+36
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz3-0/+28
gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-14x86: Updated align branch tests for Darwin and i686-pc-elfLili Cui21-179/+221
1. Update align branch assembler tests to match Darwin disassembler outputs. 2. Skip unsupported "call *foo" tests in 64-bit mode on Darwin. 3. Update align branch linker test to match any addresses for i686-pc-elf. gas/ * testsuite/gas/i386/align-branch-1a.d: Updated for Darwin. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-1i.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a, x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin. ld/ * testsuite/ld-i386/align-branch-1.d: Updated for i686-pc-elf.
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov6-9/+53
PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
2020-01-13[ARC][committed] Code cleanup and improvements.Claudiu Zissulescu1-1/+1
Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
2020-01-13ubsan: wasm32: signed integer overflowAlan Modra1-2/+2
The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
2020-01-10HPUX gas testsuite fixesAlan Modra2-2/+3
* testsuite/gas/elf/pr14891.s: Don't start directives in first column. * testsuite/gas/elf/pr21661.d: Don't run on hpux.
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich6-0/+51
The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-08Make the assembler generate an error if there is an attempt to define a ↵Nick Clifton4-0/+12
section with the same name as an already defined symbol. PR 14891 * config/obj-elf.c (obj_elf_section): Fail if the section name is already defined as a different symbol type. * testsuite/gas/elf/pr14891.s: New test source file. * testsuite/gas/elf/pr14891.d: New test driver. * testsuite/gas/elf/pr14891.s: New test expected error output. * testsuite/gas/elf/elf.exp: Run the new test.
2020-01-03Allow individual targets to decide if string escapes should be allowed. ↵Sergey Belyashov1-3/+3
Disable for PPC and Z80. PR 25311 * as.h (TC_STRING_ESCAPES): Provide a default definition. * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of NO_STRING_ESCAPES. * read.c (next_char_of_string): Likewise. * config/tc-ppc.h (TC_STRING_ESCAPES): Define. * config/tc-z80.h (TC_STRING_ESCAPES): Define.
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