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2023-01-17gas: arm: Change warning message to not reference specific A-class architectu...Stam Markianos-Wright4-222/+222
2023-01-17gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtnStam Markianos-Wright4-2/+65
2023-01-16PR29991, MicroMIPS flag erased after align directivesAlan Modra4-0/+30
2023-01-10Add aarch64-w64-mingw32 targetMark Harmstone1-1/+1
2023-01-10Add pe-aarch64 relocationsMark Harmstone2-14/+378
2023-01-02obsolete target tidyAlan Modra6-11/+7
2023-01-01Update year range in copyright notice of binutils filesAlan Modra192-192/+192
2022-12-30PR29948, heap-buffer-overflow in display_debug_lines_decodedAlan Modra1-2/+2
2022-12-27RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner1-2/+2
2022-12-23RISC-V: Relax the order checking for the architecture stringNelson Chu7-14/+8
2022-12-22gas: sframe: testsuite: add testcase for .cfi_b_key_frameIndu Bhagat3-0/+64
2022-12-22gas: re-arrange listing output for .irp and alikeJan Beulich1-2/+2
2022-12-22x86: correct dependencies of a few AVX512 sub-featuresJan Beulich1-6/+6
2022-12-22x86: rework noavx512-1 testcaseJan Beulich3-587/+415
2022-12-16gas: sframe: testsuite: add testcase for .cfi_negate_ra_stateIndu Bhagat3-0/+39
2022-12-16gas: sframe: add support for .cfi_negate_ra_stateIndu Bhagat3-32/+0
2022-12-16gas: restore Dwarf info generation after macro diagnostic adjustmentsJan Beulich4-0/+26
2022-12-14RISC-V: Add string length check for operands in ASLi Xu3-0/+7
2022-12-13gas: re-work line number tracking for macros and their expansionsJan Beulich57-2537/+9605
2022-12-13Arm: avoid unhelpful uses of .macro in testsuiteJan Beulich141-2306/+2237
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich8-11/+184
2022-12-12x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich3-0/+24
2022-12-12ix86: don't recognize/derive Q suffix in the common caseJan Beulich12-26/+59
2022-12-12x86: re-work insn/suffix recognitionJan Beulich5-4/+26
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ...Jan Beulich6-52/+52
2022-12-07PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner5-0/+52
2022-12-07PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner3-0/+30
2022-12-05gas: add Dwarf line number test for .macro expansionsJan Beulich3-0/+56
2022-12-05opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess13-514/+514
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu10-8/+170
2022-11-30x86: extend FPU test coverage for AT&T / Intel mnemonic differencesJan Beulich5-0/+44
2022-11-28RISC-V: Better support for long instructions (tests)Tsukasa OI4-1/+48
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner11-0/+860
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich2-0/+60
2022-11-24x86: correct handling of LAR and LSLJan Beulich5-19/+63
2022-11-23gas: Add --gcodeview optionMark Harmstone4-0/+342
2022-11-21Fix ARM and AArch64 assembler tests to work in a multi-arch environment.Nick Clifton4-4/+4
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI8-97/+154
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner2-0/+14
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2-0/+14
2022-11-15gas: testsuite: add new tests for SFrame unwind infoIndu Bhagat29-0/+533
2022-11-16Re: [gas] arm: Add support for new unwinder directive ".pacspval".Alan Modra1-4/+5
2022-11-15Add AMD znver4 processor supportTejas Joshi9-0/+127
2022-11-15aarch64, testsuite: Fixed recently added cssc.dAndre Vieira1-7/+0
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2-0/+334
2022-11-14[gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni2-0/+53
2022-11-14arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni1-0/+6
2022-11-12PowerPC64 paddi -MrawAlan Modra2-0/+3
2022-11-10i386: Check invalid (%dx) usageH.J. Lu4-0/+28
2022-11-09x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich3-15/+15
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