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AgeCommit message (Expand)AuthorFilesLines
2022-03-23x86: improve resolution of register equatesJan Beulich2-2/+18
2022-03-23x86: don't attempt to resolve equates and alike from i386_parse_name()Jan Beulich3-0/+29
2022-03-23gas/Dwarf: improve debug info generation from .irp and alike blocksJan Beulich3-0/+112
2022-03-23ELF32: don't silently truncate relocation addendsJan Beulich6-9/+23
2022-03-23gas: retain whitespace between stringsJan Beulich3-0/+43
2022-03-21x86: don't suppress overflow diagnostics in x32 modeJan Beulich2-0/+28
2022-03-21z80 assembler: Fix new unexpected overflow warning in v2.37Nick Clifton2-0/+23
2022-03-18RISC-V: Cache management instructionsTsukasa OI10-0/+70
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI5-0/+27
2022-03-17x86: don't accept base architectures as extensionsJan Beulich3-0/+4
2022-03-17x86: add another IAMCU testcaseJan Beulich2-2/+7
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich7-532/+0
2022-03-17x86: assorted IAMCU CPU checking fixesJan Beulich3-0/+6
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-5/+5
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra2-17/+17
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra2-14/+14
2022-03-09Constant fold view increment expressionsAlan Modra1-2/+1
2022-03-04RISC-V: make .insn actually work for 64-bit insnsJan Beulich2-0/+8
2022-03-04x86: drop redundant x86-64-code16-2 testJan Beulich2-5/+0
2022-02-23RISC-V: PR28733, add missing extension info to 'unrecognized opcode' errorPatrick O'Neill2-22/+22
2022-02-23RISC-V: PR28733, add missing extension info to 'invalid CSR' errorPatrick O'Neill4-696/+696
2022-02-23RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu11-245/+288
2022-02-23RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI11-0/+1249
2022-02-23RISC-V: Reorganize testcases for CFI directivesTsukasa OI2-13/+86
2022-01-12gas: add visibility support using GNU syntax on XCOFFClément Chigot4-0/+47
2022-01-12gas: add visibility support for XCOFFClément Chigot6-32/+253
2022-01-12objdump, readelf: Emit "CU:" format only when wide output is requestedHans-Peter Nilsson1-1/+1
2022-01-10XCOFF: add support for TLS relocations on hidden symbolsClément Chigot7-84/+289
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu6-6/+6
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-0/+56
2022-01-05Adjust quoted-sym-names testAlan Modra2-6/+6
2022-01-04x86/Intel: correct VFPCLASSP{S,D} handling when displacement is presentJan Beulich3-4/+4
2022-01-04gas: rework handling of backslashes in quoted symbol namesJan Beulich4-7/+27
2022-01-02Update year range in copyright notice of binutils filesAlan Modra191-191/+191
2021-12-24RISC-V: Rewrite the csr testcases.Nelson Chu42-1521/+3567
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta4-0/+308
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta9-90/+0
2021-12-22RISC-V: Update Scalar Crypto testcases.jiawei18-144/+144
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev8-420/+420
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton4-6/+6
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford9-0/+81
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford6-0/+54
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford15-0/+88
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+20
2021-12-09RISC-V: Clarify the behavior of .option arch directive.Nelson Chu8-9/+13
2021-12-02aarch64: Add BC instructionRichard Sandiford5-0/+86
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-0/+174
2021-12-02aarch64: Add support for +mopsRichard Sandiford5-0/+1557
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford5-0/+46
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford5-0/+8
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