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AgeCommit message (Expand)AuthorFilesLines
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich4-0/+42
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich9-13/+16
2017-11-23Fix vax/ns32k/mmix gas testsuite regression.Jim Wilson1-1/+1
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist17-96/+192
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich3-0/+20
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich2-0/+10
2017-11-23x86: correct UDnJan Beulich8-11/+12
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich2-6/+0
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+3
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss1-0/+11
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu4-0/+50
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss22-155/+168
2017-11-21mingw gas testsuite fixAlan Modra1-0/+1
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+2
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina12-0/+12808
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2-4/+76
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich3-0/+3
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu1-13/+8
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina4-4/+4
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton12-12/+12
2017-11-15x86: use correct register namesJan Beulich2-0/+21
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich3-0/+23
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich8-0/+73
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson1-0/+1
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich3-1194/+1194
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich6-0/+216
2017-11-14x86: string insns don't allow displacementsJan Beulich5-33/+43
2017-11-13gas/ia64: fix testsuite failuresJan Beulich3-11/+12
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich2-0/+11
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich2-0/+9
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich2-0/+3
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson1-1/+1
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina2-0/+12
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina5-0/+547
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang9-0/+1354
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson3-0/+24
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt3-0/+15
2017-11-07bundle_lock message tidyAlan Modra1-3/+3
2017-11-07readelf ngettext fixesAlan Modra31-132/+132
2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme2-2/+2
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman18-258/+2577
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme24-34/+289
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu12-0/+20
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson1-2/+2
2017-10-25Yet another fill-1 test fixAlan Modra2-2/+3
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman7-0/+16
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman4-0/+8
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu5-4/+40
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist13-0/+1040
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist13-0/+971
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