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While documented to not be reliable, it is still odd for objcopy to
silently produce bad output when converting COFF/PE object files to ELF
ones. The issue there is that relocation addends all are screwed up by
subtracting the symbol's section offset. In the COFF/PE world, to my
knowledge, section contents stores the addends alone, not the result of
symbol value plus addend. Hence the compensation talked about in a
comment ahead of the sole use site of CALC_ADDEND() may need to account
for the VMA (which is always zero for object files anyway), but not for
the symbol value.
The coff-sh.c adjustment is based upon guessing that behavior there is
the same. Note also how coff-aarch64.c short-circuits CALC_ADDEND()
altogether, which may suggest that a much simpler macro might do for the
COFF_WITH_PE case in the three arch-specific files touched here.
For (at least) Arm/WinCE this actually results in more appropriate
objdump output as well, as can be seen in the one testcase which has its
expectations adjusted (the generated binary doesn't change).
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Rather than special-casing rx-*-* for section30, force use of
conventional section names uniformly. By further passing $dump_opts to
a few more tests, a number of xfail-s (and one notarget) can be
eliminated (some of which had wrong justifications in associated
comments anyway). Note that section7 and section15 need to be left
alone: The harness fiddling with section names there didn't help before
and is getting in the way now. For section12b, section16b, and most of
the Dwarf tests nothing changes. Interestingly by passing $dump_opts
the need to xfail section11 for LoongArch and RISC-V also goes away.
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While --sectname-subst is nice, it isn't enough to e.g. mimic
-f{function,data}-sections in assembly code, when such use is to be
optional (e.g. dependent upon some configuration setting).
Assign meaning to '+' and '-' as section attribute letters, allowing
to inherit the prior section's attributes (and possibly type) along
with adding or removing some. Note that documenting the interaction
with '?' as undefined is a precautionary measure.
While touching the function invocation, stop using |= on the result of
obj_elf_parse_section_letters(): "attr" is firmly zero ahead of the
call.
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The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header
source bit, despite operating on registers. If BPF_SRC_X (=1) is set,
the instructions are rejected by the kernel.
Because of this there are also no neg/neg32 instructions which operate
on immediates, so remove them.
bd434cc4d94ec3d2f9fc1e7c00c27b074f962bc1 was a similar fix in the old
CGEN-based port, but was not carried forward in the new port.
include/
* opcode/bpf.h (enum bpf_insn_id): Remove spurious entries
BPF_INSN_NEGI and BPF_INSN_NEG32I.
opcodes/
* bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I
instructions.
gas/
* doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and
neg32 instructions operating on immediates.
* testsuite/gas/bpf/alu.s: Adapt accordingly.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
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This commit changes the BPF GAS port in order to handle immediate
overflows the same way than the clang BPF assembler:
- For an immediate field of N bits, any written number (positive or
negative) whose two's complement encoding fit in N its is accepted.
This means that -2 is the same than 0xffffffe. It is up to the
instructions to decide how to interpret the encoded value.
- Immediate fields in jump instructions are no longer relaxed.
Relaxing to jump instructions with wider range is only performed
when expressions are involved.
- The manual is updated to document this, and testsuite adapted
accordingly.
Tested in x86_64-linux-gnu host, bpf-unknown-none target.
gas/ChangeLog:
2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (check_immediate_overflow): New function.
(encode_insn): Use check_immediate_overflow.
(md_assemble): Do not relax instructions with
constant disp16 fields.
* doc/c-bpf.texi (BPF Instructions): Add note about how numerical
literal values are interpreted for instruction immediate operands.
* testsuite/gas/bpf/disp16-overflow.s: Adapt accordingly.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/jump-relax-ja.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja-be.d: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.l: Likewise.
* testsuite/gas/bpf/disp32-overflow.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.l: Likewise.
* testsuite/gas/bpf/offset16-overflow.l: Likewise.
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This patch adds support for the Cortex-A720 CPU to binutils.
bfd/ChangeLog:
* cpu-aarch64.c: Add Cortex-A720.
gas/ChangeLog:
* NEWS: Update docs.
* config/tc-aarch64.c: Add Cortex-A720.
* doc/c-aarch64.texi: Update docs.
* testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
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On some T-Head vendor extensions, we test against the constant
18446744073709551615 (2**64-1) to detect invalid immediate errors on -1.
However, it heavily depends on the fact that the value used to print
immediate value is a 64-bit unsigned type and this constant is not (and
should not be) important (we just want to know that -1 is not valid).
This commit replaces all such occurrences of 18446744073709551615 with
a more generic regular expression.
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-ba-fail.l: Replace
18446744073709551615 with generic regular expression.
* testsuite/gas/riscv/x-thead-bb-fail.l: Likewise.
* testsuite/gas/riscv/x-thead-bs-fail.l: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx-fail.l: Likewise.
* testsuite/gas/riscv/x-thead-memidx-fail.l: Likewise.
* testsuite/gas/riscv/x-thead-mempair-fail.l: Likewise.
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The documentation of the 'Zfa' extension states that "fli.h" is available
"if the Zfh or Zvfh extension is implemented" (both the latest and the
oldest editions are checked).
This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full
'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions).
This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh'
extensions are implemented.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add new
instruction class handling.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zfa-zvfh.s: New test.
* testsuite/gas/riscv/zfa-zvfh.d: Ditto.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h"
from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA.
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This commit adds 'Zihintntl' extension and its hint instructions.
This is based on:
<https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6da7791d5a733c553e6e2506ddcab5>,
the first ISA Manual noting that the 'Zihintntl' extension is ratified.
Note that compressed 'Zihintntl' hints require either 'C' or
'Zca' extension.
Co-authored-by: Nelson Chu <nelson@rivosinc.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl'
standard hint 'Z' extension.
(riscv_multi_subset_supports): Support new instruction classes.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl'
including auto-compression without C prefix and explicit C prefix.
* testsuite/gas/riscv/zihintntl.d: Likewise.
* testsuite/gas/riscv/zihintntl-na.d: Likewise.
* testsuite/gas/riscv/zihintntl-base.s: New test for correspondence
between 'Zihintntl' and base 'I' or 'C' instructions.
* testsuite/gas/riscv/zihintntl-base.d: Likewise.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C.
(MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL,
MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL,
MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL,
MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL,
MATCH_C_NTL_ALL): New.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add instructions from the
'Zihintntl' extension.
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No one should be using versions of dejagnu without prune_warnings,
which was available in 1996 (dejagnu-1.3).
binutils/
* testsuite/lib/binutils-common.exp: Remove fallback prune_warnings.
gas/
* testsuite/lib/gas-defs.exp: Remove fallback prune_warnings.
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PR 30715
* config/tc-vax.c (md_create_long_jump): Use pc-relative addressing.
* testsuite/gas/vax/broken_word.d,
* testsuite/gas/vax/broken_word.s: New test.
* testsuite/gas/vax/vax.exp: Run it.
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The 32-bit non-fetching atomic instructions treat the source register as
32-bits, which means in the pseudo-c syntax the "w" registers should be
used rather than the "r" registers.
opcodes/
* bpf-opc-c (bpf_opcodes): Use %sw for AAD32, AOR32, AAND32
and AXOR32 pseudo-c dialect asm templates.
gas/
* testsuite/gas/bpf/atomic-be-pseudoc.d: Use "w" for source reg
in non-fetching 32-bit atomic instructions.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
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This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d.
See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
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gas/ChangeLog:
* testsuite/gas/riscv/rouding-fail.s: Moved to...
* testsuite/gas/riscv/rounding-fail.s: ...here.
* testsuite/gas/riscv/rouding-fail.d: Moved to...
* testsuite/gas/riscv/rounding-fail.d: ...here.
* testsuite/gas/riscv/rouding-fail.l: Moved to...
* testsuite/gas/riscv/rounding-fail.l: ...here.
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This patch makes the BPF assembler to throughfully check for overflow
in immediates. This includes relaxed instructions.
Tested in bpf-unknown-none.
gas/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (signed_overflow): Copy function from
tc-aarch64.c.
(encode_insn): Check for overflow in constant immediates.
(add_relaxed_insn): Pass relax argument to encode_insn.
(add_fixed_insn): Likewise.
* testsuite/gas/bpf/disp16-overflow.d: New file.
* testsuite/gas/bpf/disp16-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.l: Likewise.
* testsuite/gas/bpf/disp32-overflow.d: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.d: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/imm32-overflow.l: Likewise.
* testsuite/gas/bpf/offset16-overflow.d: Likewise.
* testsuite/gas/bpf/offset16-overflow.s: Likewise.
* testsuite/gas/bpf/offset16-overflow.l: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.d: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.l: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: New file.
* testsuite/gas/bpf/bpf.exp: Run new tests.
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The BPF jump-always instruction (JA), like all other jump instructions
in the ISA, get a signed 16-bit displacement target argument denoted
in number of 64-bit words minus one. This can sometimes be overflown.
The BPF V4 ISA thus introduced support for a jump-always
instruction (JAL) that gets a signed 32-bit displacement instead.
This patch makes the BPF assembler to perform the following
relaxations when the disp16 field gets overflown, unless the option
-mno-relax is specified:
JA disp16 -> JAL disp32
Jxx disp16 -> Jxx +1; JA +1; JAL disp32
Documentation and tests added.
Tested in bpf-unknown-none.
gas/ChangeLog:
2023-07-28 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/30690
* config/tc-bpf.c (struct bpf_insn): Add fields is_relaxable and
relaxed_exp.
(enum options): Add OPTION_NO_RELAX.
(md_longopts): Likewise for -mno-relax.
(do_relax): New global.
(md_parse_option): Handle OPTION_NO_RELAX.
(RELAX_BRANCH_ENCODE): Define.
(RELAX_BRANCH_P): Likewise.
(RELAX_BRANCH_LENGTH): Likewise.
(RELAX_BRANCH_CONST): Likewise.
(RELAX_BRANCH_UNCOND): Likewise.
(relaxed_branch_length): New function.
(md_estimate_size_before_relax): Likewise.
(read_insn_word): Likewise.
(encode_int16): Likewise.
(encode_int32): Likewise.
(write_insn_bytes): Likewise.
(md_convert_frag): Likewise.
(encode_insn): Likewise.
(install_insn_fixups): Likewise.
(add_fixed_insn): Likewise.
(add_relaxed_insn): Likewise.
(md_assemble): Move instruction encoding logic to the above
new functions.
* testsuite/gas/bpf/jump-relax-ja.d: New test.
* testsuite/gas/bpf/jump-relax-ja-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: And corresponding source.
* testsuite/gas/bpf/jump-relax-jump.d: New test.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: And corresponding source.
* testsuite/gas/bpf/bpf.exp: Run new tests.
* doc/c-bpf.texi (BPF Options): Document -mno-relax.
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PR gas/30688
X_unsigned being clear does not indicate a negative number; it merely
indicates a signed one (whose sign may still be clear). Amend two uses
by an actual value check.
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Make the n64 ABI the default for 64-bit Linux targets specified with
`-gnuabi64' suffix included in the target triplet, for configurations
such as the Debian mips64el and mips64r6el ports. Adjust testsuite
configuration accordingly.
There are the following regressions with the new target triplet:
mips64-linux-gnuabi64 +FAIL: readelf -S bintest
mips64-linux-gnuabi64 +FAIL: MIPS reloc estimation 1
mips64el-linux-gnuabi64 +FAIL: readelf -S bintest
mips64el-linux-gnuabi64 +FAIL: MIPS reloc estimation 1
The `readelf' issue comes from a difference in section headers produced
that the `binutils/testsuite/binutils-all/readelf.s-64' pattern template
does not match. While there has been a precedent it does not appear to
me that there is a clear advantage from adding more and more variations
to the template rather than forking the existing template into multiple
ones for a more exact match. So this is best deferred to a separate
discussion.
The MIPS reloc estimation issue is an actual bug in `objdump', which
discards a number of trailing entries from output here for n64 composed
relocations:
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
0000000000000000 R_MIPS_NONE *ABS*
0000000000000000 R_MIPS_NONE *ABS*
and consequently `ld/testsuite/ld-mips-elf/reloc-estimate-1.d' does not
match even though ELF output produced is correct according to `readelf':
Relocation section '.rel.dyn' at offset 0x10400 contains 2 entries:
Offset Info Type Sym. Value Sym. Name
000000000000 000000000000 R_MIPS_NONE
Type2: R_MIPS_NONE
Type3: R_MIPS_NONE
000000010000 000300001203 R_MIPS_REL32 0000000000010010 foo@@V2
Type2: R_MIPS_64
Type3: R_MIPS_NONE
As a genuine bug this has to be handled separately.
Co-Authored by: Maciej W. Rozycki <macro@orcam.me.uk>
bfd/
* config.bfd: Add `mips64*el-*-linux*-gnuabi64' and
`mips64*-*-linux*-gnuabi64' targets.
binutils/
* testsuite/binutils-all/mips/mips.exp: Handle `*-*-*-gnuabi64'
targets.
* testsuite/binutils-all/objcopy.exp: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/binutils-all/remove-relocs-01.d: Likewise.
* testsuite/binutils-all/remove-relocs-04.d: Likewise.
* testsuite/binutils-all/remove-relocs-05.d: Likewise.
* testsuite/binutils-all/remove-relocs-06.d: Likewise.
gas/
* configure.ac: Handle `mips64*-linux-gnuabi64' targets.
* configure: Regenerate.
* testsuite/gas/mips/compact-eh-eb-7.d: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/gas/mips/compact-eh-el-7.d: Likewise.
ld/
* configure.tgt: Add `mips64*el-*-linux-gnuabi64' and
`mips64*-*-linux-gnuabi64' targets.
* testsuite/ld-undefined/undefined.exp: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/ld-mips-elf/attr-gnu-4-10.d: Likewise.
* testsuite/ld-mips-elf/compact-eh6.d: Likewise.
* testsuite/ld-mips-elf/mips-elf.exp: Handle `*-*-*-gnuabi64'
targets.
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Expect a `.MIPS.options' section alternatively to `.reginfo' and ignore
contents of either as irrelevant for all the affected compact EH tests,
removing these regressions:
mips64-openbsd -FAIL: Compact EH EB #1 with personality ID and FDE data
mips64-openbsd -FAIL: Compact EH EB #2 with personality routine and FDE data
mips64-openbsd -FAIL: Compact EH EB #3 with personality id and large FDE data
mips64-openbsd -FAIL: Compact EH EB #4 with personality id, FDE data and LSDA
mips64-openbsd -FAIL: Compact EH EB #5 with personality routine, FDE data and LSDA
mips64-openbsd -FAIL: Compact EH EB #6 with personality id, LSDA and large FDE data
mips64-openbsd -FAIL: Compact EH EL #1 with personality ID and FDE data
mips64-openbsd -FAIL: Compact EH EL #2 with personality routine and FDE data
mips64-openbsd -FAIL: Compact EH EL #3 with personality id and large FDE data
mips64-openbsd -FAIL: Compact EH EL #4 with personality id, FDE data and LSDA
mips64-openbsd -FAIL: Compact EH EL #5 with personality routine, FDE data and LSDA
mips64-openbsd -FAIL: Compact EH EL #6 with personality id, LSDA and large FDE data
mips64el-openbsd -FAIL: Compact EH EB #1 with personality ID and FDE data
mips64el-openbsd -FAIL: Compact EH EB #2 with personality routine and FDE data
mips64el-openbsd -FAIL: Compact EH EB #3 with personality id and large FDE data
mips64el-openbsd -FAIL: Compact EH EB #4 with personality id, FDE data and LSDA
mips64el-openbsd -FAIL: Compact EH EB #5 with personality routine, FDE data and LSDA
mips64el-openbsd -FAIL: Compact EH EB #6 with personality id, LSDA and large FDE data
mips64el-openbsd -FAIL: Compact EH EL #1 with personality ID and FDE data
mips64el-openbsd -FAIL: Compact EH EL #2 with personality routine and FDE data
mips64el-openbsd -FAIL: Compact EH EL #3 with personality id and large FDE data
mips64el-openbsd -FAIL: Compact EH EL #4 with personality id, FDE data and LSDA
mips64el-openbsd -FAIL: Compact EH EL #5 with personality routine, FDE data and LSDA
mips64el-openbsd -FAIL: Compact EH EL #6 with personality id, LSDA and large FDE data
Co-Authored-By: Maciej W. Rozycki <macro@orcam.me.uk>
gas/
* testsuite/gas/mips/compact-eh-eb-1.d: Accept `.MIPS.options'
section as an alternative to `.reginfo' and ignore contents of
either.
* testsuite/gas/mips/compact-eh-eb-2.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-3.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-4.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-5.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-6.d: Likewise.
* testsuite/gas/mips/compact-eh-el-1.d: Likewise.
* testsuite/gas/mips/compact-eh-el-2.d: Likewise.
* testsuite/gas/mips/compact-eh-el-3.d: Likewise.
* testsuite/gas/mips/compact-eh-el-4.d: Likewise.
* testsuite/gas/mips/compact-eh-el-5.d: Likewise.
* testsuite/gas/mips/compact-eh-el-6.d: Likewise.
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MIPS n64 ABI has a peculiarity where all relocations are composed of
three, with subsequent relocation types set to R_MIPS_NONE if further
calculation is not required. Example output produced by `readelf' and
`objdump' for such relocations is:
Offset Info Type Sym. Value Sym. Name + Addend
000000000000 000800000002 R_MIPS_32 0000000000000000 foo + 0
Type2: R_MIPS_NONE
Type3: R_MIPS_NONE
and:
OFFSET TYPE VALUE
0000000000000000 R_MIPS_32 foo
0000000000000000 R_MIPS_NONE *ABS*
0000000000000000 R_MIPS_NONE *ABS*
respectively. The presence of these extra R_MIPS_NONE entries is not
relevant for generic or even some MIPS tests, so optionally match them
with the respective dump patterns, also discarding `xfail' annotation
for MIPS/OpenBSD targets from gas/elf/missing-build-notes.d, removing
these regressions:
mips64-openbsd -FAIL: readelf -r bintest
mips64-openbsd -FAIL: forward expression
mips64-openbsd -FAIL: assignment tests
mips64-openbsd -FAIL: gas/all/none
mips64-openbsd -XFAIL: gas/elf/missing-build-notes
mips64-openbsd -FAIL: macro test 2
mips64-openbsd -FAIL: macro irp
mips64-openbsd -FAIL: macro rept
mips64-openbsd -FAIL: nested irp/irpc/rept
mips64-openbsd -FAIL: macro vararg
mips64-openbsd -FAIL: mips jalx
mips64-openbsd -FAIL: ST Microelectronics Loongson-2F workarounds of Jump Instruction issue
mips64el-openbsd -FAIL: readelf -r bintest
mips64el-openbsd -FAIL: forward expression
mips64el-openbsd -FAIL: assignment tests
mips64el-openbsd -FAIL: gas/all/none
mips64el-openbsd -XFAIL: gas/elf/missing-build-notes
mips64el-openbsd -FAIL: macro test 2
mips64el-openbsd -FAIL: macro irp
mips64el-openbsd -FAIL: macro rept
mips64el-openbsd -FAIL: nested irp/irpc/rept
mips64el-openbsd -FAIL: macro vararg
mips64el-openbsd -FAIL: mips jalx
mips64el-openbsd -FAIL: ST Microelectronics Loongson-2F workarounds of Jump Instruction issue
Co-Authored-By: Maciej W. Rozycki <macro@orcam.me.uk>
binutils/
* testsuite/binutils-all/readelf.r-64: Optionally match extra
R_MIPS_NONE pairs.
gas/
* testsuite/gas/all/assign.d: Optionally match extra
R_MIPS_NONE pairs.
* testsuite/gas/all/fwdexp.d: Likewise.
* testsuite/gas/all/none.d: Likewise.
* testsuite/gas/macros/irp.d: Likewise.
* testsuite/gas/macros/repeat.d: Likewise.
* testsuite/gas/macros/rept.d: Likewise.
* testsuite/gas/macros/test2.d: Likewise.
* testsuite/gas/macros/vararg.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-1.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-2.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-3.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-4.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-5.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-6.d: Likewise.
* testsuite/gas/mips/compact-eh-el-1.d: Likewise.
* testsuite/gas/mips/compact-eh-el-2.d: Likewise.
* testsuite/gas/mips/compact-eh-el-3.d: Likewise.
* testsuite/gas/mips/compact-eh-el-4.d: Likewise.
* testsuite/gas/mips/compact-eh-el-5.d: Likewise.
* testsuite/gas/mips/compact-eh-el-6.d: Likewise.
* testsuite/gas/mips/loongson-2f-3.d: Likewise.
* testsuite/gas/mips/mips-jalx.d: Likewise.
* testsuite/gas/elf/missing-build-notes.d: Likewise. Remove
the `xfail' tag.
ld/
* testsuite/ld-mips-elf/reloc-estimate-1.d: Optionally match
extra R_MIPS_NONE pairs.
|
|
Several MIPS test cases are suitable for the n64 ABI if not for the
extra leading zeros or spaces in addresses not handled by dump patterns.
Match the characters then, removing these regressions:
mips64-openbsd -FAIL: .set arch=FOO
mips64-openbsd -FAIL: ST Microelectronics Loongson-2F workarounds of nop issue
mips64-openbsd -FAIL: MIPS DSP ASE for MIPS64
mips64-openbsd -FAIL: gas/mips/align2
mips64-openbsd -FAIL: gas/mips/align2-el
mips64-openbsd -FAIL: Locally-resolvable PC-relative code references
mips64-openbsd -FAIL: MIPS jalx-1
mips64-openbsd -FAIL: JAL overflow 2
mips64el-openbsd -FAIL: .set arch=FOO
mips64el-openbsd -FAIL: ST Microelectronics Loongson-2F workarounds of nop issue
mips64el-openbsd -FAIL: MIPS DSP ASE for MIPS64
mips64el-openbsd -FAIL: gas/mips/align2
mips64el-openbsd -FAIL: gas/mips/align2-el
mips64el-openbsd -FAIL: Locally-resolvable PC-relative code references
mips64el-openbsd -FAIL: MIPS jalx-1
mips64el-openbsd -FAIL: JAL overflow 2
Co-Authored-By: Maciej W. Rozycki <macro@orcam.me.uk>
gas/
* testsuite/gas/mips/align2-el.d: Match extra leading zeros
with addresses.
* testsuite/gas/mips/align2.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-1.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-2.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-3.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-4.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-5.d: Likewise.
* testsuite/gas/mips/compact-eh-eb-6.d: Likewise.
* testsuite/gas/mips/compact-eh-el-1.d: Likewise.
* testsuite/gas/mips/compact-eh-el-2.d: Likewise.
* testsuite/gas/mips/compact-eh-el-3.d: Likewise.
* testsuite/gas/mips/compact-eh-el-4.d: Likewise.
* testsuite/gas/mips/compact-eh-el-5.d: Likewise.
* testsuite/gas/mips/compact-eh-el-6.d: Likewise.
* testsuite/gas/mips/loongson-2f-2.d: Likewise.
* testsuite/gas/mips/loongson-2f-3.d: Likewise.
* testsuite/gas/mips/mips-jalx.d: Likewise.
* testsuite/gas/mips/mips64-dsp.d: Likewise.
* testsuite/gas/mips/pcrel-1.d: Likewise.
* testsuite/gas/mips/set-arch.d: Likewise.
ld/
* testsuite/ld-mips-elf/jaloverflow-2.d: Match extra leading
zeros and spaces with addresses as appropriate.
* testsuite/ld-mips-elf/jalx-1.d: Likewise.
* testsuite/ld-mips-elf/reloc-estimate-1.d: Likewise.
|
|
A few GAS tests expect to be assembled with 32-bit addressing, otherwise
causing an assembly warning:
.../gas/testsuite/gas/mips/fix-rm7000-2.s:11: Warning: la used to load 64-bit address; recommend using dla instead
or pattern dump mismatches against 32-bit address calculations, however
these tests do not enforce their expectation in any. For none of them
the specific ABI used is of any relevance however, so select the o32 ABI
unconditionally, removing these failures with OpenBSD targets:
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (micromips)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips3)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips4)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips5)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r2)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r3)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r5)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon2)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon3)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeonp)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (r4000)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (sb1)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (vr5400)
mips64-openbsd -FAIL: MIPS RM7000 workarounds test 2 (xlr)
mips64-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeon2)
mips64-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeon3)
mips64-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeonp)
mips64-openbsd -FAIL: Full MIPS R5900
mips64-openbsd -FAIL: MIPS R5900 VU0
mips64-openbsd -FAIL: Paired LL/SC for mips64r6 (mips64r6)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (micromips)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips3)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips4)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips5)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r2)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r3)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (mips64r5)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon2)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeon3)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (octeonp)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (r4000)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (sb1)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (vr5400)
mips64el-openbsd -FAIL: MIPS RM7000 workarounds test 2 (xlr)
mips64el-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeon2)
mips64el-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeon3)
mips64el-openbsd -FAIL: MIPS-OCTEON octeon_saa_saad (octeonp)
mips64el-openbsd -FAIL: Full MIPS R5900
mips64el-openbsd -FAIL: MIPS R5900 VU0
mips64el-openbsd -FAIL: Paired LL/SC for mips64r6 (mips64r6)
Co-Authored-By: Maciej W. Rozycki <macro@orcam.me.uk>
gas/
* testsuite/gas/mips/fix-rm7000-2.d: Add `-32' to the `as' tag.
* testsuite/gas/mips/micromips@fix-rm7000-2.d: Likewise.
* testsuite/gas/mips/r5900-full.d: Likewise.
* testsuite/gas/mips/r5900-vu0.d: Likewise.
* testsuite/gas/mips/llpscp-64.d: Add `as' tag with `-32'.
* testsuite/gas/mips/octeon-saa-saad.d: Likewise.
|
|
Compact EH #7 tests use output templates that are not suitable for the
n64 ABI, which `mips64*-*-openbsd*' targets use by default, because the
contents of the sections examined are expected to be differnt. Disable
the tests then, removing these regressions:
mips64-openbsd -FAIL: Compact EH EB #7 with personality id and fallback FDE
mips64-openbsd -FAIL: Compact EH EL #7 with personality id and fallback FDE
mips64el-openbsd -FAIL: Compact EH EB #7 with personality id and fallback FDE
mips64el-openbsd -FAIL: Compact EH EL #7 with personality id and fallback FDE
Suitable corresponding tests for the n64 ABI can be added separately.
gas/
* testsuite/gas/mips/compact-eh-eb-7.d: Exclude for
`mips64*-*-openbsd*'.
* testsuite/gas/mips/compact-eh-el-7.d: Likewise.
|
|
* testsuite/gas/i386/sha512-intel.d: Accept section nop padding.
* testsuite/gas/i386/sha512.d: Likewise.
* testsuite/gas/i386/sm3-intel.d: Likewise.
* testsuite/gas/i386/sm3.d: Likewise.
* testsuite/gas/i386/x86-64-pbndkb-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pbndkb.d: Likewise.
* testsuite/gas/i386/x86-64-sha512-intel.d: Likewise.
* testsuite/gas/i386/x86-64-sha512.d: Likewise.
* testsuite/gas/i386/x86-64-sm3-intel.d: Likewise.
* testsuite/gas/i386/x86-64-sm3.d: Likewise.
|
|
Seen when running gas/testsuite/gas/sh/err-at.s
* config/tc-sh.c (get_operands): Always init operand type.
* testsuite/gas/sh/err-at.s: Expect unnecessary extra errors.
|
|
gas/ChangeLog:
* NEWS: Support Intel PBNDKB.
* config/tc-i386.c: Add pbndkb.
* doc/c-i386.texi: Document .pbndkb.
* testsuite/gas/i386/i386.exp: Add PBNDKB tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/pbndkb-inval.l: New test.
* testsuite/gas/i386/pbndkb-inval.s: Ditto.
* testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto.
* testsuite/gas/i386/x86-64-pbndkb.d: Ditto.
* testsuite/gas/i386/x86-64-pbndkb.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New.
(X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7.
(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0.
(rm_table): New entry for pbndkb.
* i386-gen.c (cpu_flag): Add PBNDKB.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuPBNDKB): New.
(i386_cpu_flags): Add cpupbndkb.
* i386-opc.tbl: Add PBNDKB instructions.
* i386-tbl.h: Regenerated.
|
|
gas/ChangeLog:
* NEWS: Support Intel SM4.
* config/tc-i386.c: Add sm4.
* doc/c-i386.texi: Document .sm4.
* testsuite/gas/i386/i386.exp: Run SM4 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sm4-intel.d: Add SM4 tests.
* testsuite/gas/i386/sm4.d: Ditto.
* testsuite/gas/i386/sm4.s: Ditto.
* testsuite/gas/i386/x86-64-sm4-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sm4.d: Ditto.
* testsuite/gas/i386/x86-64-sm4.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (prefix_table): Add SM4 instructions.
* i386-gen.c (isa_dependencies): Add SM4.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSM4): New.
(i386_cpu_flags): Add cpusm4.
* i386-opc.tbl: Add SM4 instructions.
* i386-tbl.h: Regenerated.
|
|
gas/ChangeLog:
* NEWS: Support Intel SM3.
* config/tc-i386.c: Add sm3.
* doc/c-i386.texi: Document .sm3.
* testsuite/gas/i386/i386.exp: Run sm3 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sm3-intel.d: New test.
* testsuite/gas/i386/sm3.d: Ditto.
* testsuite/gas/i386/sm3.s: Ditto.
* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sm3.d: Ditto.
* testsuite/gas/i386/x86-64-sm3.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
(VEX_LEN_0F38DA_W_0_P_0): Ditto.
(VEX_LEN_0F38DA_W_0_P_2): Ditto.
(VEX_LEN_0F3ADE_W_0): Ditto.
(VEX_W_0F38DA): Ditto.
(VEX_W_0F3ADE): Ditto.
(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
* i386-gen.c (isa_dependencies): Add SM3.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSM3): New.
(i386_cpu_flags): Add cpusm3.
* i386-opc.tbl: Add SM3 instructions.
* i386-tbl.h: Regenerated.
|
|
gas/ChangeLog:
* NEWS: Support Intel SHA512.
* config/tc-i386.c: Add sha512.
* doc/c-i386.texi: Document .sha512.
* testsuite/gas/i386/disassem.d: Add SHA512 tests.
* testsuite/gas/i386/disassem.s: Ditto.
* testsuite/gas/i386/i386.exp: Run SHA512 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/sha512-intel.d: New test.
* testsuite/gas/i386/sha512-inval.l: Ditto.
* testsuite/gas/i386/sha512-inval.s: Ditto.
* testsuite/gas/i386/sha512.d: Ditto.
* testsuite/gas/i386/sha512.s: Ditto.
* testsuite/gas/i386/x86-64-sha512-intel.d: Ditto.
* testsuite/gas/i386/x86-64-sha512-inval.l: Ditto.
* testsuite/gas/i386/x86-64-sha512-inval.s: Ditto.
* testsuite/gas/i386/x86-64-sha512.d: Ditto.
* testsuite/gas/i386/x86-64-sha512.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Rxmmq): New.
(Rymm): Ditto.
(PREFIX_VEX_0F38CB): Ditto.
(PREFIX_VEX_0F38CC): Ditto.
(PREFIX_VEX_0F38CD): Ditto.
(VEX_LEN_0F38CB_P_3_W_0): Ditto.
(VEX_LEN_0F38CC_P_3_W_0): Ditto.
(VEX_LEN_0F38CD_P_3_W_0): Ditto.
(VEX_W_0F38CB_P_3): Ditto.
(VEX_W_0F38CC_P_3): Ditto.
(VEX_W_0F38CD_P_3): Ditto.
(prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC,
PREFIX_VEX_0F38CD.
(vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0,
VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0.
(vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3.
* i386-gen.c (isa_dependencies): Add SHA512.
(cpu_flags): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (CpuSHA512): New.
(i386_cpu_flags): Add cpusha512.
* i386-opc.tbl: Add SHA512 instructions.
* i386-tbl.h: Regenerated.
|
|
gas/ChangeLog:
* NEWS: Support Intel AVX-VNNI-INT16.
* config/tc-i386.c: Add avx_vnni_int16.
* doc/c-i386.texi: Document avx_vnni_int16.
* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
* testsuite/gas/i386/avx-vnni-int16.d: New test.
* testsuite/gas/i386/avx-vnni-int16.s: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
(PREFIX_VEX_0F38D3_W_0): Ditto.
(VEX_W_0F38D2_P_0): Ditto.
(VEX_W_0F38D2_P_1): Ditto.
(VEX_W_0F38D2_P_2): Ditto.
(VEX_W_0F38D3_P_0): Ditto.
(VEX_W_0F38D3_P_1): Ditto.
(VEX_W_0F38D3_P_2): Ditto.
(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
PREFIX_VEX_0F38D3_W_0.
(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
(vex_w_table): Ditto.
* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
(cpu_flag): Ditto.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h: (CpuAVX_VNNI_INT16): New.
* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
* i386-tbl.h: Regenerated.
|
|
gas/ChangeLog:
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Add test for NEGI and NEG32I.
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
|
|
This patch fixes the BPF_INSN_NEGR and BPF_INSN_NEG32R BPF
instructions to not use their source registers.
Tested in bpf-unknown-none.
opcodes/ChangeLog:
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
register.
gas/ChangeLog:
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: The register neg instruction gets only
one argument.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* doc/c-bpf.texi (BPF Instructions): Update accordingly.
|
|
This patch adds the two remaining BPF v3 atomic instructions:
- BPF_INSN_ACMP{,32}: atomic compare-and-swap
- BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange
Tests and documentation are also updated.
gas/
* doc/c-bpf.texi (BPF Instructions): Document atomic exchange and
atomic compare-and-swap instructions.
* testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32
instructions.
* testsuite/gas/bpf/atomic.d: Likewise.
* testsuite/gas/bpf/atomic-be.d: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise.
include/
* opcode/bpf.h (BPF_IMM32_ACMP): Fix typo.
(enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and
BPF_INSN_AXCHG{,32}.
opcodes/
* bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and
AXCHG{,32} instructions.
|
|
This patch updates the pseudo-C dialect templates for the BPF v3 atomic
instructions. The templates match the strings emitted by clang -S for
these instructions.
The tests and documentation are updated accordingly.
gas/
* doc/c-bpf.texi (BPF Instructions): Update entries for atomic
and 32-bit atomic instructions.
* testsuite/gas/bpf/atomic.s: Test AAND, AAND32, AOR, AOR32,
AXOR, AXOR32, AFADD, AFADD32, AFAND, AFAND32, AFOR, AFOR32,
AFXOR and AFXOR32 instructions.
* testsuite/gas/bpf/atomic.d: Likewise.
* testsuite/gas/bpf/atomic-be.d: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic-v1.s: New test.
* testsuite/gas/bpf/atomic-v1.d: Likewise.
* testuiste/gas/bpf/atomic-v1-be.d: Likewise.
* testuiste/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-opc.c (bpf_opcodes): Update pseudo-C dialect templates for:
BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR,
BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR,
BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32,
BPF_INSN_AXOR32, BPF_INSN_AFADD32, BPF_INSN_AFOR32,
BPF_INSN_AFAND32, and BPF_INSN_AFXOR32 instructions.
|
|
The version 1.0.4-1 of the code size reduction specification clarifies
that 'Zcf' implies 'F' and 'Zcd' implies 'D'.
cf:
<https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1>
This commit adds those implications.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add two implications,
'Zcf' -> 'F' and 'Zcd' -> 'D'.
gas/ChangeLog:
* testsuite/gas/riscv/march-imply-zcd.d: New test.
* testsuite/gas/riscv/march-imply-zcf.d: New test.
|
|
As per:
<https://github.com/riscv/riscv-code-size-reduction/issues/221>,
the 'Zcf' extension does not exist on RV64. This is reflected on the
version 1.0.4-1 of the code size reduction specification:
<https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1>.
This commit prohibits the combination: RV64 (or any ISA with XLEN > 32)
and the 'Zcf' extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit
combination of RV64 and 'Zcf'.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv64i_zcf.d: New test.
* testsuite/gas/riscv/march-fail-rv64i_zcf.l: Likewise.
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This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
(BPF_IMM32_BSWAP32): Likewise.
(BPF_IMM32_BSWAP64): Likewise.
(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
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This patch fixes the pseudoc syntax of the V4 instructions MOVS* and
LDXS* in order to reflect https://reviews.llvm.org/D144829.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS*
and LDXS* instructions.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
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This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
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This tiny patch makes the BPF disassembler to emit, e.g.
ldxdw %r1, [%r0+0]
instead of
ldxdw %r1, [%r00]
when the offset is 0, to avoid confusion.
opcodes/
* bpf-dis.c (print_insn_bpf): Print offsets with value 0 as "+0".
gas/
* testsuite/gas/bpf/mem.s: Add tests with offset 0.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Update accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
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This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
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This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
(BPF_OFFSET16_MOVS16): Likewise.
(BPF_OFFSET16_MOVS32): Likewise.
(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R instructions. and MOVS32I instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
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CGEN is cool, but the BPF architecture is simply too bizarre for it.
The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port. The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update. Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.
This is getting un-maintenable.
So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN. Overall, this involved:
* To remove the cpu/bpf.{cpu,opc} descriptions.
* To remove the CGEN generated files.
* To replace the CGEN generated opcodes table with a new hand-written
opcodes table for BPF.
* To replace the CGEN generated disassembler wih a new disassembler
that uses the new opcodes.
* To replace the CGEN generated assembler with a new assembler that uses the
new opcodes.
* To replace the CGEN generated simulator with a new simulator that uses the
new opcodes. [This is pushed in GDB in another patch.]
* To adapt the build systems to the new situation.
Additionally, this patch introduces some extensions and improvements:
* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These
relocations are used for section-relative 16-bit offsets used in
load/store instructions.
* The disassembler now has support for the "pseudo-c" assembly syntax of
BPF. What dialect to use when disassembling is controlled by a command
line option.
* The disassembler now has support for dumping instruction immediates in
either octal, hexadecimal or decimal. The used output base is controlled
by a new command-line option.
* The GAS BPF test suite has been re-structured and expanded in order to
test the disassembler pseudoc syntax support. Minor bugs have been also
fixed there. The assembler generic tests that were disabled for bpf-*-*
targets due to the previous implementation of pseudoc syntax are now
re-enabled. Additional tests have been added to test the new features of
the assembler. .dump files are no longer used.
* The linker BPF test suite has been adapted to the command line options
used by the new disassembler.
The result is very satisfactory. This patchs adds 3448 lines of code
and removes 10542 lines of code.
Tested in:
* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
little-endian host.
* Target x86-64-linux-gnu with --enable-targets=all
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port. I beg the indulgence of the global maintainers.
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Bring disassembly back in line with what the assembler accepts, thus
also making it self-consistent (with, in particular selector load/store
insns). While there further add D to all affected insns except ARPL
(where S is used, matching LAR/LSL), to also behave correctly in suffix-
always mode.
While there also hook up the Intel variant of the LKGS test.
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This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'. Zcb also imply Zca extension to enable the compressing
features.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcb.d: New test.
* testsuite/gas/riscv/zcb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
(MASK_C_LBU): New mask.
(MATCH_C_LHU): New opcode.
(MASK_C_LHU): New mask.
(MATCH_C_LH): New opcode.
(MASK_C_LH): New mask.
(MATCH_C_SB): New opcode.
(MASK_C_SB): New mask.
(MATCH_C_SH): New opcode.
(MASK_C_SH): New mask.
(MATCH_C_ZEXT_B): New opcode.
(MASK_C_ZEXT_B): New mask.
(MATCH_C_SEXT_B): New opcode.
(MASK_C_SEXT_B): New mask.
(MATCH_C_ZEXT_H): New opcode.
(MASK_C_ZEXT_H): New mask.
(MATCH_C_SEXT_H): New opcode.
(MASK_C_SEXT_H): New mask.
(MATCH_C_ZEXT_W): New opcode.
(MASK_C_ZEXT_W): New mask.
(MATCH_C_NOT): New opcode.
(MASK_C_NOT): New mask.
(MATCH_C_MUL): New opcode.
(MASK_C_MUL): New mask.
(DECLARE_INSN): New opcode.
* opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
(EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
(ENCODE_ZCB_BYTE_UIMM): Ditto.
(ENCODE_ZCB_HALFWORD_UIMM): Ditto.
(VALID_ZCB_BYTE_UIMM): Ditto.
(VALID_ZCB_HALFWORD_UIMM): Ditto.
(enum riscv_insn_class): New extension class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operators.
* riscv-opc.c: New instructions.
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This patch add Zca/f/d extensions support, since all ZC*
extensions will imply Zca extension, just enabled compress
feature when Zca extension is available.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (riscv_set_arch): Extend compress check.
* testsuite/gas/riscv/zca.d: New test.
* testsuite/gas/riscv/zca.s: New test.
* testsuite/gas/riscv/zcd.d: New test.
* testsuite/gas/riscv/zcd.s: New test.
* testsuite/gas/riscv/zcf.d: New test.
* testsuite/gas/riscv/zcf.s: New test.
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Making target code depend on a host define like _AIX52 is never
correct, so out it goes. Also, sort some config.bfd entries a little
to make it more obvious there is a config difference between aix5.1
and aix5.2. These two changes should make no difference to anything
in binutils. The gas define of AIX_WEAK_SUPPORT on the other hand was
wrong, so fix that. Finally, fix some testsuite fails on aix < 5.2 by
simply not running the tests.
include/
* coff/internal.h (C_WEAKEXT): Don't depend on _AIX52.
bfd/
* coffcode.h (coff_slurp_symbol_table): Don't depend on _AIX52.
(coff_classify_symbol): Likewise.
* config.bfd: Sort some entries.
gas/
* configure.ac (AIX_WEAK_SUPPORT): Don't set for aix5.[01].
* configure: Regenerate.
* testsuite/gas/ppc/aix.exp (xcoff-visibility-1*) Don't run
for aix < 5.2.
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