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2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+3
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+5
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-1/+4
2020-07-28x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu1-1/+1
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+7
2020-07-07x86: Remove an incorrect AVX2 entryH.J. Lu1-10/+0
2020-06-16x86: Correct noavx512_vp2intersectCui,Lili1-0/+1
2020-04-27x86: Add i386 PE big-object supportTamar Christina1-1/+2
2020-04-26Improve -mlfence-after-loadliuhongt1-4/+8
2020-04-08x86: Correct -mlfence-before-indirect-branch= documentationH.J. Lu1-3/+3
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-1/+3
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+2
2020-03-11i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]H.J. Lu1-0/+43
2020-03-04x86: support VMGEXITJan Beulich1-1/+2
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-5/+6
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-1/+3
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu1-16/+0
2020-02-14x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu1-0/+53
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-0/+12
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-1/+2
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-0/+18
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-0/+25
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-2/+2
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu1-0/+11
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu1-0/+26
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-1/+4
2019-07-01Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton1-0/+6
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-1/+2
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-1/+4
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-6/+10
2019-06-26i386: Document memory size reference in assemblerLili Cui1-5/+10
2019-06-25x86: document certain command line options as "dangerous"Jan Beulich1-0/+6
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu1-0/+1
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-1/+2
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-1/+2
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-1/+3
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-1/+3
2019-03-18x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEXH.J. Lu1-4/+6
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-0/+10
2018-08-31x86: Extend assembler to generate GNU property notesH.J. Lu1-0/+9
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-3/+8
2018-07-02Fix use of "command line X" in binutils docThomas Preud'homme1-1/+1
2018-05-30Add znver2 support.Amit Pawar1-2/+3
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+3
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-3/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+3
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-1/+2
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-1/+2
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