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2022-03-20gas:LoongArch: Fix "make check" pr21884 fail in LoongArch32.liuzhensong2-0/+9
2022-03-20LoongArch: Update ABI eflag in elf header.liuzhensong1-26/+20
2022-03-20gas:LoongArch: Fix wrong line number in .debug_lineliuzhensong1-2/+2
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-2/+6
2022-03-20LoongArch: Use functions instead of magic numbers.liuzhensong1-104/+28
2022-03-18x86: also fold remaining multi-vector-size shift insnsJan Beulich1-7/+9
2022-03-18x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich1-0/+23
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+18
2022-03-18PR28977 tc-i386.c internal error in parse_registerAlan Modra1-9/+10
2022-03-17x86: don't accept base architectures as extensionsJan Beulich1-1/+1
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich2-72/+4
2022-03-17x86: assorted IAMCU CPU checking fixesJan Beulich1-4/+4
2022-03-16Delete PowerPC macro insn supportAlan Modra1-111/+3
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-2/+2
2022-03-04RISC-V: make .insn actually work for 64-bit insnsJan Beulich1-1/+1
2022-02-23RISC-V: PR28733, add missing extension info to 'unrecognized opcode' errorPatrick O'Neill1-14/+47
2022-02-23RISC-V: PR28733, add missing extension info to 'invalid CSR' errorPatrick O'Neill1-15/+21
2022-02-23binutils 2.38 vs. ppc32 linux kernelAlan Modra1-1/+24
2022-02-16gas local label and dollar label handlingAlan Modra1-2/+2
2022-01-22RISC-V: create new frag after alignment.Lifang Xia1-0/+6
2022-01-13Re: gas: add visibility support using GNU syntax on XCOFFAlan Modra1-1/+1
2022-01-12gas: add visibility support using GNU syntax on XCOFFClément Chigot1-0/+38
2022-01-12gas: add visibility support for XCOFFClément Chigot1-4/+152
2022-01-10XCOFF: add support for TLS relocations on hidden symbolsClément Chigot1-13/+19
2022-01-07RISC-V: update docs for -mpriv-spec/--with-priv-spec for 1.12Philipp Tomsich1-1/+1
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu1-1/+1
2022-01-06x86: drop NoAVX insn attributeJan Beulich1-17/+21
2022-01-06x86-64: restrict PC32 -> PLT32 conversionJan Beulich2-3/+7
2022-01-04x86/Intel: correct VFPCLASSP{S,D} handling when displacement is presentJan Beulich1-1/+5
2022-01-02Update year range in copyright notice of binutils filesAlan Modra243-243/+243
2021-12-28gas reloc sortingAlan Modra3-41/+2
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-5/+5
2021-12-21x86: -mfence-as-lock-add=yes doesn't work for 16-bit modeJan Beulich1-1/+6
2021-12-21gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()Jan Beulich1-13/+11
2021-12-16Fix AVR assembler so that it creates relocs that will work with linker relaxa...Nick Clifton2-0/+29
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-1/+11
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford1-0/+7
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-0/+3
2021-12-15loongarch64 build failure on 32-bit hostAlan Modra1-6/+6
2021-12-02aarch64: Add BC instructionRichard Sandiford1-0/+2
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-10/+28
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+33
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+1
2021-12-02aarch64: Provide line info for unclosed sequencesRichard Sandiford2-12/+14
2021-11-30aarch64: Check for register aliases before mnemonicsRichard Sandiford1-33/+29
2021-11-22RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu1-0/+4
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu1-17/+40
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu2-0/+59
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-1/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+78
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