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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:16 +0800 |
| commit | 3b374308d3006407b9571e573e4ccce4e904a4c4 (patch) | |
| tree | 96bfce86a830f793e0ef73924c4b3c1b3788b68a /gas/config | |
| parent | 5fac3f02edacfca458f7eeaaaa33a87e26e0e332 (diff) | |
| download | gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.zip gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.gz gdb-3b374308d3006407b9571e573e4ccce4e904a4c4.tar.bz2 | |
RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-riscv.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 9cc0abf..bb5f6e4 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1179,6 +1179,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; + case 'f': /* Fall through. */ case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; case 'z': break; /* Zero immediate. */ @@ -3191,6 +3192,23 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, imm_expr->X_op = O_absent; continue; + case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, false); + if (((unsigned) (imm_expr->X_add_number) & 0x1fU) + || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2 + || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2) + as_bad (_("improper prefetch offset (%ld)"), + (long) imm_expr->X_add_number); + ip->insn_opcode |= + ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & + ~ 0x1fU); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + default: unknown_riscv_ip_operand: as_fatal (_("internal: unknown argument type `%s'"), |